JPH05102840A - Semiconductor logic device - Google Patents

Abstract

PURPOSE:To provide the semiconductor logic device composed of a source coupled logic (SCFL) circuit used to improve the high frequency characteristic. CONSTITUTION:In the semiconductor logic device provided with a current changeover circuit composed of longitudinally stacked field effect transistors(TRs) 32, 34 and 44, 46 integrated and forming the differential pairs, the gate channel length of a couple of field effect TRs 44, 46 operated by an equal drain-source bias voltage range and forming the differential pair and the gate channel length of a couple of field effect TRs 48, 52 operated by an equal drain-source bias voltage range and forming the differential pair and forming a source follower circuit are set shorter than the gate channel length of the remaining field effect TRs 32, 34.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor logic device including a source-coupled logic circuit, and more particularly to a semiconductor logic device having improved high frequency characteristics.

[0002]

2. Description of the Related Art In recent years, there has been a demand for development of a semiconductor logic device having a high logic processing capability per unit gate and capable of high-speed processing, and gallium arsenide (G) having a high electron mobility.
a source-coupled logic circuit (SCFL) formed of a gallium arsenide metal Schottky junction field-effect transistor (GaAs MESFET) based on aAs) and having a current switching circuit similar to a silicon bipolar emitter-coupled logic circuit (ECL). )It has been known.

FIG. 3 shows a 2-input AND circuit which is an example of such a source coupled logic circuit.

The input signal A and its inverted input signal AB, and the input signal B and its inverted input signal BB are logically ANDed, and a source follower amplifier which amplifies and outputs the logical operation result. ..

The differential logic section includes enhancement type field effect transistors (hereinafter referred to as E type FETs) 2, 4
First differential pair consisting of E-type FETs 6 and 8 second differential pair
, A constant current circuit 10, and load resistors 12 and 14, and the first and second differential pairs vertically connected to the constant current circuit 10 are input signals A and AB. , B, B
By switching the current according to the logical value level of B, the calculation result is the drain contact X, Y of the E-type FETs 6, 8.
Occurs in.

The source follower amplifier is composed of an E-type FET 16,
First source follower circuit composed of Schottky barrier diodes 18, 20 and constant current circuit 22, and E-type FET
24, a Schottky barrier diode 26, 28 and a constant current circuit 30, and a second source follower circuit. The cathode contact of the Schottky barrier diode 20 has an AND output Q having the same logical value as the contact X, and the cathode of the Schottky barrier diode 28. A NAND output QB having the same logical value as that of the contact Y is generated at the contact.

As described above, the SCFL operates by stacking a plurality of differential pairs that switch currents according to input signals in a direction in which currents flow, thereby performing complicated operations at high speed with a single gate configuration. It has an excellent function such as the flexibility of logic with AND-NAND as well as processing, and OR
It is possible to configure other arithmetic circuits such as NOR calculation.

[0008]

In order to obtain high frequency characteristics in such a semiconductor logic device,
It is known that it is effective to increase the transconductance gm by increasing the ratio (W / L) of the gate channel length L to the gate channel width W of each field effect transistor. That is, the transconductance gm of the field-effect transistor has a structure such that the mobility of surface charge is μ, the dielectric constant of the insulator of the gate layer is ε, the thickness of the gate layer is t, the gate channel width is W, and the gate channel length is Let L be

[0009]

[Equation 1]

The increase in the drain current with the increase in the transconductance gm, which is given by the equation (1), enables high-speed charging of the parasitic capacitance of each field effect transistor, thereby improving the response speed.

However, in a circuit for vertically connecting differential pairs as shown in FIG. 3, for example, an E-type FET is used.
In the case of a differential pair consisting of 2 and 4, one E-type FET2
The drain contact of the E-type FET 4 is connected to the resistors 12 and 14 through E-type FETs 6 and 8 that are vertically stacked, while the drain contact of the other E-type FET 4 is directly connected to the resistor 14, and clearly The voltage applied between the drain and source of the E-type FET 2 is higher than the voltage applied between the drain and the source of the E-type FET 2. From this, the E-type FET2,
If the gate channel length L is too short in order to increase the transconductance gm of No. 4, the drain.
Due to the influence of the difference in the source-to-source voltage, the operating characteristics of the E-type FETs 2 and 4 vary, which causes a problem that the function of the differential pair cannot be exhibited.

That is, the characteristic of the drain-source voltage V _DS vs. the drain current I _D of the E-type FET designed to have a sufficient gate channel length L is as shown in FIG. E type FET with L designed short
The characteristics of the drain-source voltage V _DS vs. the drain current I _D of FIG. 5 become the characteristics shown in FIG. 5 because the so-called short channel effect becomes more prominent as the drain-source voltage V _DS increases. Therefore, in the case of a differential pair composed of a pair of E-type FETs having the characteristics shown in FIG. 4, each drain-source voltage V
_{Even if the DS} is different, the variation as a differential pair can be sufficiently suppressed, but in the case of a differential pair composed of a pair of E-type FETs having the characteristics shown in FIG. 5, each drain / source is The influence of the difference in the voltage V _DS between the drain current I _D
Therefore, an appropriate current switching operation is not performed, and the function as a differential pair cannot be exerted.

Further, not only the field effect transistor which constitutes a differential pair, but also the field effect transistor which requires an operation with uniform characteristics brings about the same problem.

The present invention can improve the high frequency characteristic by increasing the transconductance by shortening the gate channel length, but on the other hand, by improving the problem that the short channel effect causes malfunction. SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor logic device capable of realizing high frequency characteristics without impairing the effect of improving the response speed by shortening the gate channel length.

[0015]

In order to achieve such an object, the present invention provides a SCFL including a current switching circuit configured by vertically connecting a pair of field effect transistors forming a differential pair. In a semiconductor logic device consisting of, in the field effect transistors forming the differential pair, the gate channel length of the field effect transistors operating in the same drain-source bias voltage range is set within a range in which the short channel effect does not have a large influence. In this, it was made shorter than the gate channel length of other field effect transistors.

Further, a field effect transistor forming a source follower circuit for power-amplifying and outputting the positive logic operation output generated in the current switching circuit, and power-amplification and output of the inverted logic operation output generated in the current switching circuit. The gate channel length of the field effect transistor forming the source follower circuit is made shorter than the gate channel length of the field effect transistor forming the current switching circuit within the range where the short channel effect does not seriously affect.

[0017]

According to the semiconductor logic device of the present invention having such a configuration, a pair of field effect transistors forming a differential pair that operate at the same drain-source bias voltage and the same drain-source bias. Limiting the pair of field-effect transistors that compose a source-follower circuit that operates by voltage, by shortening the gate channel, the field-effect transistors that are in a pair relationship with each other operate under the same operating conditions. It is possible to improve the transconductance of each field effect transistor and to improve the high frequency characteristics of the semiconductor logic device as a whole, without causing a variation in the operating characteristics.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. It should be noted that this embodiment is a 2-input AND circuit composed of SCFL.

In FIG. 1, the E-type FETs 32 and 34 form a first differential pair, the common source contact of which is connected to the power supply terminal 38 on the low voltage Vss side through the constant current circuit 36, and one E is connected. The drain contact of the FET 34 is connected to the power supply terminal 42 on the high voltage _VDD side through the resistor 40.

The drain contact of the other E-type FET 32 is connected to the common source contact of the E-type FETs 44 and 46 forming the second differential pair, and the drain contact of one E-type FET 44 is connected through the resistor 40. E-type FET 5 which is connected to the power supply terminal 42 and constitutes the first source follower circuit.
The drain contact of the other E-type FET 46 is connected to the power supply terminal 42 via the resistor 50, and the E-type FET 4 constituting the second source follower circuit
8 gate contacts.

The drain contact of the E-type FET 48 is connected to the power supply terminal V _DD , and the source contact thereof is connected to the level shifting diodes 54 and 56 connected in series with each other, and the cathode contact of the diode 56 is a constant current. It is connected to the power supply terminal 38 via the circuit 58.

Similarly, in the E-type FET 52, the drain contact is connected to the power supply terminal V _DD , the source contact is connected to the level shift diodes 60 and 62 connected in series with each other, and the cathode contact of the diode 62 is also connected. Is connected to the power supply terminal 38 via the constant current circuit 64.

Here, a pair of E-shaped FEs forming a differential pair
Since both T44 and T46 have the same bias voltage range between the drain and the source, the transconductance gm can be improved by designing the gate channel length as short as possible within the range where the adverse effect of the short channel effect is not significant. Has been planned.

Further, an E type FE which constitutes a source follower circuit
Similarly, T48 and 52 have the same drain-source bias voltage range. Therefore, by designing the gate channel length as short as possible within the range where the short channel effect does not occur, the transconductance gm can be improved. Has been.

On the other hand, a pair of E-type FETs forming a differential pair
32 and 34 are the drain and source of the E-type FET 34 compared with the bias voltage range between the drain and source of the E-type FET 32.
Since the bias voltage range between the sources is larger, the E-type FET 34 is used in order to suppress variations in mutual operation characteristics.
Is designed so that the short channel effect is not generated, and the gate channel of the E-type FET 32 is also set to the same length as the gate channel of the E-type FET 34.

Therefore, the gate channel lengths of a pair of E-type FETs operating in the same drain-source bias voltage range are designed to be shorter than the gate channel lengths of the other E-type FETs.

Further, the bias and constant current circuits 36, 58, 64 are arranged so that the entire circuit shown in FIG. 1 operates in the saturation region.
The current value is set, and further, by applying a gallium arsenide metal Schottky junction field effect transistor to these E-type FETs, high-speed processing is realized.

The input signal A is applied to the gate contact of the E-type FET 44, its inverted input signal AB is applied to the gate contact of the E-type FET 46, and the input signal B is applied to the gate contact of the E-type FET 32.
When the inverted input signal BB is applied to the gate contact of the E-type FET 34, a positive logic operation result is generated at the drain contact X of the E-type FET 46 and an inverted logic operation result is generated at the drain contact Y of the E-type FET 44. AND output Q formed by power amplification of the calculation result of the contact X is a cathode contact of the diode 56, and NAN formed by power amplification of the calculation result of the contact Y.
The D output QB is output to the cathode contact of the diode 62.

Next, the operation of the SCFL having such a configuration will be described.

First, when the input signals A and B are both logical "H" and the inverted input signals AB and BB are both logical "L", the E-type FETs 32 and 44 are turned on and the E-type FETs 34 and 46 are turned on. Is turned off, a voltage drop does not occur in the resistor 50, and a voltage drop occurs in the resistor 40. Therefore, the contact X has a logical value “H”, the contact Y has a logical value “L”, and the output signal Q has a logical value. The output signal QB becomes "H" and the logical value becomes "L".

On the contrary, when the input signals A and B are both logical value "L" and the inverted input signals AB and BB are both logical value "H", the E type FETs 32 and 44 are off and the E type FET 34, 46 is turned on, a voltage drop occurs in the resistor 50, and no voltage drop occurs in the resistor 40.
Is a logical value "L", the contact Y is a logical value "H", the output signal Q is a logical value "L", and the output signal QB is a logical value "H".

Next, when the input signal A and the inverted input signal BB are the logical value "L" and the input signal B and the inverted input signal AB are the logical value "H", the E type FETs 32 and 46 are turned on and the E type FET is turned on. Since the FETs 34 and 44 are turned off and a voltage drop occurs in the resistor 50 and no voltage drop occurs in the resistor 40, the contact X has a logical value "L", the contact Y has a logical value "H", and the output signal Q Is a logical value "L", and the output signal QB is a logical value "H".

Further, when the input signal A and the inverted input signal BB have the logical value "H" and the input signal B and the inverted input signal AB have the logical value "L", the E type FETs 34 and 44 are turned on and the E type FET 32 is turned on. , 46 are turned off, a voltage drop occurs in the resistor 50, and a voltage drop does not occur in the resistor 40. Therefore, the contact X has a logical value “L”, the contact Y has a logical value “H”, and the output signal Q is The logical value is "L" and the output signal QB is the logical value "H".

The above operation is summarized in a function table as shown in FIG.

As described above, according to the SCFL of this embodiment, the transconductance gm is improved by shortening the gate channel lengths of the E-type FETs 44 and 46 that form the differential pair, and the differential pair is connected thereto. E type F to compose
The characteristics of the differential pair are maintained by increasing the gate channel length of the ETs 32 and 34, and further, the mutual conductance gm is improved by shortening the gate lengths of the E-type FETs 48 and 52 forming the source follower circuit. Since it is configured, it is possible to improve the high frequency characteristics without degrading the characteristics of the entire circuit.

In the above-mentioned embodiments, all the field effect transistors are of the E type, but the present invention is not limited to this, and the depletion type (D type) is appropriately used as necessary. ) Can be used.

[0037]

As described above, according to the semiconductor logic device of the present invention, a pair of field-effect transistors forming a differential pair operating at the same drain-source bias voltage and the same drain-source. Since the gate channel is shortened only for the pair of field effect transistors that compose the source follower circuit that operates with the inter-bias voltage, the field effect transistors that are paired with each other operate under the same operating conditions. It is possible to improve the high-frequency characteristics of the entire semiconductor logic device by improving the transconductance of each field effect transistor without causing variations in operating characteristics as in the conventional case.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor logic device of the present invention.

FIG. 2 is a function table for explaining the operation of one embodiment.

FIG. 3 is a circuit diagram showing an example of a conventional semiconductor logic device.

FIG. 4 is an explanatory diagram showing characteristics of an enhancement type field effect transistor.

FIG. 5 is an explanatory diagram showing another characteristic of the enhancement-type field effect transistor.

[Explanation of symbols]

32, 34, 44, 46, 48, 52 ... E-type FET 36, 58, 64 ... Constant current circuit, 38, 42 ... Power supply terminal, 40, 50 ... Resistor 54, 56, 60, 62 ... Level shift diode

Claims (3)

[Claims] 1. A pair of field effect transistors forming a differential pair are vertically connected in a plurality of stages, and a logical operation is performed by a current switching operation according to an input signal applied to a gate contact of a predetermined field effect transistor. Of the pair of field effect transistors having a current switching circuit, the field effect transistors having the same bias voltage range between the drain and the source among the pair of field effect transistors, and the gate channel length of the remaining field effect transistors. A semiconductor logic device with a shorter structure. 2. A positive logic operation is performed by vertically connecting a pair of field effect transistors forming a differential pair and switching the current according to an input signal applied to a gate contact of a predetermined field effect transistor. A source follower circuit having a pair of field effect transistors for respectively amplifying the positive logic operation result of the current switch circuit and the inverted logic operation result thereof by power amplification. A semiconductor logic device having a structure in which the gate channel length of a pair of field effect transistors in a circuit is shorter than the gate channel lengths of the remaining field effect transistors. 3. The semiconductor logic device according to claim 1, wherein all the field effect transistors are gallium arsenide metal Schottky junction field effect transistors.