JPH05102424A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05102424A JPH05102424A JP3281884A JP28188491A JPH05102424A JP H05102424 A JPH05102424 A JP H05102424A JP 3281884 A JP3281884 A JP 3281884A JP 28188491 A JP28188491 A JP 28188491A JP H05102424 A JPH05102424 A JP H05102424A
- Authority
- JP
- Japan
- Prior art keywords
- film
- rapid thermal
- nitride film
- atmosphere
- thermal nitriding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体装置の製造方法
に関し、特にＤＲＡＭ(Dynamic Random Acc-ess Memor
y）などにおけるキャパシタ絶縁膜の製造方法に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly to a DRAM (Dynamic Random Acc-ess Memor).
The present invention relates to a method for manufacturing a capacitor insulating film in y).
【０００２】[0002]
【従来の技術】今日、ＤＲＡＭのキャパシタ絶縁膜は、
ＬＰＣＶＤ（low pressure chemicalvapour depositi
n）法によるSi3N4 膜（シリコン窒化膜）と、それを酸
化して得られるSiO2膜（シリコン酸化膜）からなる積層
絶縁膜が広く用いられている。この積層絶縁膜は、実際
は、Si3N4 膜と下層電極の間の界面にSiO2膜を有し、Si
O2膜−Si3N4 膜−SiO2膜の３層構造になっている。下層
のSiO2膜は、洗浄中、乾燥中、あるいは、Si3N4 膜を形
成する時に成長するが、膜質は良好でなく、できるだけ
成長を抑える方がよい。その１つの方法として、下層電
極に対してNH3 （アンモニア）を用いた急速熱窒化処理
（ＲＴＮ；Rapid Thermal Nitriolation）を行い、それ
からSi3N4 膜を形成する方法が用いられている。すなわ
ち、下層電極に対してＲＴＮを実施すると、それまでの
洗浄中および乾燥中に成長したSiO2膜はSiON膜（シリコ
ン窒化膜）に変換され、すると、その後のSiO2膜の成長
も抑えられるのである。この方法によると、ＲＴＮを行
わない場合に比べリーク電流は減少し、経時絶縁膜破壊
特性（ＴＤＤＢ；Time Depondent Dielectric Breakdow
n 特性）も向上する。2. Description of the Related Art Today, DRAM capacitor insulating films are
LPCVD (low pressure chemical vapor depositi
A laminated insulating film composed of a Si 3 N 4 film (silicon nitride film) by the n) method and a SiO 2 film (silicon oxide film) obtained by oxidizing the same is widely used. This laminated insulating film actually has a SiO 2 film at the interface between the Si 3 N 4 film and the lower electrode.
It has a three-layer structure of O 2 film-Si 3 N 4 film-SiO 2 film. The lower SiO 2 film grows during cleaning, drying, or when the Si 3 N 4 film is formed, but the film quality is not good and it is better to suppress the growth as much as possible. As one of the methods, a method of performing rapid thermal nitridation (RTN; Rapid Thermal Nitriolation) using NH 3 (ammonia) on the lower layer electrode and then forming a Si 3 N 4 film is used. That is, when RTN is performed on the lower electrode, the SiO 2 film grown during the cleaning and drying until then is converted into a SiON film (silicon nitride film), and the growth of the SiO 2 film thereafter is also suppressed. Of. According to this method, the leakage current is reduced as compared with the case where RTN is not performed, and the time-dependent dielectric breakdown characteristic (TDDB)
n characteristics) are also improved.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、以上述
べた方法であっても、Si3N4 膜膜厚が５０Å以下になる
と、ＲＴＮも行わないよりはその割合は小さいが、リー
ク電流が増加し、ＴＤＤＢ特性も劣化する。その結果、
充分な電荷保持が得られず、デバイス特性の劣化、歩留
りの低下という問題を生じる。However, even with the method described above, when the Si 3 N 4 film thickness is 50 Å or less, the ratio is smaller than that without RTN, but the leak current increases. , TDDB characteristics are also deteriorated. as a result,
Sufficient charge retention cannot be obtained, which causes problems of deterioration of device characteristics and reduction of yield.
【０００４】この発明は上記の点に鑑みなされたもの
で、窒化膜膜厚が５０Å以下になってもリーク電流の増
加、ＴＤＤＢ特性の劣化を防止できる高信頼性のキャパ
シタ絶縁膜を形成できる半導体装置の製造方法を提供す
ることを目的とする。The present invention has been made in view of the above points, and a semiconductor capable of forming a highly reliable capacitor insulating film capable of preventing an increase in leak current and deterioration of TDDB characteristics even when the film thickness of the nitride film is 50 Å or less. An object is to provide a method for manufacturing a device.
【０００５】[0005]
【課題を解決するための手段】この発明では、キャパシ
タ絶縁膜の形成工程を次の通りとする。まず下層電極に
対してアンモニア雰囲気中で急速熱窒化処理を行ってか
ら窒化膜を形成し、その窒化膜の表面を酸化して酸化膜
を形成後、再びアンモニア雰囲気中で急速熱窒化処理、
または不活性ガス雰囲気中で急速熱処理を行う。According to the present invention, the steps of forming a capacitor insulating film are as follows. First, the lower electrode is subjected to rapid thermal nitriding treatment in an ammonia atmosphere, then a nitride film is formed, the surface of the nitride film is oxidized to form an oxide film, and then rapid thermal nitriding treatment is again performed in the ammonia atmosphere.
Alternatively, rapid thermal processing is performed in an inert gas atmosphere.
【０００６】[0006]
【作用】上記この発明においては、窒化膜の形成前にア
ンモニア雰囲気中で急速熱窒化処理を行い、さらに酸化
膜の形成後、再びアンモニア雰囲気中で急速熱窒化処
理、または不活性ガス雰囲気中で急速熱処理を行うよう
にしたので、例え窒化膜が５０Å以下と薄くても、リー
ク電流が減少し、ＴＤＤＢ特性も改善される。その理由
は明白ではないが、上記２回の処理により、窒化膜と下
層膜（酸窒化膜）の界面および、窒化膜と上層膜（酸窒
化膜または酸化膜）の界面、特に前者の下層膜側での界
面が安定するからと思われる。In the above invention, the rapid thermal nitriding treatment is performed in the ammonia atmosphere before forming the nitride film, and after the oxide film is further formed, the rapid thermal nitriding treatment is performed again in the ammonia atmosphere or in the inert gas atmosphere. Since the rapid thermal processing is performed, the leak current is reduced and the TDDB characteristics are improved even if the nitride film is as thin as 50 Å or less. The reason for this is not clear, but by the above two treatments, the interface between the nitride film and the lower film (oxynitride film) and the interface between the nitride film and the upper film (oxynitride film or oxide film), particularly the former lower film It seems that the interface on the side is stable.
【０００７】[0007]
【実施例】以下この発明の一実施例を図面を参照して説
明する。図１はこの発明の一実施例を示す図であり、Ｄ
ＲＡＭにおけるキャパシタ部分を抜き出したものであ
る。図１（ａ）において、１１は下層電極としてのポリ
シリコン層であり、このポリシリコン層１１にＰ（リ
ン）もしくはＡｓ（ヒ素）の不純物を拡散後、８５０〜
１０００℃の温度、３０〜６０秒の時間、NH3 中で急速
熱窒化処理（ＲＴＮ）を行う。このＲＴＮにより、ポリ
シリコン層１１の表面に形成されていたシリコン酸化膜
はシリコン酸窒化膜（SiON膜）１２となり、すると、そ
の後のシリコン酸化膜の成長も抑えられる。その後、Si
ON膜１２を挾んでポリシリコン層１１上にＬＰＣＶＤ法
によりシリコン窒化膜（Si3N4 膜）１３を３０〜６０Å
堆積させる。その後、８００〜９５０℃の温度で、Ｈ2
（水素）＋Ｏ2 （酸素）の混合雰囲気中で１０〜６０分
アニールを行い、前記Si3N4 膜１３の表面にシリコン酸
化膜（SiO2膜）１４を形成する。その後、再度８５０〜
１０００℃の温度、３０〜６０秒の時間、NH3 雰囲気中
で急速熱窒化処理（ＲＴＮ）を行う。このＲＴＮによ
り、前記SiO2膜１４は、図１（ｂ）に示すようにシリコ
ン酸窒化膜（SiON膜）１５となる。その後、このSiON膜
１５上に上層電極としてのポリシリコン層１６を形成
し、不純物としてＰやＡｓを拡散させる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an embodiment of the present invention, in which D
This is an extraction of the capacitor part in the RAM. In FIG. 1A, reference numeral 11 denotes a polysilicon layer as a lower electrode, which is diffused into the polysilicon layer 11 with an impurity of P (phosphorus) or As (arsenic) and then 850 to 850.
Rapid thermal nitridation (RTN) is performed in NH 3 at a temperature of 1000 ° C. for a time of 30 to 60 seconds. Due to this RTN, the silicon oxide film formed on the surface of the polysilicon layer 11 becomes a silicon oxynitride film (SiON film) 12, and then the growth of the silicon oxide film is also suppressed. Then Si
The silicon nitride film (Si 3 N 4 film) 13 is sandwiched between the ON film 12 and the polysilicon layer 11 by the LPCVD method to 30 to 60Å
To deposit. Then, at a temperature of 800 to 950 ° C., H 2
Annealing is performed for 10 to 60 minutes in a mixed atmosphere of (hydrogen) + O 2 (oxygen) to form a silicon oxide film (SiO 2 film) 14 on the surface of the Si 3 N 4 film 13. Then again 850
Rapid thermal nitriding treatment (RTN) is performed in a NH 3 atmosphere at a temperature of 1000 ° C. for 30 to 60 seconds. Due to this RTN, the SiO 2 film 14 becomes a silicon oxynitride film (SiON film) 15 as shown in FIG. Then, a polysilicon layer 16 as an upper layer electrode is formed on the SiON film 15, and P and As are diffused as impurities.
【０００８】図２は、以上のようにして形成されたキャ
パシタ絶縁膜（SiON膜１２／Si3N4 膜１３／SiON膜１５
の３層構造）の定電圧ＴＤＤＢ特性を示す。この発明の
一実施例のように、ＲＴＮを２回行うことにより、Si3N
4 膜１３の膜厚が酸化膜換算膜厚で４７Åと薄くても、
ＴＤＤＢ特性は大きく改善される。すなわち、この発明
の一実施例によれば、３種類の従来例に比較して印加電
界を大きくでき、かつ寿命を延ばすことができている。FIG. 2 shows the capacitor insulating film (SiON film 12 / Si 3 N 4 film 13 / SiON film 15) formed as described above.
Constant voltage TDDB characteristics of the three-layer structure of FIG. By performing RTN twice as in the embodiment of the present invention, Si 3 N
4 Even if the film thickness of the film 13 is as thin as 47 Å in terms of oxide film,
The TDDB characteristics are greatly improved. That is, according to one embodiment of the present invention, the applied electric field can be increased and the life can be extended as compared with the three types of conventional examples.
【０００９】なお、ＲＴＮを２度行うと、なぜこのよう
に特性改善が図られるかは明確に解明されていないが、
２回のＲＴＮにより、SiON膜１２とSi3N4 膜１３の界面
および、Si3N4 膜１３とSiON膜１５の界面、特にSiON膜
１２とSi3N4 膜１３の界面が安定したからと考えられ
る。Although it is not clearly understood why the characteristics are improved in this way when RTN is performed twice,
By the two RTNs, the interface between the SiON film 12 and the Si 3 N 4 film 13 and the interface between the Si 3 N 4 film 13 and the SiON film 15, especially the interface between the SiON film 12 and the Si 3 N 4 film 13 were stabilized. it is conceivable that.
【００１０】なお、上記一実施例では、SiO2膜１４形成
後、再びNH3 雰囲気中でＲＴＮを行ったが、これを不活
性ガス雰囲気中での急速ランプアニール（ＲＴＡ;Rapid
Th-armal Anneal）としてもよく、その場合も上記一実
施例と同様の効果を得ることができる。ＲＴＡの場合の
温度、時間の具体的数値はＲＴＮの場合と同一である。
なお、ＲＴＡの場合は、SiO2膜１４は、SiO2のままとな
り、SiON膜に変換はされない。In the above embodiment, RTN was performed again in the NH 3 atmosphere after the SiO 2 film 14 was formed. However, this is subjected to rapid lamp annealing (RTA; Rapid) in an inert gas atmosphere.
Th-armal Anneal), and in that case, the same effect as in the above-described one embodiment can be obtained. Specific values of temperature and time in the case of RTA are the same as those in the case of RTN.
In the case of RTA, the SiO 2 film 14 remains as SiO 2 and is not converted to a SiON film.
【００１１】[0011]
【発明の効果】以上詳細に説明したように、この発明に
よれば、キャパシタ絶縁膜の形成工程において、窒化膜
形成前にアンモニア雰囲気中で急速熱窒化処理を行い、
さらに窒化膜上に酸化膜を形成後に再びアンモニア雰囲
気中で急速熱窒化処理、または不活性ガス雰囲気中で急
速熱処理を行うようにしたので、例え窒化膜の膜厚が５
０Å以下と薄くても、キャパシタ絶縁膜の経時絶縁破壊
特性を改善でき、リーク電流も減少でき、信頼性の高い
キャパシタ絶縁膜を形成できる。その結果、充分な電荷
保持能力のキャパシタが得られ、デバイス特性および歩
留りの向上を図ることができる。As described in detail above, according to the present invention, in the step of forming the capacitor insulating film, the rapid thermal nitriding treatment is performed in the ammonia atmosphere before the formation of the nitride film,
Further, after forming the oxide film on the nitride film, the rapid thermal nitriding process is performed again in the ammonia atmosphere or the rapid thermal annealing process is performed in the inert gas atmosphere.
Even if it is as thin as 0 Å or less, the dielectric breakdown characteristics of the capacitor insulating film over time can be improved, the leakage current can be reduced, and a highly reliable capacitor insulating film can be formed. As a result, a capacitor having a sufficient charge retention ability can be obtained, and device characteristics and yield can be improved.
【図１】この発明の一実施例を示す工程断面図である。FIG. 1 is a process sectional view showing an embodiment of the present invention.
【図２】この発明の一実施例と従来の方法とによるＴＤ
ＤＢ特性を示す特性図である。FIG. 2 shows a TD according to an embodiment of the present invention and a conventional method.
It is a characteristic view which shows DB characteristic.
１１ ポリシリコン層 １２ SiON膜 １３ Si3N4 膜 １４ SiO2膜 １５ SiON膜11 polysilicon layer 12 SiON film 13 Si 3 N 4 film 14 SiO 2 film 15 SiON film
Claims (1)
急速熱窒化処理を行う工程、 下層電極上に窒化膜を形成する工程、 前記窒化膜を酸化して表面に酸化膜を形成する工程、 再度アンモニア雰囲気中で急速熱窒化処理を行う、また
は不活性ガス雰囲気中で急速熱処理を行う工程、 をキャパシタ絶縁膜の形成工程として順次行うことを特
徴とする半導体装置の製造方法。1. A step of performing rapid thermal nitriding treatment on the lower layer electrode in an ammonia atmosphere, a step of forming a nitride film on the lower layer electrode, a step of oxidizing the nitride film to form an oxide film on the surface, A method of manufacturing a semiconductor device, characterized in that rapid thermal nitriding treatment in an ammonia atmosphere or rapid thermal annealing treatment in an inert gas atmosphere is sequentially performed as a capacitor insulating film forming step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3281884A JP3048445B2 (en) | 1991-10-03 | 1991-10-03 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3281884A JP3048445B2 (en) | 1991-10-03 | 1991-10-03 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05102424A true JPH05102424A (en) | 1993-04-23 |
| JP3048445B2 JP3048445B2 (en) | 2000-06-05 |
Family
ID=17645314
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3281884A Expired - Fee Related JP3048445B2 (en) | 1991-10-03 | 1991-10-03 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3048445B2 (en) |
-
1991
- 1991-10-03 JP JP3281884A patent/JP3048445B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP3048445B2 (en) | 2000-06-05 |
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