JPH05102205A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPH05102205A
JPH05102205A JP25789491A JP25789491A JPH05102205A JP H05102205 A JPH05102205 A JP H05102205A JP 25789491 A JP25789491 A JP 25789491A JP 25789491 A JP25789491 A JP 25789491A JP H05102205 A JPH05102205 A JP H05102205A
Authority
JP
Japan
Prior art keywords
die pad
integrated circuit
axis
circuit chip
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25789491A
Other languages
Japanese (ja)
Inventor
Kazuhiko Suzuki
和彦 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP25789491A priority Critical patent/JPH05102205A/en
Publication of JPH05102205A publication Critical patent/JPH05102205A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01039Yttrium [Y]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To contrive improvement both in working capability in a die-attaching process and in judgement of the mounting and fixing position of a chip by a method wherein a half-etching section is provided on the chip-mounting surface of a die pad. CONSTITUTION:Long and narrow half-etching sections 7a to 7d are provided along X-and Y-axes on an almost square-shaped die pad 1 to be used to mount an integrated circuit chips. In a die-attaching process, the center of the die pad 1 and the center of an integrated circuit chip 4 are judged by the eye measurement of the operator from the shape of the half-etching parts 7a to 7d, the X-axis and the Y-axis of the die pad 1 and the integrated circuit chip 4, which orthogonally intersect at the above-mentioned centers, are brought in coincidence with each other, and as a result, the position of the integrated circuit chip 4, which is placed and fixed on the die pad 1, can be determined. Accordingly, the judging period of the operator, namely, the period required for manufacture, can be cut down, and at the same time, the generation of short circuit between wires and between the wire and the die pad can be prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、主に樹脂封止型の半導
体装置の外部リード付け組立に使用されるリードフレー
ムに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame mainly used for external lead assembly of a resin-sealed semiconductor device.

【0002】[0002]

【従来の技術】リードフレームを用いた集積回路の組立
においては、前記ダイパッドの集積回路チップ搭載面に
集積回路チップを接着剤を用いて載置固着される、ダイ
アタッチが実施される。
2. Description of the Related Art In assembling an integrated circuit using a lead frame, die attachment is carried out in which the integrated circuit chip is mounted and fixed on an integrated circuit chip mounting surface of the die pad with an adhesive.

【0003】図3は、前記リードフレームのダイパッド
部の平面図であり、図において、ダイパッド部1はフラ
ットな板体であって、ダイアタッチが施される際の前記
集積回路チップが載置固着される位置は、作業者が集積
回路チップ形状からその中心を、またダイパッド形状か
らダイパッドの中心を目測で判断し、前記2つのそれぞ
れの中心を通り、その中心で直交するX軸,Y軸を一致
させることにより決定している。
FIG. 3 is a plan view of the die pad portion of the lead frame. In the figure, the die pad portion 1 is a flat plate, and the integrated circuit chip is mounted and fixed when die attachment is performed. The operator visually determines the center of the integrated circuit chip shape and the center of the die pad from the die pad shape, passes the respective two centers, and determines the X-axis and the Y-axis orthogonal to the center. It is decided by matching.

【0004】[0004]

【発明が解決しようとする課題】近年、半導体装置の機
能増大にともない、集積回路の入出力端子数の増加に対
する要求が急激に高まってきており、200ピンを越え
る半導体装置も多数できている。
In recent years, as the functions of semiconductor devices have increased, the demand for an increase in the number of input / output terminals of an integrated circuit has rapidly increased, and many semiconductor devices having more than 200 pins have been made.

【0005】それに比例し、前記集積回路チップ上に設
けられているパッドの微細化も進み、またリードフレー
ムのインナーリード部の多ピン化も進められている。
In proportion to this, miniaturization of the pads provided on the integrated circuit chip is progressing, and the number of pins of the inner lead portion of the lead frame is increasing.

【0006】その結果、前記従来技術によるダイアタッ
チ工程における集積回路チップの載置固着位置を決定す
る方法では、図4に示したように集積回路チップ4のそ
れぞれのX軸,Y軸が一致しないようにダイアタッチ工
程で載置固着されると、集積回路チップ上のパット6
a,6bからインナーリード5a,5bにそれぞれワイ
ヤーボンディングされたワイヤー3aと3bが交差し、
回路を流れる電流がショートしてしまったり、図5に示
したように集積回路チップ4がダイパッド1の集積回路
チップ搭載面の一部方向に片寄って載置固着されると、
集積回路チップ上のパット6c,6dからインナーリー
ド5c,5dにそれぞれワイヤーボンディングされたワ
イヤー3c,3dの長さが規格以上に長くなり、図6の
ように他電位のリードフレーム部(ダイパッド1)に接
触してしまうなどの問題が生じた。したがって、以上の
問題を克服し、ダイアタッチ工程を迅速かつ確実に認識
することのできる集積回路用リードフレームを提供する
ことが強く望まれた。
As a result, in the method of determining the mounting and fixing position of the integrated circuit chip in the die attach process according to the above-mentioned conventional technique, the X axis and the Y axis of the integrated circuit chip 4 do not match as shown in FIG. When it is mounted and fixed in the die attach process, the pad 6 on the integrated circuit chip is
The wires 3a and 3b, which are wire-bonded from a and 6b to the inner leads 5a and 5b, respectively intersect,
If the current flowing through the circuit is short-circuited or the integrated circuit chip 4 is placed and fixed while being offset toward a part of the integrated circuit chip mounting surface of the die pad 1 as shown in FIG.
The lengths of the wires 3c and 3d wire-bonded from the pads 6c and 6d on the integrated circuit chip to the inner leads 5c and 5d become longer than the standard, and the lead frame portion (die pad 1) of another potential as shown in FIG. There was a problem such as contact with. Therefore, it has been strongly desired to provide a lead frame for an integrated circuit, which can overcome the above problems and can quickly and surely recognize the die attach process.

【0007】[0007]

【課題を解決するための手段】本発明のリードフレーム
は、集積回路チップを搭載する略四角形のダイパッド
と、前記ダイパッドの周縁に配置され、一端をダイパッ
ドに向けたインナーリードによって構成されるリードフ
レームにおいて、前記ダイパッドの集積回路チップ搭載
面にその中心で互いに直交するX軸,Y軸によって区切
られた4つの象限にそれぞれがX軸,Y軸に対して他の
象限にあるものと対象になるようにハーフエッチング部
を設けたことを特徴とする。
A lead frame according to the present invention comprises a substantially square die pad on which an integrated circuit chip is mounted, and an inner lead which is arranged on the periphery of the die pad and has one end facing the die pad. , The four quadrants separated by the X-axis and the Y-axis which are orthogonal to each other at the center on the integrated circuit chip mounting surface of the die pad are in the other quadrants with respect to the X-axis and the Y-axis. The half-etched portion is provided as described above.

【0008】[0008]

【作用】本発明は、ダイパッドの外形以外の、ダイパッ
ドの中心を判断する基準となるハーフエッチング部をダ
イパッドのチップ搭載面に設けたことにより、ダイパッ
ド中心が容易にしかも正確に判断でき、ダイアタッチ工
程において作業が迅速かつ正確になるという効果があっ
た。
According to the present invention, the center of the die pad can be easily and accurately determined by providing the half-etched portion other than the outer shape of the die pad, which is a reference for determining the center of the die pad, on the chip mounting surface of the die pad. There was an effect that the work became quick and accurate in the process.

【0009】[0009]

【実施例】以下、本発明の実施例を図1および図2によ
り説明する。
Embodiments of the present invention will be described below with reference to FIGS.

【0010】図1は、本発明の一実施例を示すダイパッ
ド部の平面図である。集積回路チップを搭載するための
略四角形のダイパッド1は、その四隅においてダイパッ
ド吊りリード2によって支持されている。
FIG. 1 is a plan view of a die pad portion showing an embodiment of the present invention. A die pad 1 having a substantially rectangular shape for mounting an integrated circuit chip is supported by die pad suspension leads 2 at its four corners.

【0011】略四角形のダイパッド1には、X軸,Y軸
上に沿ったそれぞれ2つの細長いハーフエッチング部7
a〜7dが設けられている。このハーフエッチング部7
a〜7dは、X軸上のものは互いにY軸に対して、Y軸
上のものは互いにX軸に対して対称の位置に設けられて
いる。また、それぞれのハーフエッチング部は同形状で
あり、X軸,Y軸の交点からの距離はすべて等しくなっ
ている。
The die pad 1 having a substantially rectangular shape has two elongated half-etched portions 7 each extending along the X axis and the Y axis.
a to 7d are provided. This half etching part 7
a to 7d are provided at positions symmetrical with respect to the Y axis with respect to each other on the X axis, and with respect to each other with respect to each other on the Y axis. Further, the respective half-etched portions have the same shape, and the distances from the intersections of the X axis and the Y axis are all equal.

【0012】図2もまた、本発明の一実施例のダイパッ
ド部の平面図である。略四角形のダイパッド1には、X
軸,Y軸によって区切られた4つの象限それぞれに1つ
L字型のハーフエッチング部8a〜8dが設けられてい
る。このハーフエッチング部は、それぞれが、X軸,Y
軸に対して対称の位置に設けられている。また、それぞ
れのコーナー部を結んでできる四角形は、ダイパッドの
集積回路搭載面の外形の四角形と同形状である。 ハー
フエッチング部9a〜9dおよび10a〜10dは、ハ
ーフエッチング部8a〜8dと同様、X軸,Y軸によっ
て区切られた4つの象限それぞれに1つ設けられ、その
1つ1つがX軸,Y軸に対して対称の位置に設けられて
いる。それぞれのハーフエッチング部のコーナー部を結
んでできる四角形は、ダイパッドの集積回路搭載面の外
形の四角形と同形状である。
FIG. 2 is also a plan view of the die pad portion according to the embodiment of the present invention. On the substantially square die pad 1, X
One L-shaped half etching portion 8a to 8d is provided in each of the four quadrants divided by the axis and the Y axis. This half-etched part has an X-axis and a Y-axis, respectively.
It is provided in a symmetrical position with respect to the axis. The quadrangle formed by connecting the respective corners has the same shape as the quadrangle of the outer shape of the integrated circuit mounting surface of the die pad. Similar to the half-etched portions 8a-8d, the half-etched portions 9a-9d and 10a-10d are provided in each of the four quadrants divided by the X-axis and the Y-axis, and each one is provided in the X-axis and the Y-axis. It is provided in a symmetrical position with respect to. The quadrangle formed by connecting the corners of the respective half-etched portions has the same shape as the quadrangle of the outer shape of the integrated circuit mounting surface of the die pad.

【0013】本発明は前記ダイアタッチ工程で、このよ
うなハーフエッチング部7a〜7d,8a〜8d,9a
〜9dおよび10a〜10dの形状から作業者がダイパ
ッド1の中心と集積回路チップ4の中心を目測で判断
し、これらの中心で直交するダイパッド1と集積回路チ
ップ4のそれぞれのX軸,Y軸を一致させることによ
り、ダイパッド1に載置固着する集積回路チップ4の位
置を決定する。
In the die attach step of the present invention, the half-etched portions 7a to 7d, 8a to 8d and 9a are formed.
9d and 10a to 10d, the operator visually judges the center of the die pad 1 and the center of the integrated circuit chip 4, and the X-axis and the Y-axis of the die pad 1 and the integrated circuit chip 4 which are orthogonal to each other at these centers are determined. The positions of the integrated circuit chips 4 to be mounted and fixed on the die pad 1 are determined by matching the above.

【0014】[0014]

【発明の効果】以上述べたように、本発明において、ダ
イパッド上に、X軸,Y軸によって区切られた4つの象
限に、その1つ1つがX軸,Y軸に対して対称であるハ
ーフエッチング部を設けることにより、前記ダイアタッ
チ工程において、作業者の認識時間つまり製造時間が短
縮されるのと同時に、ダイパッドへ載置固着する集積回
路チップの位置が正確に決定できるため、ワイヤー間の
ショート、ワイヤーとダイパッドのショートといった不
良発生を防止するという優れた効果がある。(従来技術
ではダイパッドの中心と集積回路チップの中心のずれ
が、半径約0.30mmなのが、本発明により約0.1
5mmになった。)
As described above, according to the present invention, on the die pad, in each of the four quadrants separated by the X axis and the Y axis, one half is symmetrical with respect to the X axis and the Y axis. By providing the etching portion, in the die attach step, the recognition time of the operator, that is, the manufacturing time is shortened, and at the same time, the position of the integrated circuit chip mounted and fixed on the die pad can be accurately determined. It has an excellent effect of preventing the occurrence of defects such as a short circuit and a short circuit between the wire and the die pad. (In the prior art, the deviation between the center of the die pad and the center of the integrated circuit chip is about 0.30 mm.
It became 5 mm. )

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示すダイパッド部の平面
図。
FIG. 1 is a plan view of a die pad portion showing an embodiment of the present invention.

【図2】本発明の他の実施例を示すダイパッド部の平面
図。
FIG. 2 is a plan view of a die pad portion showing another embodiment of the present invention.

【図3】ダイパッド部の平面図。FIG. 3 is a plan view of a die pad portion.

【図4】従来技術の一例を示すダイパッド部の平面図。FIG. 4 is a plan view of a die pad portion showing an example of a conventional technique.

【図5】従来技術の他の一例を示すダイパッド部の平面
図。
FIG. 5 is a plan view of a die pad portion showing another example of the conventional technique.

【図6】図5におけるI−I断面図。6 is a sectional view taken along line I-I in FIG.

【符号の説明】[Explanation of symbols]

1 インナーリードのダイパッド部 2 インナーリードの吊り部 3a〜3d ワイヤー 4 集積回路チップ 5a〜5d インナーリード 6a〜6d 集積回路チップ上のパット 7a〜7d ハーフエッチング部 8a〜8d ハーフエッチング部 9a〜9d ハーフエッチング部 10a〜10dハーフエッチング部 1 Inner lead die pad part 2 Inner lead suspension part 3a to 3d Wire 4 Integrated circuit chip 5a to 5d Inner lead 6a to 6d Pad on integrated circuit chip 7a to 7d Half etching part 8a to 8d Half etching part 9a to 9d Half Etching part 10a to 10d Half etching part

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】集積回路チップを搭載する略四角形のダイ
パッドと、前記ダイパッドの周縁に配置され、一端をダ
イパッドに向けたインナーリードによって構成されるリ
ードフレームにおいて、前記ダイパッドの集積回路チッ
プ搭載面にその中心で互いに直交するX軸,Y軸によっ
て区切られた4つの象限に、それぞれがX軸,Y軸に対
して他の象限にあるものと対象になるようにハーフエッ
チング部を設けたことを特徴とするリードフレーム。
1. A lead frame constituted by a substantially rectangular die pad on which an integrated circuit chip is mounted, and an inner lead arranged on the periphery of the die pad and having one end facing the die pad, the integrated circuit chip mounting surface of the die pad. In the four quadrants separated by the X-axis and the Y-axis which are orthogonal to each other at the center, half-etched parts are provided so as to be in contrast with those in the other quadrants with respect to the X-axis and the Y-axis. Characteristic lead frame.
JP25789491A 1991-10-04 1991-10-04 Lead frame Pending JPH05102205A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25789491A JPH05102205A (en) 1991-10-04 1991-10-04 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25789491A JPH05102205A (en) 1991-10-04 1991-10-04 Lead frame

Publications (1)

Publication Number Publication Date
JPH05102205A true JPH05102205A (en) 1993-04-23

Family

ID=17312669

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25789491A Pending JPH05102205A (en) 1991-10-04 1991-10-04 Lead frame

Country Status (1)

Country Link
JP (1) JPH05102205A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010131706A1 (en) * 2009-05-15 2010-11-18 ローム株式会社 Semiconductor device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010131706A1 (en) * 2009-05-15 2010-11-18 ローム株式会社 Semiconductor device
US8680659B2 (en) 2009-05-15 2014-03-25 Rohm Co., Ltd. Semiconductor device
JP5572622B2 (en) * 2009-05-15 2014-08-13 ローム株式会社 Semiconductor device
US9035441B2 (en) 2009-05-15 2015-05-19 Rohm Co., Ltd. Semiconductor device
US9343394B2 (en) 2009-05-15 2016-05-17 Rohm Co., Ltd. Semiconductor device
US9379047B2 (en) 2009-05-15 2016-06-28 Rohm Co., Ltd. Semiconductor device
US9613890B2 (en) 2009-05-15 2017-04-04 Rohm Co., Ltd. Semiconductor device
US9847282B2 (en) 2009-05-15 2017-12-19 Rohm Co., Ltd. Semiconductor device
US9899299B2 (en) 2009-05-15 2018-02-20 Rohm Co., Ltd. Semiconductor device
US10431527B2 (en) 2009-05-15 2019-10-01 Rohm Co., Ltd. Semiconductor device with island and associated leads
US10978379B2 (en) 2009-05-15 2021-04-13 Rohm Co., Ltd. Semiconductor device with island and associated leads

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