JPH05101661A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent noise that is transmitted via a signal line for driving a sense amplifier at the time of a write transmitting cycle to a memory cell. CONSTITUTION:Plural sense amplifiers sharing data registers RG1-RG4, e.g. sense amplifier driving signals SAa and SAb are separated into two systems of SAPL, SANL and SAPR, SANR. The connections of the data registers RG1-RG4 to the sense amplifier SAa-SAz are selectively performed by data transfer signals DTL, DTR. The signal quantity of the sense amplifiers on the selected side at the time of write data transfer is much larger than the other side; but since the sense amplifier driving signals are separated into two systems and operated independently from each other, the transmission of noise is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to an image semiconductor memory device for serially reading and writing data in a memory cell via a register.

[0002]

2. Description of the Related Art Conventionally, a sense amplifier drive signal of this type of image semiconductor memory device is commonly supplied to all sense amplifiers for amplifying data read from memory cells connected to the same word line. It was For the conventional example,
A description will be given with reference to the drawings.

FIG. 7 is a circuit diagram showing a conventional image semiconductor memory device. The memory cells ma to mz are word lines W.
The data selected and held by L is transmitted to the bit lines Da to Dz, respectively. Actually, there are a plurality of word lines, but only one is shown here for the sake of simplification of the description.

The sense amplifiers SAa to SAz are differential type amplifiers, and the bit lines Da to Dz and their anti-phase signal lines D are used.
a (overline) to Dz (overline) are connected. The sense amplifier drive signals SAP and SAN are all sense amplifiers S
The signal is commonly input to Aa to SAz, and the bit lines Da to Dz and the opposite phase signal lines Da (overline) to Dz (overline) (hereinafter,
The bit line pairs are balanced through N-channel transistors T1 to T24 controlled by the bit line precharge signal PDL, respectively, and the power supply voltage (hereinafter,
It is precharged to a half level (hereinafter referred to as VCC) (hereinafter referred to as HVCC).

Further, each bit line pair has Da to Dz, Da (overline) to Dz (overline), N-channel transistor T.
The data register to the data registers RG1 to RG4 are connected via the selection circuit 501 composed of a1, Ta2 to Tz1 and Tz2, and N-channel transistors Ta1, Ta2, Tc1,
Tc2, ..., TW1, TW2, Ty1, Ty2 are controlled by the data transfer signal DTL, while N-channel transistors Tb1, Tb2, Td1, Td2, ..., Tx1, Tx2,
Tz1 and Tz2 are controlled by the data transfer signal DTR. Therefore, either the bit line pair Da, Da (overline) or Db, Db (overline) is connected to the data register R.
Selectively connected to G1.

The same applies to the other data registers RG2 to RG4, and the data register RG2 is a data register R for the bit line pair Dc, Dc (overline) or Dd, Dd (overline).
G3 is a bit line pair DW, DW (overline) or Dx, Dx
The data register RG4 (overline) has a bit line pair Dy,
It corresponds to Dy (overline) or Dz, Dz (overline) respectively, and one of them is selectively connected.

The data registers RG1 to RG4 are connected to the data input / output bus I / O via N-channel transistors T21 to T28.
It is connected to O and I / O buses (hereinafter referred to as I / O buses). The N-channel transistors T21 to T28 connecting the data registers RG1 to RG4 to the I / O bus are controlled by the serial pointer 500, and the data register RG
Only one of 1 to RG4 is connected to the I / O bus.

The serial pointer 500 is a ring counter composed of flip-flops FF1 to FF4,
When the reset signal Reset is set to the high level, only the output of the flip-flop FF is set to the high level, and the other flip-flops FF2 to FF4 are initialized to the low level. After that, shift up is performed in synchronization with the rising edge of the clock CLK, Registers RG1 to RG4 are sequentially I / O
It connects to the O bus and writes or reads data in the data register.

Next, a data transfer cycle between the data registers RG1 to RG4 and the memory cells ma to mz will be described. 9 to 10 are waveform charts showing operation timings in the data transfer cycle of the conventional image semiconductor memory device shown in FIG. 7, and also show the levels of respective signals in consideration.

In the write data transfer cycle (FIG. 9),
From the column data registers RG1 to RG4 to the memory cell m
Data bits are written to a to mz, and the memory cells ma to m are read in the read data transfer cycle (FIG. 10).
Reading from z to the data registers RG1 to RG4 is executed.

In FIGS. 9 to 10, attention is paid to the bit line pair Da, Da (overline) and Db, db (overline), and the data between the data register RG1 and the bit line pair Db, Db (overline). Describes the transfer.

Next, the write data transfer cycle will be described with reference to FIG. In the first stage of the write data transfer cycle, the precharge signal PDL is set to the low level (time t1) and each bit line pair Da to Dz, Da (over line) to D (overline) to D
Stop the balance of z (overline) and supply of HVCL level.

Next, the word line WL is set to the high level, and the data bits held in the memory cells ma to mb are transmitted to the bit lines Da to Db. The data bit held in each memory cell ma to mz is assumed to be low level.

In the next stage, the sense amplifier drive signal SA
P, SAN from HVCC level to power supply level VCC
And slowly shift to the ground level GND to amplify the minute difference potential of the bit line pair. In the write data transfer cycle, prior to activation of the sense amplifier, the data transfer signal DTL is set to the high level for a certain time (time t2),
The data bits held in the data registers RG1 to RG4 are transmitted to the bit line pair Db, Db (overline). After the amplification by the sense amplifiers SAa to SAz is completed (time t3), the word line WL is set to the low level and the precharge signal PDL is set to the high level to end the cycle.

In the normal dynamic RAM, after amplifying the data of the memory cell, the data bit to be written into the memory cell is externally forcibly supplied to the activated sense amplifier, but the write data transfer of the image semiconductor memory device is performed. At some time, the number of sense amplifiers to be written reaches several thousand, so that this method causes a very large through current of the sense amplifiers SAa to SAz, which causes a malfunction. Therefore, it is common to transmit the data bit to be written on the bit line in advance and write the data bit in the memory cell by the sense amplifier.

However, with this method, it is very difficult to set the write level. That is, if the write level is too low, write failure occurs, and if the write level is too high, noise is generated in the adjacent bit line via the inter-bit line capacitance between the adjacent bit lines,
Further, when the potential difference between the bit line pairs exceeds the threshold level (hereinafter referred to as Vt) of the N-channel or P-channel transistor forming the sense amplifier, current flows back to the sense amplifier drive signal line to SAP and SAN, The write data is not transferred until each setting level is changed. The bit line pair Da and Da (overline), which simply amplifies the minute difference potential, causes a large noise and causes a malfunction.

Next, the operation of the read data transfer cycle will be described with reference to FIG. The first half of the cycle is the same as the normal dynamic RAM. In the first stage of the cycle, the precharge signal PDL is set to the low level (time t4), and the bit line balance and the supply of the HVCC level are stopped.

Next, the word line WL is set to the high level (time t5), and the data held in the memory cells ma and mb is transmitted to the bit lines Da and Db. The data bit held in each memory cell is assumed to be low level.

After this, the sense amplifier drive signals SAP, S
AN from HV CC level to power supply level V CC and ground level G
Slowly shift to ND respectively to amplify the minute difference potential of the bit line pair.

When the amplification is completed (time t6), the data transfer signal DTR is set to the high level for a certain period of time, and the data bit of the bit line pair Db, Db (overline) is transmitted to the data registers RG1 to RG4. At this time, the data register RG1
Since the potential difference between the bit line pair Db and Db (overline) becomes slightly smaller due to the data bit already held in ˜RG4, amplification is performed again (time t7).

Finally, the word line WL is set to low level and the precharge signal PDL is set to high level to end the cycle (time t8).

FIG. 8 is a detailed circuit diagram of SAz of the sense amplifier SAa shown in FIG. 7. Each sense amplifier has P-channel transistors TPa1, TPa2, TPb1, TPb2 and N-channel transistors TNa1, TNa2, TNb1,
This is a flip-flop type differential amplifier composed of TNb2. Data bit input / output is from bit line pairs Da, Da (overline), Db, Db (overline), and all sense amplifiers SAa-SAz are activated simultaneously by the shared sense amplifier drive signals SAP, SAN. To be done. Cn1, C
n2 and Cn3 are parasitic capacitances between adjacent bit lines.

[0023]

In the above-mentioned conventional semiconductor memory device, the sense amplifier drive signals SAP and SAN are used.
Is shared by all sense amplifiers that amplify the data of the memory cells connected under the same word line, so that all sense amplifiers are always activated at the same time. Therefore, when the write data is selectively transferred to any one of the bit line pairs of the plurality of sense amplifiers connected to one data register, the bit line capacitance not selected for the data transfer target is set to the inter-bit line capacitance. There is a problem that noise is generated through Cn1 to Cn3 or via the sense amplifier drive signal lines SAP and SAN to cause a malfunction.

[0024]

The gist of the present invention is to provide a plurality of memory cells arranged in rows and columns, a plurality of bit line pairs respectively connected to columns of a plurality of memory cells, and a plurality of bit line pairs. A plurality of sense amplifiers, each of which is activated by a sense amplifier drive signal and differentially amplifies a data bit on the bit line pair, a plurality of data registers, and a plurality of bit line pairs are collectively formed. The bit line pair group is provided between the plurality of bit line pair groups and the plurality of data registers, and one bit line pair is selected from the plurality of bit line pair groups in response to a data transfer signal and connected to the plurality of data registers. In the semiconductor memory device including a selection circuit for controlling the sense amplifier, the sense amplifier drive signal is set to a plurality of systems that can be controlled independently of each other, and It is to activate in multiple strains of the drive signal.

[0025]

In the semiconductor memory device having the above structure, when writing the data bit, the data bit is transferred from the plurality of data registers to the bit line pair designated by the data transfer signal. These data bits are differentially amplified by a plurality of sense amplifiers, but there is a data bit read from a memory cell on the bit line pair not specified by the data transfer signal, and the sense amplifier is Since it is activated by multiple lines of sense amplifier activation signals,
The designated bit line pair and the undesignated bit line are not coupled via the sense amplifier activation signal.

[0026]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a semiconductor memory device according to an embodiment of the present invention. Of the components shown in FIG. 1, memory cells ma to mz and bit line pairs Da and Da (overline) to D
z, Dz (overline), N-channel transistors T1 to T24 controlled by the precharge signal PDL and precharging and balancing the bit line pair to the HVCC level, N-channel transistors Ta1 controlled by the data transfer signals DTL, DTR, A selection circuit 501 composed of 2 to Tz1 and 2; data registers RG1 to RG4; and data registers RG1 to RG4 controlled by the serial pointer 500.
To T21 to T28 and clock signal C for connecting the
Serial pointer 5 composed of flip-flops FF1 to FF4 controlled by LK and reset signal Reset
The configuration of 00 is the same as that of the conventional example, and the description thereof is omitted.

The sense amplifiers SAa to SAz are differential amplifiers, and the bit line pair Da, Da (overline) to Dz, Dz.
Each (overline) is connected as a data input / output line.

This embodiment is different from the conventional example in that the sense amplifier drive signals SAPL and SANL are the sense amplifier SA.
a, SAc to SAw, SAy are commonly input and supplied, while
That is, the sense amplifier drive signals SAPR and SANR are commonly supplied to the sense amplifiers SAb, SAd to SAx and SAz.

FIG. 4 shows the sense amplifiers SAa to SAa in one embodiment.
It is a circuit diagram which shows SAz. Similar to the conventional sense amplifier shown in FIG. 8, P-channel transistors TPa1 and T
Pa2, TPb1, TPb2 and N-channel transistor TN
It is composed of a1, TNa2, TNb1, and TNb2. The difference from the conventional example is that the sense amplifier drive signal is set to SAPL, SA.
It is divided into two systems, NL, SAPR, and SANR, and they can operate independently.

Next, a data transfer cycle between the data registers RG1 to RG4 and the memory cells ma to mz will be described with reference to the drawings. 2 to 3 are waveform charts showing the data transfer operation of the present embodiment, which are also shown in consideration of the level of each signal. Sense amplifier drive signals SAPL, SAP
R, SANL, and SANR correspond to SAP and SAN of the conventional example, and the operation of other control signals is the same as that of the conventional example.

In this embodiment, the sense amplifier drive signal SAP
L, SAPR, SANL, and SANR are data transfer signals D
Since each sense amplifier group selected by TL and DTR is independently controlled, even if the write level to the bit line pair is too large during write data transfer, the sense amplifier that does not perform data transfer via the sense amplifier drive signal can be used. No noise is generated. Therefore, in this embodiment, the sense operation of the sense amplifier that does not perform data transfer can be released from noises via the drive signals (SAPL / R, SANL / R), and stable operation can be realized.

5 and 6 are waveform charts showing the operation timing of another embodiment of the semiconductor memory device of the present invention.

This embodiment is different from the above-mentioned embodiment in that sense amplifier drive signals SAPL and S in the write data transfer cycle.
APR, SANL, SANR, data transfer signal DTL,
Different in DTR operation. That is, the operation timings of the sense amplifier drive signals SAPR and SANR on the side selected by the data transfer signal DTR and the data transfer signal DTR are delayed, and the sense amplifier on the side that does not perform data transfer is activated first. Therefore, in addition to the advantage of the above-described embodiment, it is possible to eliminate noise due to the capacitance between adjacent bit lines on the sense amplifier side where the potential difference between bit lines is small.

[0035]

As described above, according to the present invention, a plurality of sets of sense amplifier drive signals for activating sense amplifiers for amplifying data of memory cells connected to the same word line are provided and connected to a data register. Since the sense amplifiers selected as the data transfer target and the sense amplifiers not selected for the plurality of bit line pairs can be independently driven, the sense amplifiers not selected during write data transfer It is possible to prevent noise from passing through the capacitance between bit lines and / or via the sense amplifier drive signal.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment.

FIG. 2 is a waveform diagram showing a data transfer cycle according to an embodiment.

FIG. 3 is a waveform diagram showing a read data transfer cycle according to an embodiment.

FIG. 4 is a circuit diagram showing a sense amplifier of one embodiment.

FIG. 5 is a waveform diagram showing a write data transfer cycle of another embodiment.

FIG. 6 is a waveform diagram showing a read data transfer cycle of another embodiment.

FIG. 7 is a circuit diagram of a conventional example.

FIG. 8 is a circuit diagram showing a conventional sense amplifier.

FIG. 9 is a waveform diagram showing a write data transfer cycle of a conventional example.

FIG. 10 is a waveform diagram showing a read data transfer cycle of a conventional example.

[Explanation of symbols]

ma to mz memory cells Da to Dz, Da (overline) to Dz (overline) bit line SAa to SAz sense amplifiers Reg1 to Reg4 data registers 1 to 4 F / F1 to F / F4 flip-flops T1 to T24, Ta1, 2 ~ Tz1,2, T21 ~ T28, TNa1,2
~ TNb1,2 N-channel transistor TPa1,2 ~ TPb1,2 P-channel transistor 500 Serial pointer 501 selection circuit

Claims (3)

[Claims] 1. A plurality of memory cells arranged in a matrix,
A plurality of bit line pairs connected to columns of a plurality of memory cells, and a plurality of sense amplifiers provided on the plurality of bit line pairs and activated by a sense amplifier drive signal to differentially amplify data bits on the bit line pairs. An amplifier, a plurality of data registers, a plurality of bit line pairs formed by grouping a plurality of bit line pairs, and a plurality of bit line pairs are provided between the plurality of data registers. In a semiconductor memory device having a selection circuit for selecting one bit line pair from each of the bit line pair groups and connecting to each of the plurality of data registers, a plurality of systems capable of independently controlling the sense amplifier drive signals. A semiconductor memory device, wherein the plurality of sense amplifiers are activated by a plurality of systems of sense amplifier drive signals. 2. A semiconductor memory device according to claim 1, wherein a plurality of systems of the sense amplifier drive signal activate a plurality of sense amplifiers substantially at the same time. 3. Each of the plurality of bit line pair groups is composed of a plurality of adjacent bit line pairs, and a plurality of systems of the sense amplifier drive signal are provided in the plurality of adjacent bit line pairs. Of the bit line pair specified by the data transfer signal and the sense amplifier provided on the bit line pair not specified by the data transfer signal have different timings. The semiconductor memory device as claimed in claim 1, wherein the semiconductor memory device is activated by.