JPH05101130A - Equivalent circuit generating method and logical simulating method - Google Patents

Abstract

PURPOSE:To perform the logical simulation of an MOS digital circuit by generat ing an equivalent circuit which can be simulated by a logical simulator from the MOS digital circuit. CONSTITUTION:The types of terminals of elements which constitute the MOS digital circuit are classified 110 according to conditions showing whether the terminals are input or output terminals and whether a high-impedance state is present in case of an output terminal. The flow direction of a signal is determined according to the types of terminals which are directly connected to the source terminal and drain terminal of an MOS transistor(TR), which is replaced by a unidirectional element 140. Characteristics as a dynamic circuit are decided according to the type of a terminal which is directly connected to a network and a virtual latch element is inserted 150. Consequently, the equivalent circuit consisting of only the unidirectional element can be generated at a high speed from the MOS digital circuit and used to perform the logical simulation of the MOS digital circuit at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an equivalent circuit making method and a logic simulation method, and more particularly to an equivalent circuit making method and a logic simulation method suitable for handling a MOS digital circuit.

[0002]

2. Description of the Related Art In a simulator used for verifying a logic design of a MOS digital circuit, a dynamic circuit peculiar to the MOS circuit (such as a 3-state gate, an output net of an element whose output has a high impedance state, A circuit that utilizes the memory effect of the wiring capacitance of the net.
It is often used in LSI design. ), And a function of simulating the operation of the MOS transistor as a bidirectional element. Circuit simulators and switch level simulators are conventionally known as simulators having these two functions.

However, since the circuit simulator handles the simulation target circuit as an analog circuit,
A large amount of computer time is required when targeting an OS digital circuit. On the other hand, since the switch level simulator handles the simulation target circuit as a digital circuit, when the MOS digital circuit is targeted, the simulation can be executed in less computer time than the circuit simulator. However, in consideration of the operation as a dynamic circuit, all MO
Since the S-transistor is treated as a bidirectional element, it also requires a lot of computer time.

A logic simulator is conventionally known as a simulator capable of simulating a digital circuit at high speed. However, since the logic simulator does not consider the action as a dynamic circuit and basically handles only unidirectional logic gates such as AND, OR, and inverters, the MOS digital circuit cannot be simulated as it is. Therefore, by using a virtual latch element in consideration of the action as a dynamic circuit and creating an equivalent circuit in which a MOS transistor is modeled as a unidirectional element, an M
The technology that enables OS digital circuits to be handled is the 18th Design Automation Conference Proceedings (1976), pages 775 to 785 (18th Desi
gn Automation Conference Proceedings (1976), pp.775
-785). However, there is no disclosure about a method of creating an equivalent circuit of a MOS digital circuit, and a logic simulation of a general MOS digital circuit has not been realized.

On the other hand, JP-A-62-119471
In the publication, a technique for modeling a MOS transistor as a unidirectional element is proposed. This JP-A-6
The technique proposed in Japanese Patent Laid-Open No. 2-119471 is a MOS
The direction in which a signal propagates is determined by examining the distance between the power supply and the ground of two terminals except the gate terminal of the transistor, and the MOS transistor is modeled as a unidirectional element.

[0006]

However, the above-mentioned Japanese Unexamined Patent Application Publication No.
In the technique proposed in Japanese Patent Laid-Open No. 2-119471, since an equivalent circuit is not created in consideration of the action as a dynamic circuit, there is a problem that the equivalent circuit must be manually corrected.

Further, since the shortest path from the terminal of the MOS transistor of interest to the power supply or the ground has to be searched, there is a problem that a very long calculation time is required in some cases. Furthermore, since the distance is defined by the number of transistors between the terminal of the MOS transistor of interest and the power supply or the ground, it is difficult to accurately calculate the distance when the logic gate, flip-flop, etc. are included. There is a problem that becomes. Also, except for the gate terminal of the MOS transistor of interest, 2
If the terminals are equal in distance from the power supply and the ground, there is a problem that manual specification is required. Furthermore, in the pass transistor existing between the output terminal of one logic gate and the input terminal of another gate, a signal is connected from the side connected to the output terminal of the logic gate to the side connected to the input terminal of another gate. Although it should flow, there is a problem that the direction is determined by the distance from the power supply or the ground regardless of such a logical property.

For this reason, the conventional logic simulator has been used for MO
It is practically impossible to handle the S digital circuit, and there is a problem that a circuit simulator or a switch level simulator which requires a great amount of calculation time must be used.

Therefore, the first object of the present invention is to provide a general M
An object of the present invention is to provide an equivalent circuit creation method for creating an equivalent circuit that can be simulated by a logic simulator from an OS digital circuit. The second object of the present invention is to
An object of the present invention is to provide a logic simulation method that can handle a general MOS digital circuit.

[0010]

The present invention is directed to a given MOS.
Information about the types of elements that make up the digital circuit and information about the connection relationship between the terminals of each element are obtained, and based on this information, for each terminal of each element except the source terminal and drain terminal of the MOS transistor, Sources and drains of MOS transistors are classified according to whether they are power supply terminals, ground terminals, input terminals, MOS transistor gate terminals, output terminals that do not have a high impedance state, or output terminals that have a high impedance state. Regarding the terminals, the direction in which the signal of the MOS transistor flows is determined according to the type of the other terminals directly connected to each terminal, and the type is classified according to whether it is an input terminal or an output terminal.
Provided is an equivalent circuit creating method characterized in that an equivalent circuit is created by replacing a MOS transistor with one or more unidirectional elements according to the direction of signal flow of the transistor.

Further, according to the present invention, in the above equivalent circuit producing method, when all output terminals connected to a net included in the MOS digital circuit are output terminals in which a high impedance state exists, a terminal directly connected to the net. The present invention provides a method for producing an equivalent circuit, which is represented by using a virtual latch element or a latch-type element according to the type.

Further, the present invention is characterized in that a circuit description of a MOS digital circuit is input, an equivalent circuit is created by the above-mentioned equivalent circuit creating method, and the operation of the MOS digital circuit is simulated using the equivalent circuit. To provide a logic simulation method.

[0013]

According to the equivalent circuit producing method of the present invention, the direction of the MOS transistor is determined in the process by classifying the terminals of the MOS transistor according to the type of the terminal and the type of the other terminal directly connected to the terminal. To do. Further, in the equivalent circuit creating method of the present invention, the dynamic circuit peculiar to the MOS digital circuit is represented by a virtual latch element or a latch type element according to the type of the terminal directly connected to the net. Therefore, unlike the conventional case, a complicated process of searching for the shortest path to reach the power supply or the ground is not required, so that the process can be simplified and the computer time can be shortened.

Further, in the logic simulation method of the present invention, high speed logic simulation is performed using the equivalent circuit created by the above equivalent circuit creation method. Therefore,
The design verification of a general MOS digital circuit can be performed efficiently at high speed.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. The present invention is not limited to this.

FIG. 1 is a block diagram of a logic simulation system 800 for implementing the equivalent circuit creating method and logic simulation method of the present invention. The circuit description file 801 is a file in which a MOS digital circuit that is an object of equivalent circuit creation or logic simulation is described, and includes information on the types of elements that make up the MOS digital circuit and information on the terminals of the elements. The information on the type of element indicates whether the element is a logic gate element composed of a plurality of MOS transistors or a three-state gate element,
It is information such as whether it is a flip-flop, a single MOS transistor, or a power source or ground which is usually an external input pin. The information on the terminal of the element is that the terminal is the input terminal or the output terminal, whether the terminal of the single MOS transistor is the gate terminal or the other terminal, whether the output terminal has a high impedance state, or other information. It is information such as which terminal of which element is connected.

The processing device 802 is a device for performing equivalent circuit creation processing and logic simulation processing. The equivalent circuit description file 803 is the circuit description file 801.
Is a file describing the equivalent circuit created by the processing device 802. Simulation result file 804
Is a file that stores the result of the logic simulation executed by the processing device 802 using the equivalent circuit description file 803. Simulation result list 8
Reference numeral 05 is a list output of the execution result of the logic simulation.

FIG. 2 shows a data structure representing an equivalent circuit in the equivalent circuit description file 803. The element table 910 holds information corresponding to each element forming the equivalent circuit. The net table 920 holds information corresponding to nets between the respective elements forming the equivalent circuit. The input terminal table 940 and the output terminal table 950 are
The information corresponding to the input terminal and the output terminal of each element forming the equivalent circuit is held, and the record of the element table 910 and the record of the net table 920 are associated with each other.

Next, each table 910, 920, 94
The contents of 0,950 will be described. Element table 91
One record of 0 has 5 fields. First
Field 911 indicates the type of the element (AND gate, OR gate, inverter, 3-state gate, unidirectional transistor, 3-state connection logic, latch, etc.). The second field 912 indicates the number of input terminals of the device. The third field 913 is a pointer that points to the record of the corresponding input terminal table 940. When the number of input terminals of the element is plural, although the records of the input terminal table 940 corresponding to the number of input terminals continuously exist, the first record is designated. The fourth field 914 indicates the number of output terminals of the device. The fifth field 915 is a pointer that points to a record in the corresponding output terminal table 950. When the number of output terminals of the element is plural, the output terminal table 9 for the number of output terminals is provided.
Although 50 records exist continuously, the first record is designated.

One record of the net table 920 has 12 fields. First field 92
1 indicates a unique net name given to the net.

The second field 922 to the ninth field 929 hold the type information of the terminal directly connected to the net. Here, the terminal type is defined as follows. Type F ... Power supply or ground Type D ... Element output terminal without high impedance state Type T ... Element output terminal with high impedance state Type G ... MOS transistor gate terminal, and ,
Terminals that become inputs of elements other than MOS transistors Type K ... Source and drain terminals of MOS transistors and terminals that become inputs Type X ... Source or drain terminals of MOS transistors become inputs during the process of creating an equivalent circuit When it is undecided whether or not it will be an output, it is not possible to decide whether to use type K or type T, so the terminal is temporarily set to type X. In other words, if there is a terminal of the above type among the terminals directly connected to the net, the second field 922
To the corresponding field in the seventh field 927 <
A value other than 0> is held, and if it does not exist, a value <0> is held. If there are a plurality of terminals (types F, D, and T) that are signal sources when viewed from the net, a value other than <0> is held in the eighth field 928. Holds the value <0>. Further, if there is a bidirectional transistor directly connected to the net, a value other than <0> is held in the ninth field 929, and if it does not exist, a value <0> is held.

The tenth field 931 is a pointer which points to one of the records in the output terminal table 950 corresponding to the terminal which is the signal source when viewed from the net. The eleventh field 932 is a pointer that points to one of the records in the input terminal table 940 corresponding to the terminal that serves as a sink when viewed from the net. A twelfth field 933 is a pointer that points to one of the transistor terminal tables 970 (described later with reference to FIG. 3) corresponding to a transistor whose direction is undecided to be directly connected to the net.

One record of the input terminal table 940 has 6 fields. First field 941
Holds a terminal number uniquely determined for each element to identify the terminal. The second field 942 is
Indicates the type of the terminal (any one of types F, D, and T). The third field 943 is a pointer that points to a record in the element table 910 corresponding to the element to which the terminal belongs. The fourth field 944 is a pointer that points to a record in the net table 920 corresponding to the net to which the terminal is connected.

The fifth field 945 is a pointer for connecting the records of the input terminal table 940 of these terminals when other input terminals are also connected to the net to which the terminal is connected. That is, the record of the net table 920 corresponding to a certain net is recorded in one input terminal table 94 by the eleventh field 932.
Specify 0 record. The designated input terminal table 940 record designates the record of the input terminal table 940 corresponding to another terminal connected to the net by the fifth field 945 thereof. Hereinafter, similarly, the records of all the input terminal tables 940 corresponding to the terminals connected to the same net are sequentially designated. The last record of the input terminal table 940 is the net table 9
Input terminal table 9 designated by 20 records
Specify 40 records.

A sixth field 946 is an output terminal table 95 corresponding to the same terminal when the terminal is the source terminal or the drain terminal of the bidirectional transistor.
It is a pointer that points to a record of 0.

One record of the output terminal table 950 has 6 fields. First field 951
Holds a number uniquely determined for each element to identify the terminal. The second field 952 indicates the type of the terminal (either type G or K). Third
Field 953 is a pointer that points to a record of the element table 910 corresponding to the element to which the terminal belongs. The fourth field 954 is a pointer that points to a record in the net table 920 corresponding to the net to which the terminal is connected.

The fifth field 955 is a pointer for connecting the records of the output terminal table 950 of these terminals when other output terminals are also connected to the net to which the terminal is connected. That is, the record of the net table 920 corresponding to a certain net is recorded in one output terminal table 95 by the tenth field 931 thereof.
Specify 0 record. The designated record of the output terminal table 950 designates the record of the output terminal table 950 corresponding to another terminal connected to the net by the fifth field 955. Hereinafter, similarly, the records of all the output terminal tables 950 corresponding to the terminals connected to the same net are sequentially designated. The last record of the output terminal table 950 is the net table 9
Output terminal table 9 designated by 20 records
Indicate 50 records.

The sixth field 956 is an input power terminal table 9 corresponding to the same terminal when the terminal is the source terminal or the drain terminal of the bidirectional transistor.
It is a pointer that points to 40 records.

FIG. 3 shows an equivalent circuit creation data structure used in the equivalent circuit creation work. In the undecided direction transistor table 960, a record is created for a MOS transistor whose signal flow direction is undecided. The transistor terminal table 970 holds information about the terminals of each transistor.

Next, the contents of the tables 960 and 970 will be described. Direction undetermined transistor table 96
One record of 0 has 5 fields. The first field 961 is a transistor terminal table 97 that holds information corresponding to the gate terminal of the transistor.
It is a pointer that points to a record of 0. The second field 962 and the third field 963 are pointers that point to records in the transistor terminal table 970 that hold information corresponding to the source terminal or drain terminal of the transistor.

The fourth field 964 newly determines the type of another terminal connected to the source terminal or the drain terminal of the transistor when there is a possibility of determining the direction of the transistor in the process of creating an equivalent circuit. If a value other than <0> is held, the value <0> is held otherwise.

The fifth field 965 holds a value <0> when the direction of the signal flow of the transistor corresponding to the record is undecided, and holds a value other than <0> when the direction has been decided. ..

One record of the transistor terminal table 970 has three fields. The first field 971 is a pointer that points to a record in the direction undetermined transistor table 960 corresponding to the transistor element to which the terminal belongs. The second field 972 is
Net table 9 corresponding to the net to which the terminal is connected
It is a pointer that points to 20 records. The third field 973 is a pointer for linking the records of the transistor terminal table 970 of other terminals when the source or drain terminals of other transistors are also connected to the net to which the terminal is connected. That is, the record of the net table 920 corresponding to a certain net indicates the record of one transistor terminal table 970 by its twelfth field 933.
The designated record of the transistor terminal table 970 designates the record of the transistor terminal table 970 corresponding to another terminal connected to the net by the third field 973 thereof. Hereinafter, similarly, the records of all the transistor terminal tables 970 corresponding to the terminals connected to the same net are sequentially designated. The last transistor terminal table 970 record points to the transistor terminal table 970 record pointed to by the net table 920 record.

FIG. 4 shows a first method of making an equivalent circuit according to the present invention.
It is a flowchart of the process concerning an Example. In process 110, process 111 and process 121 are performed for all the elements. In process 111, the circuit description file 801 is read. In process 121, it is determined whether or not the element of interest is a single MOS transistor. If it is a single MOS transistor, processing 122, processing 123,
The process 124 is performed. Otherwise, process 127,
The process 130 is performed.

In the process 122, 1 record is secured in the direction undetermined transistor table 960, 3 records are secured in the transistor terminal table 970, and the information of the single MOS transistor and the pointer information are stored in them. The three records of the transistor terminal table 970 correspond to the gate terminal, source terminal, and drain terminal of the transistor, respectively. However, the distinction between the source terminal and the drain terminal is not essential. Also, it is checked whether the net name of the net to which each terminal is connected is already registered in the net table 920. If the net name is already registered, the net and the terminal of the record secured in the corresponding record and the transistor terminal table 970 are registered. The pointer information indicating the relationship is stored, or, if there is another record of the transistor terminal table 970 indicating the same net, the pointer information indicating the same is stored. On the other hand, when the net name is not registered in the net table 920, one record is secured in the net table 920, and the record and the transistor terminal table 9 are stored.
The net information and pointer information are stored in the record secured in 70. At this point, the net table 920
The value of <0> is stored in the second field 922 to the ninth field 929 of the newly secured record.

In process 123, the gate terminal of the MOS transistor is classified into type G. That is, the fifth field 925 of the record of the net table 920 designated by the second field 972 of the record corresponding to the gate terminal secured in the transistor terminal table 970.
A value other than <0> is stored in.

In process 124, the source and drain terminals of the MOS transistor are classified into type X. That is, values other than <0> are stored in the seventh field 927 of the record of the net table 920 designated by the second field 972 of the record corresponding to the source and drain terminals secured in the transistor terminal table 970.

In process 127, the information of the element is registered in the element table 910. That is, the element table 91
1 record is secured in 0, records for the number of input terminals are secured in the input terminal table 940, and output terminal table 95
Records for the number of output terminals are secured in 0, and element information and pointer information are stored. Further, the storage of information in the net table 920 is performed in the same manner as in the case of the processing 123 described above. When registering the output terminal, the same net has already been registered and the net table 9 corresponding to the net is registered.
If the pointer value is registered in the tenth field 931 of T.20, a value other than <0> is stored in the eighth field 928 of the net table 920.

In process 130, process 131 is performed for all terminals of the device. In the process 131, when the terminal is a power source or a ground (that is, the element is an external input pin connected to the power source or the ground),
The process 132 is performed. When the terminal is not the power supply or the ground and is the input terminal, the processing 133 is performed. If the terminal is not the power supply or the ground and is the output terminal, the processing 134 is performed.

In process 132, the terminal is classified into type F. That is, <Type F> is stored in the second field 952 of the record of the output terminal table 950 corresponding to the relevant terminal, and <Type F> is stored in the second field 922 of the record of the net table 920 designated by the fourth field 954. Store values other than 0>. In process 133, the terminal is classified into type G. That is, the second record of the record of the input terminal table 940 corresponding to the terminal.
<Type G> is stored in the field 942 of the net table 920, and the fourth table 944 indicates the net table 920.
A value other than <0> is stored in the fifth field 925 of the record.

In step 134, if a high impedance state exists in the terminal (that is, the type of element to which the terminal belongs is a 3-state gate or the like), step 135 is executed. When the high impedance state does not exist, the processing 136 is performed.

In step 135, the terminal is classified into type T. That is, <Type T> is stored in the second field 952 of the record of the output terminal table 950 corresponding to the terminal, and <Type T> is stored in the fourth field 924 of the record of the net table 920 designated by the fourth field 954. Store values other than 0>.

In process 136, the terminal is classified into type D. That is, <type D> is stored in the second field 952 of the record of the output terminal table 950 corresponding to the terminal, and <Type D> is stored in the third field 923 of the record of the net table 920 designated by the fourth field 954. Store values other than 0>.

In process 140, until the direction undecided transistor registered in process 122 does not exist (that is, there is no record of the direction undecided transistor table 960 having the value <0> in the fifth field 965). Up to), one of the undetermined direction transistors is taken out, and processing 141 and processing 142 are performed.

In step 141, the types of all the terminals directly connected to the source terminal / drain terminal of the direction undetermined transistor are checked. That is, the record of the transistor terminal table 970 indicated by the second field 962 and the third field 963 of the record of the direction undecided transistor table 960 corresponding to the direction undecided transistor is referred to, and the second field 972 thereof is further referred to. By referring to the contents of the second field 922 to the seventh field 927 of the net table 920 instructed by the terminal, which is directly connected to each of the source terminal / drain terminal of the direction undetermined transistor. Find out the type.

In process 142, the direction in which the signal of the direction undetermined transistor flows is determined using the direction determination table 200 shown in FIG. For example, a type F terminal (power supply or ground) exists on the source terminal side of the direction undetermined transistor, a type F terminal does not exist on the drain terminal side, and neither type D nor T terminal exists. In this case, the arrow in the direction determination table 200 determines that a signal flows from the source terminal side to the drain terminal side. In addition, for example, the type F terminal does not exist on the source terminal side of the direction undetermined transistor, the type D or T terminal exists, and the type G or K terminal exists, and the drain terminal side If there is no type F terminal, there is a type D or T terminal, and there is no type G or K terminal and there is a type X terminal, then at this point Do not decide the direction of flow (it cannot be decided, so hold it). Also,
For example, the type F terminal does not exist on the source terminal side of the direction undetermined transistor, the type D or T terminal exists, the type G or K terminal exists, and the drain terminal side Type F terminal does not exist and either type D or T terminal exists and type G, K
When either terminal is present, the direction of signal flow is determined to be bidirectional. Note that, for example, when a type F terminal exists on the source terminal side of the direction undecided transistor and a type F terminal also exists on the drain terminal side, the design failure is caused by <Error> in the direction determination table 200. To judge. When the direction in which the signal of the direction undetermined transistor flows is determined to be unidirectional or bidirectional, processing 143 is performed.

In processing 143, it is determined whether or not the direction in which the signal of the direction undetermined transistor flows is determined to be unidirectional. If it is determined to be unidirectional, processing 144 is performed, and if it is determined to be bidirectional. The process 145 is performed.

In process 144, the MOS transistor ((a) in FIG. 6) is changed in accordance with the direction of signal flow.
It is replaced with a unidirectional transistor element (FIG. 6B). That is, the direction undetermined transistor table 960
A value other than <0> is stored in the fifth field 965 of the corresponding record. Further, one record is secured in the element table 910, two records are secured in the input terminal table 940, and one record is secured in the output terminal table 950. The symbols used in FIG. 6B are determined for convenience in order to represent the basic elements that realize the MOS equivalent circuit, and will be described later.

The first record of the two records secured in the input terminal table 940 corresponds to the gate terminal G of the unidirectional transistor element TRS. <Type G> is stored in the second field 942 of the first record. The second record of the two records secured in the input terminal table 940 is the source terminal or the drain terminal of the MOS transistor and corresponds to the input terminal D of the unidirectional transistor element TRS. <Type K> is stored in the second field 942 of the second record. The record secured in the output terminal table 950 is the source terminal or the drain terminal of the MOS transistor and corresponds to the output terminal O of the unidirectional transistor element TRS. <Type T> is stored in the second field 952 of the record.

Further, in the process 144, the pointer information is fetched from the direction undetermined transistor table 960 and the transistor terminal table 970, and the element table 9 is fetched.
10, input terminal table 940, output terminal table 95
Store in each record secured to 0. Then, the fifth field 925 of the record of the net table 920 indicated by the fourth field 944 of the first record of the two records secured in the input terminal table 940.
A value other than <0> is stored in. Also, the net table 92 designated by the fourth field 944 of the second record of the two records secured in the input terminal table 940.
A value other than <0> is stored in the sixth field 926 of the 0 record. Further, a value other than <0> is stored in the fourth field 924 of the record of the net table 920 designated by the fourth field 954 of the record secured in the output terminal table 950.

In step 145, the MOS transistor (FIG. 7A) is replaced with a combination of two unidirectional transistor elements and node elements (FIG. 7B). That is, 2 records are secured in the element table 910, 4 records are secured in the input terminal table 940, and 2 records are secured in the output terminal table 950. Further, similar to the processing 144 described above, information regarding the two unidirectional transistor elements and pointer information indicating the relationship between the elements and the terminals are stored. In addition, since the number of nets increases as the number of elements increases, a necessary number of records are secured in the net table 920, and the secured records and the input terminal table 9 are secured.
40 and the corresponding record of the output terminal table 950, pointer information indicating the relationship between the net and the terminal is stored. Further, pointers indicating the same terminal are stored in the sixth fields 946 and 956 of the input terminal table 940 and the output terminal table 950, respectively. Further, similarly to the processing 144 described above, the gate terminal G, the input terminal D, and the output terminal O of the unidirectional transistor element are classified into types G, K, and T, respectively. The symbols used in FIG. 7B are determined for the sake of convenience to represent the basic elements that realize the MOS equivalent circuit, and will be described in detail later.

In process 150, the circuit description file 801
The processing 151 and the processing 153 are performed for all the nets present therein. In the process 151, when there are a plurality of terminals on the signal source side as viewed from the net (when the content of the eighth field 928 of the record of the net table 920 is a value other than <0>), the process is performed. Perform 152. In process 152, a virtual three-state connection logic element ((a) of FIG. 13 described later) is inserted so that only one terminal on the signal source side can be seen from the net. That is, the element table 910 and the output terminal table 950.
1 record for each of the input terminal table 940 and the net table 920 for the number of terminals on the signal source side of the net.
Stores information about the net. At this time, if a type F terminal exists on the signal source side of the net, the output terminal of the 3-state wired logic element is classified into type F.
If the type F terminal does not exist and the type D terminal exists on the signal source side of the net, the output terminal of the 3-state connection logic element is classified into the type D. Also,
When neither the type F terminal nor the type D terminal exists on the signal source side of the net, the output terminal of the 3-state connection logic element is classified into the type T.

In process 153, the property of the net as a dynamic circuit is determined. That is, process 151
If the terminal on the signal source side as viewed from the net before performing is only the type T terminal, the net operates as a dynamic circuit, and thus the process 154 is performed. Process 15
In 4, a virtual latch element (for example, a flip-flop) is inserted in front of the type G terminal on the sink side as seen from the net. Even if there are a plurality of type G terminals, one virtual latch element is inserted and the output terminal of the virtual latch element is connected to the plurality of type G terminals. Specifically, the element table 910, the input terminal table 940, the output terminal table 950, and the net table 9
One record is secured in each of 20 and information regarding elements, terminals and nets is stored.

By the above equivalent circuit creation processing, for example, from the MOS digital circuit 500 of FIG.
The equivalent circuit 510 of (b) is obtained. In FIG. 8A, 501, 502, and 503 are MOS transistors, 504 is an inverter, and 505 is a net. Figure 8
(B), 511, 512, and 513 are unidirectional transistors, 514 is a virtual three-state connection logic element, 515 is an inverter, and 520 is a virtual latch element.

According to the above equivalent circuit creation processing, it is possible to create an equivalent circuit in consideration of the action as a dynamic circuit. Further, since the orientation of the MOS transistor is determined only by the type of the terminals of other elements directly connected to the source terminal and the drain terminal of the MOS transistor, the computer time can be shortened.

FIG. 9 shows a second method of producing an equivalent circuit according to the present invention.
It is a flowchart of the process concerning an Example. In process 310, as in processes 110 to 136 in FIG.
Except for the source and drain terminals of the OS transistor,
The types of terminals of each element forming the MOS digital circuit are classified. In the process 340, the processes 140 to 145 shown in FIG.
Similarly, the direction of the MOS transistor is determined by the type of the terminal directly connected to each of the source terminal and the drain terminal of the MOS transistor.

In process 350, the circuit description file 801
The processing 351 and the processing 353 are performed for all the nets existing therein. In the process 351, the processes 151 to 151 in FIG.
Similarly to 152, when there are a plurality of terminals on the signal source side viewed from the net, a virtual three-state connection logic element is inserted, and the terminal on the signal source side viewed from the net is unique. To become one.

In process 353, the property of the net as a dynamic circuit is determined. That is, process 351
If the terminal on the signal source side as viewed from the net before performing is only the type T terminal, the net operates as a dynamic circuit, so processing 354 is performed. Process 35
In No. 4, processing 355 is performed when only a type G terminal exists on the sink side as viewed from the net, and processing 356 is performed otherwise. In process 355, process 351
The virtual three-state connection logic element inserted in step 3 is replaced with a latch type element ((b) of FIG. 13 described later). As a specific process, the contents of the first field 911 of the corresponding record in the element table 910 are replaced.

In step 356, a virtual latch element is inserted in front of the type G terminal on the sink side as seen from the net. As a virtual latch element, a latch type 3
A state connection logic element ((b) of FIG. 13 described later) may be used.

By the above equivalent circuit creation processing, for example, the equivalent circuit 530 of FIG. 10B can be obtained from the MOS digital circuit 500 of FIG. 10A. According to the above equivalent circuit creation processing, it is possible to create an equivalent circuit in consideration of the action as a dynamic circuit. Also, M
Since the orientation of the OS transistor is determined only by the type of the terminals of other elements directly connected to the source terminal and the drain terminal of the MOS transistor, the computer time can be shortened. Furthermore, the number of virtual latch elements to be inserted in order to take into consideration the action of the dynamic circuit can be reduced, and a faster logic simulation can be executed.

FIG. 11 is a flow chart of processing according to the third embodiment of the equivalent circuit producing method of the present invention. Process 310,
340, 350, and 351 are the same as the processing in FIG. In the process 361, the process 363 is performed when there is only one terminal on the signal source side viewed from the net, and the process 353 is performed when there are a plurality of terminals. In process 363, since the net operates as a dynamic circuit when the terminal on the signal source side viewed from the net is a type T terminal, process 364 is executed. In process 364, process 365 is performed when only the type G terminal is present on the sink side as viewed from the net. In the process 365, the element having the signal source side terminal viewed from the net is replaced with the latch type element. An element having a terminal on the signal source side is an element having a terminal of type T, and for example, the unidirectional transistor TRS of FIG. 12A, the three-state connection logic element TSW of FIG. (A) 3-state gate T
These are SG, which are the unidirectional transistor TRSL of FIG. 12B, the three-state connection logic element TSWL of FIG. 13B, and the three-state gate T of FIG. 14B.
Replace with SGL respectively. As specific processing,
The contents of the first field 911 of the corresponding record in the element table 910 are replaced with an appropriate one.

Processes 353, 354, 355 and 356 are
This is the same as the processing in FIG.

According to the above equivalent circuit creation processing, it is possible to create an equivalent circuit in consideration of the action as a dynamic circuit. Further, since the orientation of the MOS transistor is determined only by the type of the terminals of other elements directly connected to the source terminal and the drain terminal of the MOS transistor, the computer time can be shortened. Furthermore, the number of virtual latch elements to be inserted in order to take into consideration the action of the dynamic circuit can be reduced, and a faster logic simulation can be executed.

Here, the symbols used in FIGS. 6B, 7B, 8B, and 10B will be described with reference to FIGS. 12, 13, and 14. .. The unidirectional transistors TRS and TRSL shown in FIG.
The transistor is a unidirectional model focusing on the direction of signal flow. The latch type unidirectional transistor TRSL considers the property of the net connected to the output terminal as a dynamic circuit. 3 shown in FIG.
The state connection logic elements TSW and TSWL are virtual node elements that simulate the operation of the connection logic in which the outputs of the plurality of elements form one net. The figure shows an element with four inputs, but the number of inputs is arbitrary. The latch type 3-state connection logic element TSWL considers the property of the net as a dynamic circuit. The output O of the three-state gates TSG and TSGL shown in FIG. 14 can take a high impedance Z. The latch type 3-state gate TSGL holds the output value Q immediately before when the output becomes high impedance in consideration of the property of the net connected to the output terminal as a dynamic circuit.

Next, FIG. 15 is a flow chart of processing according to the embodiment of the logic simulation method of the present invention. In process 402, an equivalent circuit including only unidirectional elements is created by the equivalent circuit creating process as shown in FIG. 4, FIG. 9 or FIG. In step 403, the operation of the MOS digital circuit is simulated by using an equivalent circuit and a normal logic simulation method that targets only unidirectional elements. In process 404, the simulation result is edited in an appropriate format and output to the simulation result file 804 and the simulation result list 805.

According to the above logic simulation processing, an equivalent circuit composed of only unidirectional elements is created from a general MOS digital circuit and the logic simulation is performed, so that high-speed logic simulation is possible.

[0067]

According to the equivalent circuit creating method of the present invention, it is possible to create an equivalent circuit in consideration of the operation as a dynamic circuit. Further, since the orientation of the MOS transistor is determined only by the type of the terminals of other elements directly connected to the source terminal and the drain terminal of the MOS transistor, the computer time can be shortened.

Further, according to the logic simulation method of the present invention, since an equivalent circuit composed of only unidirectional elements is created from a general MOS digital circuit and the logic simulation is performed, high-speed logic simulation is possible.

[Brief description of drawings]

FIG. 1 is a block diagram of a logic simulation system embodying the present invention.

FIG. 2 is a data structure diagram of an equivalent circuit description file.

FIG. 3 is a data structure diagram for creating an equivalent circuit.

FIG. 4 is a flowchart of an equivalent circuit creation process according to the first embodiment of the present invention.

FIG. 5 is an explanatory diagram of a direction determination table.

FIG. 6 is an explanatory diagram in which a MOS transistor is replaced with a unidirectional transistor.

FIG. 7 is an explanatory diagram in which a MOS transistor is replaced with a unidirectional transistor and a virtual node element.

FIG. 8 is an explanatory diagram of an example of a MOS digital circuit and its equivalent circuit.

FIG. 9 is a flowchart of an equivalent circuit creation process according to the second embodiment of the present invention.

FIG. 10 is an explanatory diagram of a MOS digital circuit example and its equivalent circuit.

FIG. 11 is a flowchart of an equivalent circuit creation process according to the third embodiment of the present invention.

FIG. 12 is an explanatory diagram of symbols and operations of unidirectional transistors used in an equivalent circuit.

FIG. 13 is an explanatory diagram of symbols and operations of a 3-state wired logic element used in an equivalent circuit.

FIG. 14 is an explanatory diagram of symbols and operations of a 3-state gate used in an equivalent circuit.

FIG. 15 is a flowchart of the logic simulation process in the fourth embodiment of the present invention.

[Explanation of symbols]

 200 Direction determination table 503 MOS transistor 504 Inverter 513 Unidirectional transistor element 520 Latch element 533 Three-state connection logic element 800 Logic simulation system 801 Circuit description file 802 Processor 803 Equivalent circuit description file 804 Simulation result file 805 Simulation result list 910 Element table 920 Net table 940 Input terminal table 950 Output terminal table 960 Direction undecided transistor table 970 Transistor terminal table

Claims (6)

[Claims] 1. Obtaining information on the types of elements that make up a given MOS digital circuit and information on the connection relationship between the terminals of each element, and based on that information, the source and drain terminals of a MOS transistor are determined. Except for each terminal of each element, power supply terminal, ground terminal, input terminal, M
Types are classified according to the gate terminal of the OS transistor, the output terminal that does not have a high impedance state, or the output terminal that has a high impedance state. Regarding the source terminal and the drain terminal of the MOS transistor,
The direction of signal flow of the MOS transistor is determined according to the type of other terminals directly connected to each, and the type is classified according to whether it is an input terminal or an output terminal, and the direction of signal flow of the MOS transistor determined in the type classification process. According to the method, an equivalent circuit is created by replacing the MOS transistor with one or more unidirectional elements to create an equivalent circuit. 2. The equivalent circuit manufacturing method according to claim 1, wherein when a MOS transistor whose direction of signal flow cannot be determined appears in the process of type classification, the type classification is suspended and other terminals are classified first. And classifying one or more other terminals, and then re-executing the type classification for the MOS transistor for which the type classification has been suspended. 3. The equivalent circuit producing method according to claim 1 or 2, wherein all output terminals connected to the net included in the MOS digital circuit are output terminals in which a high impedance state exists. A method for producing an equivalent circuit, characterized in that a virtual latch element is inserted just before the input terminal of an element other than a MOS transistor and the gate terminal of a MOS transistor among the input terminals connected to. 4. The equivalent circuit creating method according to claim 1 or 2, wherein all output terminals connected to the net included in the MOS digital circuit are output terminals in which a high impedance state exists. When the input terminal connected to is composed only of the input terminal of an element other than a MOS transistor and the gate terminal of a MOS transistor, the net is replaced with a latch-type connection logic element, and the input terminal connected to the net is an element other than a MOS transistor. When the input terminal and the terminal different from the gate terminal of the MOS transistor are included, insert a virtual latch element immediately before the input terminal of the element other than the MOS transistor and the gate terminal of the MOS transistor among the input terminals connected to the net. A method for creating an equivalent circuit, characterized by. 5. The equivalent circuit creating method according to claim 4, wherein there is one output terminal connected to each net included in the MOS digital circuit, and the output terminal has a high impedance state. When the input terminal connected to the net consists only of the input terminal of the element other than the MOS transistor and the gate terminal of the MOS transistor,
A method for producing an equivalent circuit, characterized in that an element having an output terminal connected to the net is replaced with a virtual latch type element. 6. A circuit description of a MOS digital circuit is input, an equivalent circuit is created by the equivalent circuit creating method according to claim 1, and the MOS digital circuit is created using the equivalent circuit. A logic simulation method characterized by simulating the behavior of the above.