JPH0499851U - - Google Patents
Info
- Publication number
- JPH0499851U JPH0499851U JP447391U JP447391U JPH0499851U JP H0499851 U JPH0499851 U JP H0499851U JP 447391 U JP447391 U JP 447391U JP 447391 U JP447391 U JP 447391U JP H0499851 U JPH0499851 U JP H0499851U
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. by varying supply voltage
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Environmental & Geological Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP447391U JPH0499851U (ja) | 1991-02-07 | 1991-02-07 | |
| EP19920102074 EP0498449A3 (en) | 1991-02-07 | 1992-02-07 | Semiconductor integrated circuit device having dynamic burn-in circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP447391U JPH0499851U (ja) | 1991-02-07 | 1991-02-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0499851U true JPH0499851U (ja) | 1992-08-28 |
Family
ID=11585091
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP447391U Pending JPH0499851U (ja) | 1991-02-07 | 1991-02-07 |
Country Status (2)
| Country | Link |
|---|---|
| EP (1) | EP0498449A3 (ja) |
| JP (1) | JPH0499851U (ja) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06242188A (ja) * | 1993-02-16 | 1994-09-02 | Mitsubishi Electric Corp | 半導体集積回路及びそのテスト方法 |
| US8095104B2 (en) * | 2006-06-30 | 2012-01-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and electronic device having the same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4855672A (en) * | 1987-05-18 | 1989-08-08 | Shreeve Robert W | Method and process for testing the reliability of integrated circuit (IC) chips and novel IC circuitry for accomplishing same |
| JPH0770573B2 (ja) * | 1989-07-11 | 1995-07-31 | 富士通株式会社 | 半導体集積回路装置 |
-
1991
- 1991-02-07 JP JP447391U patent/JPH0499851U/ja active Pending
-
1992
- 1992-02-07 EP EP19920102074 patent/EP0498449A3/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| EP0498449A3 (en) | 1993-06-02 |
| EP0498449A2 (en) | 1992-08-12 |