JPH049781A - Mls timing monitor device - Google Patents

Abstract

PURPOSE:To enable deviation in a MLS timing to be detected positively in a simple circuit configuration by monitoring transition of a reference clock due to drift and a test signal which is superposed to each function timing. CONSTITUTION:A memory 105 of a function timing generating part 102 outputs a signal 106 where a one-bit test signal is superposed on one function timing signal based on an address of a counter 104 and a control signal 107 which is generated at a same timing as the test signal. The presence of each test signal which is separated 108 from this signal 106 is monitored by a detection circuit 110 through an OR circuit 109. Also, a timer gate with a drift displacement allowable range of a generating source of a reference clock which becomes a generation standard of a timing signal as a pulse width is formed based on a clock for monitoring which divides an output of a crystal oscillator for monitoring 111 by a timer 113. A detection circuit 115 detects whether the reference clock is generated within the pulse width or not.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is directed to an MLS (microwave landing system) that monitors the transmission timing of its own device in each component device of the MLS (microwave landing system).
This invention relates to an S timing monitor device.

(Prior technology) MLS uses microwave band (5 GHz band) at airports.
This is a device for guiding aircraft to land using radio waves, and was developed as a next-generation landing guidance system to replace the ILS (Instrument Landing System).

Here, MLS basically consists of an azimuth guidance device (hereinafter referred to as rAZJ) that reciprocates horizontally with a fan-shaped fan beam formed in a vertical plane, and a direction guidance device (rAZJ) that scans a fan-shaped fan beam formed in a horizontal plane vertically. High-low guidance bag W (
rELJ) and a go-around azimuth guidance system that provides azimuth guidance when an aircraft re-approaches! (Hereinafter, rBA
Each device is equipped with a plurality of antennas, such as a data antenna and a beam scanning antenna, depending on the function to be transmitted.

By the way, in MLS, each device transmits radio waves of the same frequency in a time-division manner under the control of device AZ. That is, each device has a predetermined cycle (
An example is shown in Fig. 4, in which fixed timing positions that do not overlap each other within 615 ms) are defined, and a transmission operation is performed within a predetermined time at the defined timing positions in accordance with a synchronization signal sent from device AZ every 615 m5. This is an indication.

In Figure 4, the functions of each device are grouped together into AZ,
It is indicated as EL, BAZ (4th [J(2+(31G)
41), the basic data (Ba5ic Data) and auxiliary data (uxiliary Data), which are functions that exist only in the device AZ and the same BAZ, are extracted and shown separately (Fig. 4 +51161).

Therefore, each device transmits a plurality of functions in a time-division manner within a defined predetermined period of time, and also forms internal signals. An example of this is shown in FIG. FIG. 5 shows the situation at one timing position (FIG. 5 (1)) assigned to the WAZ within one cycle.
It is shown that the transmission timing positions of the cation) signal and the scan (SCAN) signal are defined in this order, and that the DPSK control signal, which is an internal signal, is formed within the transmission timing period of the preamble.

Note that the Preamble (FIG. 5 (2)) includes a function ID indicating that the subsequent function belongs to the device AZ.
rcntiaPhase 5hift Keying)
The code is transmitted from the data antenna of device AZ. The OCI signal (Figure 5 (31f4) (51) is
This signal indicates that the signal is outside the MLS guidance range, and is divided into three types depending on the direction of transmission: rear, left, and right. That is, three O
Each is transmitted from a CI antenna. SCAN signal (
FIG. 5(6)) is transmitted from the beam scanning antenna of the device AZ. In addition, the DPSK control signal (Fig. 5 (7))
is a DPSK signal to a high frequency (RF) signal using a function ID, etc. within the transmission timing of the preamble.
This is an internal signal that controls the modulator to provide modulation.

In this way, each device transmits its respective functions in a time-sharing manner, so it is necessary to individually monitor each device to ensure that each function is being transmitted at the correct timing without interfering with each other. becomes.

Therefore, conventionally, a monitor device as shown in FIG. 3, for example, is installed for each device to monitor it. In FIG. 3, the monitor device includes a monitor function timing generator 306 and a function timing monitor 3.
It consists of 11. The monitor function timing generation section 306 has the same configuration as the function timing generation section 302 which is originally included in each device and is a monitoring target, and both share the same control crystal oscillator 315. The function timing monitor 3+1 includes a deviation detection section 312 and an abnormality determination section 3N.

As mentioned above, the synchronization signal is repeatedly generated at a period of 615m5, but the synchronization signal is generated by the counter gate generation section 303 (307
> In response to this synchronization signal, a gate signal defining a predetermined period within one cycle is generated, and the gate signal is sent to the counter 304 (30
8) as a control signal. This counter 304 (3
1), the clock is given from the frequency divider 316 (317>) that divides the output of the control crystal oscillator 315, counts within a period specified by the gate signal, and stores the count value in the memory as an address signal. 305 (309).

As a result, timing signals of various functions and internal control signals are output from the memory 305 (309).
The output of 5 is sent to each part of the transmitter, where it is used for forming various signals, and is also input to the function timing monitor 311. On the other hand, the output of the memory 309 of the monitor function timing generator 306 is directly input to the function timing monitor 311.

In the function timing monitor 311, the deviation detection unit 312 detects a deviation of more than a specified value between the two, and the abnormality determination unit 3+3 determines that the deviation is abnormal if it continues for a predetermined time or more, and outputs a shutdown control signal. Ru.

(Problems to be Solved by the Invention) In the conventional monitor device described above, various timing signals to be monitored are generated anew and compared with the original ones, so that the monitor function timing generator It has the same configuration as the timing generator, and has a redundant circuit configuration. In addition, it is not possible to determine which of the timing signals for monitoring and the original timing signals have deviated, and there is a possibility that it may be determined that there is an abnormality even though there is actually no problem with the original timing signals themselves. There's a problem.

The present invention has been made in view of such conventional problems, and an object thereof is to provide an MLS timing monitor device that can reliably detect deviations in MLS timing with a simple circuit configuration.

(Means for Solving the Problems) In order to achieve the above object, the MLS timing monitor device of the present invention has the following configuration.

That is, the MLS timing monitor device of the present invention
(Microwave Landing System) Each device is installed in the azimuth guidance device, elevation guidance device, and approach/go-around direction guidance device, which are components of the microwave landing system, and each device transmits time-divisionally using radio waves of the same frequency according to a synchronization signal of a predetermined period. MLS that monitors function generation timing individually in each device
In a timing monitor device: When generating corresponding timing signals to generate various functions, means for superimposing a test signal on each timing signal without mutually temporal overlap; and means for separating the timing signal and the test signal. means for detecting the presence or absence of a separated test signal; means for generating a clock for monitoring; 1 - means for forming a signal based on the monitor clock; and means for detecting whether or not the reference clock occurs within the pulse width of the gate signal.

(Function) Next, the function of the MLS timing monitor device of the present invention configured as described above will be explained.

A circuit that generates corresponding timing signals to generate various functions is a circuit that is originally included in the component device, but in the present invention, when generating a timing signal in this circuit, a test signal is superimposed and formed, The presence or absence of that test signal is monitored. If there is a drop in the test signal, it can be assumed that a failure has occurred in a component of the circuit, and the abnormal location can be reliably identified.

Further, since the timing of the function is always confirmed to be within the regulations when installing the MLS ground equipment at the airport, the component equipment normally transmits time-division transmission at the predetermined timing during initial setting.

In other words, timing deviations occur during operation after installation, and the cause is drift due to temperature and aging of the crystal oscillator, which is the clock generation source.

Therefore, in the present invention, a gate signal is formed using a monitor clock, and the transition of the reference clock due to drift is monitored.

Thus, according to the MLS timing monitor device of the present invention, with a simple circuit configuration, it is possible not only to reliably detect deviations in MLS timing, but also to check for failures in the circuit that generates function timing. It is possible to provide a monitor device that can perform effective monitoring.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an MLS timing monitor device according to an embodiment of the present invention. In FIG. 1, a function timing generation section 102 is structurally similar to a conventional function timing generation section 302, but the monitor device of the present invention includes some operations of a counter 104 and a memory +05. Timing generator JO2
The control crystal oscillator 315 can be checked for failures and the drift of the control crystal oscillator 315 can be monitored. This will be explained below with reference to FIG. Note that FIG. 2 shows the case in the apparatus AZ, and the functions are the same as in FIG. 5.

The memory 105 outputs a function timing signal/test signal 106 and a control signal 107, which are as shown in FIG.
Function timing signal/test signal +06 is
One function timing signal is superimposed with a 1-bit test signal (indicated by a square mark in FIG. 2), and each test signal is arranged so as not to overlap with each other in time. 107 is generated at the same timing as each test signal.These test signals and control signal +07 are output from the memory 105 using a predetermined 1 bit in the function timing signal.Therefore, the counter 104 In addition to address signals that generate function timing signals, address signals that generate test signals and control signals 107 are also output.

Function timing signal/test signal separation circuit 1
0♂ uses the control signal 107 as a window signal and separates the function timing signal/test signal +06 into a function timing signal and a test signal. Each separated test signal is detected via the ○, R (OR) circuit 109. The test signal is input to IN+10 and the presence or absence of a test signal is monitored. A dropout in the test signal means that there is a malfunction in the counter gate generator 303, a measurement failure in the counter 104, a bit failure in the memory +05, etc. Therefore, this enables a failure check.

Also, a part of the output of the frequency divider 316 that divides the output of the control crystal oscillator 315 is ANDed with the timer +13.
and one input of the circuit 114. Timer IN is a frequency divider 1 that divides the output of the monitoring crystal oscillator III.
Based on the output clock of 12, the timer gate (Figure 2 (4)
)) and applies it to the other input of AND circuit +14. The pulse width of this timer gate is set to a width corresponding to the allowable width when the timing of the reference clock changes due to the drift of the control crystal oscillator 315, and the reference clock output from the frequency divider 316 is set at the initial setting. The timing is adjusted so that the pulse width falls within this pulse width.

Thus, during operation, if a drift occurs in the control crystal oscillator 315 due to changes in temperature or aging, and this drift exceeds a permissible value, the output of the AND circuit becomes zero, and deviation from the specifications is detected.

(Effects of the Invention) As explained above, according to the MLS timing monitor device of the present invention, instead of generating and monitoring the same function timing, a gate signal is formed using a monitor clock, and Since the transition of the reference clock is monitored and a test signal is superimposed on each function timing and monitored, it is possible to not only reliably detect deviations in MLS timing with a simple circuit configuration, but also to generate function timing. This has the effect of providing a monitor device that can also check for failures in circuits that operate, and can perform reliable monitoring.

[Brief explanation of drawings]

FIG. 1 is a configuration block diagram of an MLS timing monitor device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of the MLS timing monitor device of the present invention in device AZ, and FIG.
FIG. 4 is a block diagram of the configuration of a conventional device, FIG. 4 is a transmission time chart of each function +-, and FIG. 5 is a generation time chart of each function and internal signals in the device AZ. +02...Function timing generation section,
104...Counter, +05...
Memory, +08...Function timing signal/test signal separation circuit, 109,116...
...OR (Oan circuit, 110.115...detection circuit, II!...monitor crystal oscillator,
112,316... Frequency divider, +13 Old...
Timer, +14...AND circuit, 3+5...Control crystal oscillator. Agent Patent Attorney Yoshihiro Hachiman

Claims (1)

[Claims] Each device is installed in the azimuth guidance device, elevation guidance device, and approach/go-around direction guidance device, which are components of the MLS (microwave landing system), and each device transmits time-divisionally using radio waves of the same frequency according to a synchronization signal of a predetermined period. In an MLS timing monitor device that individually monitors the generation timing of each function in each device; when generating corresponding timing signals to generate various functions, a test signal is applied to each timing signal without any temporal overlap. means for superimposing; means for separating the timing signal and the test signal; means for detecting the presence or absence of the separated test signal; means for generating a clock for monitoring; generation of a clock that is a reference for generating the timing signal. means for forming a gate signal based on the monitor clock, the pulse width of which is a permissible drift displacement range of the source; and means for detecting whether or not the reference clock occurs within the pulse width of the gate signal. An MLS timing monitor device characterized by: