JPH0496415A - Logical filter - Google Patents

Abstract

PURPOSE:To obtain a logical filter effective for improving picture quality by comparing the absolute value of an output signal from an intermediate value generating means with the absolute value of a signal at a central sample point in signal trains arranged at prescribed sample intervals, and selectively outputting either the output signal of the intermediate value generating means or the signal at the central sample point based on the output of this comparison. CONSTITUTION:A composite video signal is led into an input terminal 11 and inputted to a 1H delay device 12 and maximum value circuits 16 and 18 in an intermediate value generating circuit 15. The outputs of maximum value circuits 16-18 are inputted to a minimum value circuit 19 of the intermediate value generating circuit 15, and the output is inputted to an absolute value circuit 21 and inputted to a selector circuit 23. In the selector circuit 23, when the output of the absolute value circuit 20 is smaller than the output of an absolute value circuit 21, the output of an inverter 14 is controlled to be selectively led out, and reversely when the output of the absolute value circuit 21 is smaller than the output of the absolute value circuit 20, the output of the intermediate value generating circuit 15 is controlled to be selectively led out. Thus, a characteristic for separating a luminance signal and a chrominance signal can be more improved and the picture quality can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a logical filter that separates a composite video signal into a luminance signal and a chrominance signal.

(Conventional technology) The television broadcasting system currently used in Japan is
The luminance signal and the color signal are frequency multiplexed and transmitted. The receiver separates these signals and demodulates the color signals to reproduce the image. Current home television receivers and video tape recorders (VTRs) have
Two horizontal and vertical frequencies are used to separate luminance signals and color signals.
Two-dimensional filters that separate in dimensional regions are often used.

FIG. 9 shows the configuration of a conventional two-dimensional Y/C separation filter. This filter is composed of a filter that performs vertical separation and a filter that performs horizontal separation, and the blocks surrounded by broken lines in the figure are circuits that extract vertical high frequency components.

A composite video signal is introduced into the input terminal 101, and an IH delay device with a delay amount of one horizontal period (hereinafter referred to as H)]0
2 is input to the coefficient unit 104.

The output of the IH delay device] 02 is further input to an IH delay device 103 and a coefficient unit] 05, and is also input to a subtracter 109. The output of the IH delay device 103 is input to the coefficient multiplier 106 . Coefficients of (-1/4), (1,/2), and (-1/4) are set in the coefficient units 104, 105, and 106, respectively. The outputs of the coefficient multipliers 104, 105, 106 are input to an adder 107, and the outputs of this adder 107 are input to a subtracter 109 and a band pass filter (BPF) 11.
0 is man-powered.

According to the above circuit, the high frequency component in the vertical direction is obtained from the adder 107, and is passed through the bandpass filter 110 to the color 1
I can take out No. 5. This color signal is output from output terminal 11.
2.

Furthermore, in the subtracter 109, a luminance signal is obtained by subtracting the vertical high frequency component (color signal) from the output of the IH delay device 102, and this luminance signal is derived to the output terminal 1].

In addition to the above-mentioned filters, there is a circuit called a logic filter that separates a luminance signal and a color signal. A logical filter regards a signal as a set of patterns and performs filtering by converting these patterns.

FIG. 10 shows an example of the configuration of the above logic filter.

The blocks surrounded by broken lines substantially correspond to the blocks surrounded by broken lines in FIG.

In this circuit, a composite video signal at an input terminal 101 is input to an IH delay device 102, and a minimum value circuit 122,
It is input to the maximum value circuit 125.

The output of the IH delay device 102 is input to the IH delay device 103 and the adder 131 as well as to the inverter 121. The output of the inverter 121 is input to a minimum value circuit 122, a minimum value circuit 123, a maximum value circuit 125, and a maximum value circuit 126. The output of the IH delay device 103 is sent to the minimum value circuit 123.
, are input to the maximum value circuit 126.

[Minimum value circuit] The detection outputs of 22 and 123 are the maximum value circuit 1.
24, and the maximum value output obtained here is input to adder 1
28. Further, the detection outputs of the maximum value circuits 125 and 126 are input to the minimum value circuit 127, and the minimum value output of the minimum value circuit 127 obtained here is input to the adder 128. The output of the adder 128 is sent to the 1/2 coefficient unit 129
The signal is manually inputted to an adder 131 and an inverter 130 via.

The output of the inverter 130 is delivered as a color signal to the output terminal 112 via the bandpass filter 110. Further, an adder 131 adds the output of the IH delay device 102 and the output of the coefficient unit 129, and outputs the result to the output terminal 111 as a luminance signal.

FIG. 11 shows an example of a signal pattern shown to explain the operation of the logic filter.

a, b, and c in the same figure are the IH delay devices 10 in FIG. 10, respectively.
3 shows the signals of the inverter 121 and the input terminal 101. Further, XouL indicates the output from the coefficient unit 129.

When signal patterns such as those shown in (a), (b), (c), and (d) of FIG. 11 are input, the calculation results for X out are as shown in the respective figures.

A step-like signal pattern as shown in FIG. 11(C),
In the case of a linear signal pattern as shown in FIG. 2(d), the median value and the center signal S coincide, so that a signal X out having the same value as the center signal S is obtained. On the other hand, in the case of an impulse-like signal pattern as shown in FIGS. 11(a) and 11(b), the median value and the average value of the center signal S are obtained as the signal X out.

Further, the characteristics of the above circuit will be explained with reference to FIG.

FIG. 12 shows input signals for each scanning line.

In this figure, the output signal of the delay device 103 and the input terminal 10
This indicates that a color carrier wave having the same phase and amplitude value P is superimposed on the signal No. 1, and no carrier wave is superimposed on the signal of the line between them (output of the inverter 121).

Since the minimum value circuit 122 outputs the minimum value of the output signal of the inverter 121, which is the reference potential, and the signal of the input terminal 101, a signal as shown in FIG. 12(d) is obtained. Further, in the minimum value circuit 123, the output signal of the inverter 121 and the I
Since the minimum value of the output signal of the H delay device 103 is
The signal will be as shown in Figure (e). Furthermore, this signal
Since the signal is input to the maximum value circuit 124 and the maximum value is output, a signal as shown in FIG. 12(f) is obtained.

Since the maximum value circuit 125 derives the maximum value of the output signal of the inverter 121 and the signal of the input terminal 101, the first
The signal will be as shown in Figure 2(g). Maximum value circuit 126
Then, the maximum value of the output signal of the inverter 121 and the output signal of the IH delay device 103 is derived, resulting in a signal as shown in FIG. 12(h). This signal is input to the minimum value circuit 127 and the minimum value is derived, resulting in a signal as shown in FIG. 12(i).

The signal in FIG. 12(i) and the signal in FIG. 12(f) are sent to the adder 128.
When added, the signal shown in FIG.
A signal x out shown in Figure (k) is obtained. As a result, from the output terminals 111 and 112, output terminals (1) and (m) in the same figure
A luminance signal and a color signal as shown in the figure are obtained.

Looking carefully at the signal waveform above, the output signal of the IH delay device 102 (intermediate tap signal) originally does not have a color signal (FIG. 12(b)), but the signal at the output terminal 112 It can be seen that a color signal with an amplitude of P/2 is derived (Fig. 12(m)). Further, a luminance signal component ((1) in FIG. 12) is derived from the output terminal 11 (ordinarily, a constant level is sufficient).

In such a case, cross color and cross luminance appear on the screen, degrading the image quality of the video.

As mentioned above, in the case of conventional logic filters, if the input signal is a linear or step pattern, Y/C separation is performed perfectly, but if the input signal is an impulse pattern, incomplete separation occurs, resulting in image quality degradation. becomes a factor.

According to conventional logic filters, when the input signal is a linear or step pattern, Y/C separation is performed perfectly, but when the input signal is an impulse pattern, incomplete separation occurs, which causes image quality deterioration. ing.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a logic filter that has better separation characteristics between luminance signals and color signals and is useful for improving image quality.

[Structure of the Invention (Means for Solving the Problems) This invention comprises an intermediate value generating means for selectively outputting a signal of the (m+1)th magnitude from a (2m+1) signal string lined up at a predetermined sample interval. (m is an integer), a first absolute value circuit that generates the absolute value of the output signal of the intermediate value generating means;
a second absolute value circuit that generates the absolute value of a signal at a central sample point among the (2m+1) signal strings lined up at the predetermined sample interval; and magnitudes of output signals of the first and second absolute value circuits. The apparatus is equipped with a comparison means for performing a comparison, and a selection circuit for selectively outputting either the output signal of the intermediate value generation means or the center sample point signal for the comparison output of the comparison means.

(Function) With the above means, it is possible to obtain a mode in which the signal at the central sample point is directly derived, so that even with an impulse-like input signal pattern, an accurate filter output can be obtained.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. A composite video signal is introduced into the input terminal 11 and input into the IH delay device 12 and the maximum value circuit 16 and maximum value circuit 18 of the intermediate value generation circuit 15. The output of the IH delay device 12 is input to the IH delay device 13 and also to the inverter 14. Inverter 1
The output of 4 is input to the maximum value circuit 16.17. The output of the IH delay device 13 is also input to maximum value circuits 17 and 18.

The 1H delay devices 12 and 13 create a plurality of sample signals with different delay times, and the output signal of the inverter 14 is supplied to the absolute value circuit 20 and the selection circuit 23.

The intermediate value generation circuit 15 has a minimum value circuit 19, and the outputs of the maximum value circuits 16, 17, and 18 are input to the minimum value circuit 19. The output of the minimum value circuit 19 is the absolute value circuit 2.
1 and is also input to the selection circuit 23.

Here, the outputs of the absolute value circuits 20 and 21 are input to a comparator 22 and compared in magnitude. The determination signal obtained from the comparator 22 is input to the selection circuit 23, and when the output of the absolute value circuit 20 is smaller than the output of the absolute value circuit 21, the determination signal obtained from the comparator 22 is input to the selection circuit 23.
Conversely, when the output of the absolute value circuit 21 is smaller than the output of the absolute value circuit 20, the output of the intermediate value generating circuit 15 is controlled so as to be selectively derived. . The signal selected by the selection circuit 23 is output to the output terminal 24.

Figure 2 shows a first step to explain the operation of the above logic filter. This is an example of a signal pattern shown for this purpose.

As shown in FIG. 1, the output signal of the 1H delay device 3 is a1, the output signal of the inverter 14 is b1, and the signal of the input terminal 11 is C. Now, assuming that the signal pattern is as shown in FIG. 2(a), the maximum value detection circuit 6 compares the signals S and C, and derives the signal S. In addition, in the maximum value circuit 17, the signals S and A are compared, so that the signal S is output. Furthermore, the maximum value circuit 18 compares signals c and a, and outputs signal a. Therefore, the minimum value circuit 19 outputs the signal a. That is, the minimum value circuit] 9 outputs the median value. The absolute value of this signal is taken by the absolute value circuit 21 and input to the comparator 22. On the other hand, the absolute value of the signal output from the inverter 14 is taken by an absolute value circuit 20 and input to a comparator 22. Figure 2 (
In the case of the signal pattern a), the comparator 22 obtains a judgment output indicating that the absolute value of the signal S is small.

As a result, the selection circuit 2B outputs the output f- from the inverter 14.
Select and derive the number.

In the case of a signal pattern as shown in FIG. 2(b), the intermediate value circuit 15 outputs the signal a as the median value, and the signal A as the central sample point signal. When the absolute values of these signals are compared, the absolute value of the center signal S is smaller, so the selection circuit 23 selects and derives the signal S.

In the case of signal patterns as shown in Fig. 2(C) and Fig. 2(d), the center sample point signal and the signal that takes the median value are equal, so in the case of Fig. 2(C), the signal or C
Either one of them is output, and in the case of FIG. 2(d), the signal S is output.

As described above, for an impulse-like signal pattern, a mode for directly deriving the center sample point signal can be formed.

Next, a Y/C separation circuit using the above logic filter will be explained with reference to FIG.

The center sample point signal is further input to an adder 24, where the same parts as in FIG.

Further, the output signal of the selection circuit 23 is input to the adder 24 and also to the inverter 26. This inverter 26
The output of is led out to an output terminal 28 as a color signal via a bandpass filter 27. The output of adder 24 is delivered to output terminal 25 as a luminance signal.

FIG. 4 shows an example of signal waveforms at various parts of the above circuit.

Figure (a) shows the IH delay device] Output signal a1 of 3 (Figure (b))
is the output signal b1 of the inverter 14, and (c) is the input terminal 11.
This is signal C. The intermediate value generation circuit 15 performs a logical operation based on magnitude detection based on the principle described above, and obtains a signal with a waveform as shown in FIG. 4(d). The signal indicating this median value and the absolute value of the output signal (b) of the inverter 14 are compared in a comparator 22. As is clear from the figure, in this example, the output signal of the inverter 14 is small. Therefore, as shown in FIG. 4(e), the selection circuit 23 directly derives the inverted signal of the central sample point. Figure 4 (f
) is the output signal of the absolute value circuit 21.

The output of the selection circuit 23 (inverted signal of the center sample point) and]
The center sample point signal from the H delayer 12 is the center sample point signal from the adder 2
4 and is added and output as a luminance signal to the output terminal 25 (FIG. 4(g)). Further, the signal selected by the selection circuit 23 is inverted by an inverter 26, and is output as a color signal to an output terminal 28 via a bandpass filter 27 (FIG. 4(h)).

As in this operation example, the mode in which the inverted signal of the central sample point is derived and the intermediate value derivation mode are selectively formed by comparing absolute values, and the luminance and color separation operations become accurate.

Further, an example of the operation of the above circuit will be explained with reference to FIG.

FIG. 5(a) shows the output signal a1 of the IH delay device 13 (
b) is the output signal b1 of the inverter 14, and (c) is the signal C of the input terminal 11. Here, it is assumed that the signals a and C have the same phase and the same amplitude, and the signal A has the same phase but different amplitudes.

When such a signal is input, a signal C or a signal a is derived from the intermediate value generation circuit 15 as shown in FIG. 5(d).

Furthermore, when the absolute value of this signal is taken, a signal waveform as shown in FIG. 5(f) is obtained. On the other hand, the absolute value output of the signal is as shown in FIG. 5(e). When these two absolute value outputs are compared, the output of the absolute value circuit 20 is smaller than the output of the absolute value circuit 21. Therefore, from the selection circuit 23, the output signal (b) of the central inverter 14 (FIG. 5(g)
) is derived.

When the signal in FIG. 5(g) is input to the adder 24, I
Since a signal having a polarity completely opposite to that of the signal shown in FIG. 5(g) is inputted from the H delay circuit 12, a luminance signal as shown in FIG. 5(h) is obtained. On the other hand, as for the color signal, the signal derived from the selection circuit 26 is inverted by the inverter 26 and is derived via the bandpass filter 27.

In this way, the center sample point signal (center signal) is
If the chrominance carrier amplitude is smaller than that of the pre-IH signal, the luminance signal and chrominance signal can be completely separated. In general, when Y/C separation is incomplete, cross luminance is particularly noticeable when the color subcarrier amplitude is small, but under such conditions, the filter in this example is extremely effective in achieving complete separation. Useful.

The above Y/C separation is a circuit that separates a luminance signal and a color signal using a signal pattern in the vertical direction, but the present invention also applies to a circuit that separates a luminance signal and a color signal using a signal pattern in the horizontal direction. is applicable.

FIG. 6 shows another embodiment of the invention.

A composite video signal is input to an input terminal 31 and is input to a delay device 33 and a demodulator 34 via an AC coupling circuit 32 . The demodulator 34 extracts the color signal through a bandpass filter and supplies it to the logic filter 35 .

The logic filter 35 has the same circuit configuration as shown in FIG. 1, but the IH delay devices 12 and 13 in FIG. 1 are replaced with unit delay devices. The output of the logic filter 35 is led out to an output terminal 39 as a demodulated color signal, and is also input to a modulator 36 where it is converted back into a color signal at the original frequency. The output signal of this modulator 36 is input to a subtracter 37.

The subtracter 37 subtracts the color signal from the output signal of the delay device 33 and outputs a luminance signal to the output terminal.

FIGS. 7 and 8 show signal waveforms at various parts of the circuit that separates the luminance signal and color signal using the horizontal signal pattern as described above. The signal waveform in FIG. 7 is the signal waveform when a conventional logic filter is used, and FIG. 8 is the signal waveform when the logic filter of the present invention is used.

7 and 8, (a) shows the output signal of the AC coupling circuit 32, (b) shows the demodulated output from the demodulator 34, and (c) shows the output of the logic filter. Same figure (
d) is the output of the modulator 36, and (e) in the figure is the luminance signal output from the adder 37.

In the conventional logical filter, as shown in FIG. 2(b), sample point signals 1. When m and n are input, the average value of the median value and the center signal is output, so the sample point signal q becomes a signal different from the demodulated signal m, as shown in FIG. When this is modulated (see (d) in the same figure) and subtracted from the input signal, the color carrier wave component remains as shown in (e) in the same figure, and cross luminance occurs.

On the other hand, when using the logical filter 35 of the present invention, the smaller absolute value of the median value and the center signal is selected and derived (sample point signal pq-r''), so the same signal as the demodulated signal is obtained. Therefore, when this signal is subtracted from the input signal, no color carrier component remains in the luminance signal as shown in FIG. 8(e).

This logic filter can be applied not only to Y/C separation but also to various circuits. For example, this is high-frequency component extraction from a contour correction circuit, etc. , [Effect of the invention] As explained above, according to the logical filter of this invention,
It has better separation characteristics between luminance signals and color signals, and is useful for improving image quality.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is an explanatory diagram showing signal patterns for explaining the operation of the circuit shown in Fig. 1, and Fig. 3 is a Y/C to which this invention is applied. 4 and 5 are diagrams showing signal waveforms shown to explain the operation of the circuit in FIG. 3, and FIG. 6 is a diagram showing a Y/C separation circuit to which the present invention is applied. FIGS. 7 and 8 are signal waveform diagrams shown to explain the operation of the circuit in FIG. 6, and FIGS. 9 and 10 are diagrams showing conventional Y/C separation circuits. , FIG. 11 is a signal pattern diagram shown to explain the operation of the logic filter of FIG. 10, and FIG. 12 is a signal waveform diagram shown to explain the operation of the circuit of FIG. 10. 12.1B... IH delay device, 14... Inverter, 15
...Intermediate value generation circuit, 20.21...Absolute value circuit,
22... Comparator, 23... Selection circuit, 24... Subtractor, 26... Inverter, 27... Band pass filter. Applicant's agent Patent attorney Takehiko Suzue Figure 8 Figure Q Ward 4; -128 output (k) out (L') Teru no 1j i name (m) color i name number 12

Claims (2)

[Claims] (1) an intermediate value generating means for selectively outputting a signal of the (m+1)th magnitude from a (2m+1) signal string lined up at a predetermined sample interval (m is an integer); a first absolute value circuit that generates an absolute value; a second absolute value circuit that generates the absolute value of a signal at a central sample point among the (2m+1) signal strings arranged at the predetermined sample interval; Comparing means for comparing the magnitudes of the output signals of the first and second absolute value circuits, and selecting and outputting either the output signal of the intermediate value generating means or the central sample point signal based on the comparison output of the comparing means. 1. A logical filter comprising: selection means for selecting a logical filter; (2) The comparing means controls the selecting means to selectively output the output signal of the intermediate value generating means and the central sample point signal, whichever has a smaller absolute value. The logical filter described in item 1.