JPH049346B2 - - Google Patents

Description

[Detailed description of the invention]

[Field of Application of the Invention] The present invention relates to a memory management unit for an information processing system, and particularly to a memory management unit suitable for a system requiring high integration and high-speed memory access. [Background of the Invention] Conventional highly integrated information processing systems using CMOS or the like generally have the configuration shown in FIG. 2. In the figure, arithmetic processing unit 1
is for decoding and executing programs, and is for CMOS
It is realized on a single chip using logic. The address translation unit 2 dynamically allocates the logical address sent by the arithmetic processing unit 1 to a physical address and sends it to the system bus 3 in order to support the virtual storage space. Main memory 4 stores programs and data, and I/O adapter 5 supports communication between system bus 3 and I/O bus 6. The file control processor 7 controls, for example, the disk drive 8 and executes direct memory access (hereinafter referred to as DMA) to the main memory 4. In the system configuration as described above, memory accesses from the arithmetic processing unit 1 associated with instruction fetches and operand fetches are performed by the address conversion unit 2.
After the logical address is converted into a physical address, the main memory 4 is accessed directly.
Conventionally, there was no significant difference between the processing speed of the arithmetic processing unit and the access speed of the dynamic RAM that constitutes the main memory, and the above system configuration was able to sufficiently bring out the performance of the arithmetic processing unit. However, with the advancement of CMOS process technology,
The degree of integration of elements is increasing, and as a result, arithmetic processing units tend to be faster due to higher functionality and shorter element delay times. In contrast, with dynamic RAM used for main memory, the access speed remains constant and emphasis is placed on high density, so the difference between the processing speed of the arithmetic unit and the access speed of the main memory is increasing. . In order to take full advantage of the performance of high-speed arithmetic processing devices, a cache device that serves as a buffer between the two devices and stores a portion of the main memory in a high-speed, small-capacity memory has come to be required. Furthermore, in the field of artificial intelligence, which has recently attracted attention, programming languages that can handle predicate logic, such as hardware that can process prologues at high speed, are required, but since these languages are based on stack operations, It is characterized by higher memory access frequency than conventional languages. Here too, the realization of a cache memory that is effective in speeding up memory access is becoming an important issue. The conventional method of realizing cache memory is as follows.
The configuration shown in FIG. 3 is common. That is, after converting the logical address 89 into a physical address 90 by the address conversion buffer 84, the directory 85
The comparator 88 compares the output of the directory with the physical address 90, and if they match, the selector 87 selects the corresponding data. This configuration can be converted to VLSI
When applied to a highly integrated information processing system using technology, the following problems occur. (1) The cache memory uses a set associative method to improve the hit rate, and the number of sets is usually about 2 to 4. Therefore, the directory and cache data sections consist of 2 to 4 planes and need to be accessed in parallel.
At this time, the word length of the memory used for the cache data section is, for example, 8K words when a cache memory with a capacity of 64KB and a bandwidth of 4B is implemented using the 2-set associative method. However, using existing high-density technology, memory with a single address space of 8K words or more, for example 16K words (0 to 15999 in decimal format), has a higher degree of integration. Such long word length memory cannot be fully utilized, leading to an increase in the amount of hardware. (2) At the time of a read request, it is possible to access the directory and cache data section in parallel, but at the time of a write request, it is necessary to start writing to the cache data section using the result of comparing the directory output and the physical address. Because of this, parallel processing is not possible and access becomes slow. Figure 4 also shows that the mainframe is a high-performance minicomputer, and for the purpose of high-speed access,
The adopted cache configuration is shown. In this configuration, the address translation buffer 92 performs address translation, and at the same time, the directory 93 and cache data section 94 are accessed using an offset 97 in the logical address 99 that does not depend on address translation, and the physical address 98 obtained by address translation and the output of the directory are accessed. After the comparison is made by the comparator 95, if there is a hit, the corresponding data is selected by the selector 96. With this configuration, access is fast, but since the directory and cache data sections are accessed at offsets, the number of sets becomes considerably large. For example, to achieve a cache with a page size of 4KB and a capacity of 64KB, the number of sets is 16. Therefore, when considering application to a VLSI system, the word length of one plane of the cache data section is shorter than in the cache implementation example described above, and this is accessed in parallel, which makes effective use of memory that is long in the word direction. becomes even more unsuitable, and the problem arises that the amount of hardware increases. Next, an actual known example of memory management using VLSI technology is the "Preliminary Product Spacing" of Zilog's CPU.
As described in the Preliminary Product Specification, a device has been proposed in which a small-capacity cache memory is provided within a chip of an arithmetic processing unit. That is, as shown in FIG. 5, the arithmetic processing device 1,
A device 1 in which an address conversion section 2, a directory 9 and a cache data section 10 are mounted on one chip.
It is 1. However, this implementation method has the following problems. (1) There is a limit to the amount of hardware that can be put on-chip.
Since the cache capacity is limited, the cache hit rate is low and the performance of high-speed computing devices expected in the future cannot be fully exploited. (2) From file control processor 7
Overhead is required to match the contents of the main memory 4 and the cache memory 10 for memory access by other bus masters such as DMA transfer. Another known example is Signetaix's "Basic Memory Access Controller".
(Basic Memory Access Controller) address information (Advanced Memory Access Controller)
As described in ``Information'', a memory management unit has been proposed in which an address conversion section and a cache directory are integrated into one chip. That is, as shown in FIG. 6, this is a device 12 in which the address conversion section 2 and the tag comparison section 9 of the cache memory are integrated into one chip. The problems in this case are: (1) In order to speed up access, a method is used to search the cache using logical addresses, but this method does not support multiple virtual spaces, which is a feature of UNIX, which is currently becoming the mainstream OS. In this case, it is necessary to clear the cache every time the task is switched, resulting in a decrease in hit rate. (2) Similar to the prior art example, overhead is required to match the main memory and cache memory for DMA transfer. [Object of the Invention] A first object of the present invention is to provide a memory management unit that improves the throughput of cache access. A second object of the present invention is to provide a memory management unit that realizes a large capacity cache memory with a small amount of hardware. A third object of the present invention is to provide a memory management unit that facilitates ensuring consistency between a cache memory within an arithmetic processing unit and a main memory. [Summary of the Invention] The first and second objects described above are to cause a memory management unit to perform address translation and cache tag comparison in parallel by searching the directory section using an offset section of a logical address that does not depend on translation. means for generating an address of a cache data section by combining information obtained by encoding a cache tag comparison result with an offset section of a logical address; means for holding an address of the cache data section; This is achieved by providing means for reading out the cache data section according to the address of , and means for performing pipeline operation of the cache tag comparison and the readout of the cache data section. In the above memory management unit, since the cache directory is searched at the offset portion of the logical address that does not depend on address translation, address translation and cache tag comparison can be performed in parallel. Furthermore, since the cache data section is read using an address that combines the information encoded from the cache tag comparison result and the offset section of the logical address, the cache data section can be read out without having to divide the cache data section into multiple sets and read them in parallel. Associative type cache memory can be realized. Furthermore, the means for holding the address of the cache data section enables pipeline processing of the parallel execution stage of address conversion and cache tag comparison and the cache data section access stage. The third purpose is to provide the memory management unit with
a receive latch register that holds a memory access address from an input/output device such as a DMA device; a first selector that selects an offset portion of the receive latch register and an offset portion of a logical address from the arithmetic processing unit; a second selector for selecting a physical page number of a register and a physical page number generated by the address translation buffer; means for searching a cache directory based on the access address of the selected input/output device; and encoding a cache tag comparison result. By providing means for generating the address of the cache data section by combining the information and the offset section of the access address of the input/output device, and means for reading the data of the cache data section using the address of the cache data section. , achieved. The memory management unit that achieves this third purpose has a means for selecting an access address from an arithmetic processing unit and an access address from an input/output device, and an offset between information encoded as a result of comparing cache tags and the access address of an input/output device. The means for reading out the cache data section by reading out the cache data section makes it possible to read out the cache memory directly from the input/output device. Thereby, all accesses from the input/output device can be made via the cache memory, and it is possible to easily guarantee consistency between the cache memory and the main memory. [Embodiments of the Invention] Examples of the present invention will be described below with reference to the drawings. FIG. 7 shows an example of the configuration of a system using the unit of the present invention.
It is integrated into one chip using CMOS logic, and when accessing memory, it sends a request signal, a 32-bit logical address, and a 3-bit address space signal.
That is, main memory physical address space and I/
A signal distinguishing the O bus from the physical address space is transferred to the memory management unit 13. main memory 4
It has a 27-bit address space, a capacity of 128MB, and is constructed using dynamic RAM.
The I/O adapter 5 has an internal address conversion table and has the function of converting logical addresses on the I/O bus 6 into main memory physical addresses in response to DMA transfer requests from the file control processor 7, etc. . This allows the bus master on the I/O bus 6 to dynamically use the main memory. The object of the present invention is the memory management unit 1.
3, and its internal configuration is shown in FIG. An address line 17 and a data line 18 are connected to the arithmetic unit 1.
It is connected to the main memory 4 through an address line 21 and a data line 22, and connected to the I/O adapter 5 through an address line 19 and a data line 20. The address generation chip 14 is a feature of the present invention, and an embodiment thereof will be explained later with reference to FIG. receives a logical address from an arithmetic device or a physical address from a DMA device, and generates a cache address and a physical address in one cycle. It is made into a single chip using CMOS microfabrication technology. Cash data section 1
5 is a data storage section of cache memory;
High-speed static RAM with 64KB capacity
This is realized using Interface section 16
is realized with a gate array, etc., and has a main memory and a write buffer to the I/O adapter, etc.
Control the flow of data. The operation of this memory management unit 13 is as follows. (1) Processing for a read request from an arithmetic unit The processing flow is shown in FIG. A read request signal, a logical address 17, and an address space signal from the arithmetic unit 1 are received by the address generation chip 14, and the logical address is first converted into a physical address by an address conversion section. The cache's tag is then compared using the resulting physical address and address space signals. As a result, if the target data exists in the cache, a cache address 23 is generated, the data is read from the cache data section 15, and the data line 18 is read out.
Data is transferred to the arithmetic device 1 through the arithmetic unit 1.
If the target data does not exist in the cache, the requested space is distinguished from the address space signal, and if it is the main memory space, the address line 2
1, if it is an I/O space, sends the physical address to the address line 19 and sends the physical address to the memory management unit 13.
Request data transfer to. Data from the memory space is written to the cache data section 15 in units of 32 bytes through data lines 22 and 24.
Data from the I/O space is transferred to interface section 1.
After being written into the buffer No. 6, the requested data is transferred to the arithmetic unit via the data line 18. (2) Processing for a write request from an arithmetic unit The processing flow is shown in Figure 10. A write request signal, logical address 17, and address space signal from the arithmetic unit 1 are received by the address generation chip 14, and write data is received by the interface section 16 through the data line 18. First, the address generation chip 14 converts a logical address into a physical address. Next, the target space is identified from the address space signal, the physical address is written, and the write data is written to the write buffer of the corresponding space. At this time, the cache tags are also compared, and if the target data depends on the cache, it is written into the cache data section 15 via the data line 24. If it does not exist in the cache,
No operation is performed on the cache data section 15. (3) Processing for access from DMA device Processing for access from file control processor 7, etc.
When a DMA transfer request is made, the I/O adapter 5 first converts the logical address in the I/O bus space 6 into a physical address in the main memory space. The result is transferred to the address generation chip 14 through the address line 19, and a cache memory search is executed. The above memory access operations are executed at high speed,
The key to realizing this with a small amount of hardware is the address generation chip 14, an embodiment of which is shown in FIG. In the figure, the input is a physical address 19 from the I/O space, a logical address 17 from the arithmetic processing unit, and the output is a physical address 21 and a cache address 23 to the main memory or I/O space. Also, latch registers 25, 2
6, 27, 28, 100, and 101 are through latches used as pipeline registers.
The logical address tag holding unit 31, the physical address tag holding unit 32, the comparator 33, and the selector 34 are as follows:
It constitutes an address translation buffer (TLB) to speed up address translation. As shown in Table 1, this uses a two-way set associative method, and each set has 128 entries for combinations of logical addresses and physical addresses. The replacement algorithm replaces the page that was not accessed most recently for each column.
The LRU method will be used.

[Table] Selectors 29 and 30 are selectors for selecting a request from the arithmetic device 1 and a request from the DMA device. The directory 35 holds as its contents the upper 15 bits of the physical address corresponding to the data in the cache, and is accessed using the 12 bits of the offset part, which does not depend on address translation. Therefore, the cache data capacity corresponding to one set is limited to 4KB. Therefore, in order to obtain the target cache capacity of 64KB, a method is used in which 16 sets are accessed in parallel. The tag comparison unit 36 compares the upper 15 bits of the physical address obtained by address conversion of the access address with the corresponding tag of each set (the upper 15 bits of the physical address of the data on the cache) to check for a match. The encoding unit 37 is the tag comparison unit 36
The information obtained is encoded to generate the upper 4 bits of the cache address. The cache memory has the characteristics shown in Table 2, corresponding to the directory 35 mentioned above.

〔Effect of the invention〕

According to the first invention, the following effects (a) and (b) can be obtained, and according to the second invention, the following effect (c) can be obtained. (a) Address conversion and cache tag comparison can be executed in parallel, and the parallel execution stage of address conversion and cache tag comparison and the cache data section access stage can be processed in a pipeline. This greatly improves the throughput of cache access. (b) Since the cache data section is read by an address that combines the information encoded by the cache tag comparison result and the offset section of the logical address, it is not necessary to divide the cache data section into multiple sets and read them in parallel. A set associative type cache memory with a high hit rate can be realized. As a result, even if the cache memory becomes large in capacity, there is no need to read out the cache data portion in parallel, and it becomes possible to realize a large capacity cache memory with a small amount of hardware. (c) By selecting the access address from the processing unit and the access address from the input/output device, all accesses from the input/output device can be made via the cache memory, and the cache memory for access from the input/output device is It is possible to easily guarantee consistency between the storage memory and the main memory.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of an address generation chip that is a feature of the present invention, FIG. 2 is a configuration diagram of a conventional information processing system, FIG. 3 is a configuration diagram of a general cache memory, and FIG. The figure shows a configuration diagram of a cache memory that can be accessed at high speed and is used in mainframes, etc. Figure 5 is a system configuration diagram using a CPU manufactured by Zilog, and Figure 6 is a system configuration diagram using a memory management unit manufactured by Signetakes. 7 is a system configuration diagram using the unit of the present invention, FIG. 8 is an internal configuration diagram of a memory management unit using the address generation chip of FIG. 1, and FIGS.
The figure shows a flowchart of a memory read flow and a memory write by the memory management unit in FIG. 8, FIG. 11 is an explanatory diagram of logical addresses, FIG. FIG. 15 is a state transition diagram of the cycle controller and its configuration diagram, FIG. 15 is a state transition diagram of the second cycle controller, and FIG. 16 is a time chart of pipeline operation of memory access. 13...Memory management unit, 14...Address generation chip, 15...Cache data section, 2
5, 26, 27, 28, 100, 101... Latch register, 29, 30... Selector, 31...
Logical address tag holding unit, 32... Physical address tag holding unit, 33, 36... Comparator, 34... Selector, 35... Directory, 37... Encoder.

Claims (1)

[Claims] 1. An address conversion buffer that receives a logical address from an arithmetic processing unit, converts the logical page number that is part of the logical address into a physical page number, and generates a physical address, and a search using the generated physical address. In the memory management unit, which consists of a directory part of the cache memory that is stored in means for executing address translation and cache tag comparison in parallel by searching the directory section using an offset section that is not stored; means for generating the cache data section; means for holding the address of the cache data section; means for reading the cache data section based on the address of the cache data section; and a pipeline operation for comparing the cache tags and reading the cache data section. A memory management unit characterized in that it is provided with means for controlling. 2. An address conversion buffer that receives a logical address from an arithmetic processing unit, converts the logical page number that is part of the logical address into a physical page number, and generates a physical address, and a cache memory that is searched using the generated physical address. A memory management unit consisting of a directory section and a data section of a cache memory that holds part of the data in the main memory and is read out using the generated physical address, handles memory access addresses from input/output devices such as DMA devices. A receive latch register to be held, a first selector that selects an offset part of the receive latch register and an offset part of the logical address from the arithmetic processing unit, a physical page number of the receive latch register, and the address translation buffer are generated. a second selector for selecting a physical page number; means for searching a cache directory according to the access address of the selected input/output device; and information encoding the cache tag comparison result and an offset part of the access address of the input/output device. 1. A memory management unit comprising: means for combining to generate an address of a cache data section; and means for reading data of the cache data section using the address of the cache data section.