JPH049018B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a waveform compensation device that compensates for harmonic distortion generated in a power supply system by a load.

In recent years, as semiconductor switch control devices have come to be used for loads and the like, harmonic distortion in power supply systems has become a problem. For example, as shown in FIG. 4, when a rectifier circuit is connected to an alternating current power supply AC, a square wave current I _L that matches the power supply cycle flows.
To solve this problem, control has conventionally been carried out using L and C filters between the power supply and the load. L and C filters are often used in the form of resonant shunts according to the harmonic order;
Since the C filter is for correcting voltage distortion, the degree of waveform improvement was not satisfactory. Furthermore, since the L and C filters are large in size, there is also the drawback that the entire device becomes large in size.

In order to eliminate the above drawbacks, voltage and current distortion can be compensated with high precision by using a harmonic filter using a power converter with active elements.
Moreover, the applicant of the present application has already proposed a waveform compensation device that can be manufactured in a small size (Japanese Patent Laid-Open No. 139031/1983).

SUMMARY OF THE INVENTION An object of the present invention is to provide a waveform compensator using a harmonic filter using an active element, which can supply an optimal compensation current regardless of changes in the harmonic current level of a load.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In FIG. 1, 1 is an AC power supply, 2 is a load which is a harmonic generation source, 3 is a line, and 4 to 7 are power converters. 4 is a harmonic removal LC filter, one end of which is connected in parallel to the line 3, and the other end connected to the first winding 5a of the transformer 5. The second winding 5b of the transformer 5 has a midpoint 5c, and the winding 5
The anodes of the self-arc-extinguishing semiconductor elements 6a and 6b are connected to both ends of b, and the cathodes thereof are commonly connected. Reference numeral 7 denotes a DC reactor that serves as a DC power source. A self-arc-extinguishing semiconductor element 6c is connected in parallel to this DC reactor 7, one end of which is connected to the midpoint 5c of the second winding 5b, and the other end connected to the element. It is connected to a common connection point on the cathode side of 6a and 6b. 8 is a detector for load current i _L , and 9 is a detector for DC current i _D.

a self-extinguishing semiconductor element 6a of the power converter;
The pulse width of 6b is controlled by the output of a control circuit described below, and the semiconductor element 6c is turned on at the same time as 6a and 6b are turned off, so that unnecessary current does not flow through the transformer 5.

The output of the load current detector 8 is sent to the load 2 via a band reject filter 10 that blocks only the fundamental wave.
The harmonic current i _LR of is extracted. This harmonic current
_iLR is input to the set value determining circuit 11, and the set value _iS of the DC current _iD corresponding to its level is taken out from the set value determining circuit 11. This set value i _S is set to the peak value of the effective value of the current signal i _LR . The set value i _S is compared with the output i _D of the DC current detector 9, and the difference between the DC levels of both signals (current difference for waveform compensation) is calculated.
is taken out, and this signal is input to the first input Y of the multiplier 12.
be made into The _second input of this multiplier 12 is given _a signal An output including the polarity of the power source 1 is taken out. This output is a DC current control signal that is passed to the DC reactor 7 through a bandpass filter 12A that has a passband in the fundamental frequency band of the power supply 1.
S _D is taken out. Here, bandpass filter 1
2A is the power supply current i _i by controlling the current i _D
This is to prevent harmonic current from flowing to the

On the other hand, the harmonic current i _LR of the load and the DC current i _D are inputted to a divider 13, and a signal S _R (compensation signal) obtained by calculating the ratio i _LR /i _D of both currents is taken out. This divider ₁₃ is provided to prevent the gain of the compensation current (the ratio of the level of the current _iD to the level of the current _iLR ) from changing due to the current iD, and to keep the gain constant. This constant gain reduces the generation of unnecessary harmonics, as will be described later.

The compensation current signal S _R and the above-mentioned DC current signal S _D are added and used as a comparison input signal S of the comparator 14 . A comparison standard for the comparator 14 is provided by a triangular wave generator 15 that outputs a triangular wave signal synchronized with the power supply 1, and a pulse width modulated PWM signal corresponding to the level and polarity of the signal S is taken out from the comparator 14. This PWM signal is applied to the logic circuit 16.
A gate signal synchronized with the frequency of the power source 1 is taken out. This gate signal is gate circuit 1
7, the self-arc-extinguishing semiconductor element 6
It is used as an on/off control signal for a, 6b, and 6c.
Note that the triangular wave generator 15 is synchronized with the power source 1 by, for example, a phase lock loop (PLL), and generates a triangular wave having a frequency that is an integral multiple of the frequency of the power source 1.

The operation of the compensation device having such a configuration will be explained with reference to the waveform diagram of each part shown in FIG.

When the load 2 is a rectifier circuit shown in FIG. 4, the load current i _L becomes a distorted square wave current as shown in FIG. 2a. The difference (distortion) between this distorted current and the case where the current i _i from the AC power source 1 becomes a sine wave as shown in FIG. 2a is as shown in FIG. 2b. This difference is detected by the band reject filter 10 as a harmonic current i _LR , and by flowing a current with the opposite polarity of the waveform of the difference as a compensation current I ₀ shown in FIG. 2b, the current i _i becomes a sinusoidal waveform. Become.

To generate the compensation current _I0 , the DC reactor 7 is used as a current source that flows a constant current _iD , and the semiconductor elements 6a, 6
This is done by pulse width control of b and 6c. That is, during the positive polarity period _TP of the compensation current _I0 , the semiconductor element 6a is controlled on/off according to the PWM waveform with a pulse width proportional to the level of the period, and similarly during the negative polarity period
At T _N , the semiconductor element 6b is on/off controlled according to the PWM waveform, and the winding 5a or 5b of the transformer 5 is
In this case, a current with a PWM waveform as shown in Figure 2g is obtained. This current is passed through filter 4 to remove harmonics included in the triangular wave from the PWM waveform.
I get ₀ .

Here, during the off period of the semiconductor element 6a or 6b, the semiconductor element 6c is turned on, and the current of the DC reactor 7 continues to flow in a loop through the semiconductor element 6c, and unnecessary harmonic current flows through the transformer 5 to the power supply side. prevent. Further, the filter 4 is connected to a reactor L as shown in FIG. 3, for example.
A one-stage LC filter having a capacitor C and a triangular wave frequency component included in the PWM waveform is removed to obtain the waveform of the compensation current _I0 .

Next, the generation of a PWM waveform according to the harmonic current i _LR will be explained. In the divider 13, the harmonic current
By dividing i _LR by the magnitude of the DC current i _D , the ratio to the DC current i _D is made constant. If the ratio of the output S _R of the divider 13 to i _D is 1 and the signal S _D is zero, it will match the signal S, and as shown in Figure 2e, the signal S _R will have a waveform that matches the compensation current I ₀ . Become. The comparator 14 compares this signal S with a triangular wave signal synchronized with the power supply 1 as shown in FIG. 2f, and the PWM waveform shown in FIG. 2g is obtained as the output. The logic circuit 16 detects the semiconductor element 6 from the PWM waveform.
The gate circuit 17 generates on-pulses for the semiconductor elements 6a, 6b, and 6c, and amplifies the power of the on-pulses, respectively, to generate gate pulses for the semiconductor elements 6a, 6b, and 6c.

Here, the division by the divider 13 is to set a constant ratio (gain constant) to the current value i _D of the DC reactor 7, and this means that the peak value of the signal S with respect to the triangular wave signal peak level of the triangular wave generator 15 is Always maintain a constant ratio. As a result, the PWM waveform generation of the comparator 14, that is, the modulation rate in PWM modulation becomes constant regardless of the level change of the harmonic current _iLR , and as shown in FIG. 2f, the signal S=( =S _R ) gives a constant and high modulation rate. By increasing this modulation rate, the content rate of unnecessary harmonic components caused by the frequency of the triangular wave (carrier wave) is reduced in the PWM form after modulation. Thereby, harmonic components can be removed by simplifying the filter 4, such as by using a one-stage LC filter as shown in the configuration shown in FIG. In this respect, the device disclosed in Japanese Patent Application Laid-Open No. 55-139031 does not have a divider, and the modulation rate changes.

Next, the current i _D secured in the DC reactor 7 is controlled by the path between the multiplier 12 and the filter 12A according to the magnitude of the harmonic current i _LR . The set value determination circuit 11 obtains the peak value of the effective value of the harmonic current i _LR as the set value i _S of the current i _D. As shown in Fig. 2c, this set value i _S is compensated according to the maximum level of the harmonic current i _LR by full-wave rectifying the harmonic current i LR and converting it to direct current, and setting it as its peak _value . Current I ₀
to occur.

The current i _D of the DC reactor 7 is compared as a feedback signal with respect to the set value i _S , and the current increase/decrease of the DC reactor 7 is controlled according to the deviation.
For this current increase/decrease control, the bias amount S _D of the compensation current I ₀ is
is added to the signal S _R as
is added as the pulse width increment/decrement of the PWM waveform,
This is done by supplying current from a power source 1 through a transformer 5.

At this time, the multiplier 12 multiplies the power supply voltage signal by the deviation (i _D -i _S ) so that the current supplied from the power supply 1 to the transformer 5 matches the voltage phase of the power supply 1 .
Since this power supply voltage signal includes a PWM waveform component and a harmonic current _iLR , the fundamental wave component of the power supply 1 is extracted in the bandpass filter 12A and obtained as a signal S _D. Figure 2d shows the signal S _D when there is a deviation, and this signal S _D is the output of the divider 13.
The signal S ( _second
(see Figures e and f) are the inputs of the comparator 14.

Therefore, the current i _D is adjusted depending on the peak level of the harmonic current i _LR with respect to the level of the DC reactor current i _D , and the compensation current is adjusted to match the change in the peak value of the harmonic current i _LR . Current i _D is controlled to supply I ₀ , and in steady state the peak value of i _LR is i _D
, and the signal S _D becomes zero. Also, the multiplier 12
The multiplication by the semiconductor element 6 is performed according to the power supply voltage phase.
This is for controlling on/off of a and 6b. Here, by passing the filter 12A, the power supply 1
Extracting the fundamental wave component removes harmonic components and prevents unnecessary harmonic components from being generated on the power supply 1 side for controlling the current _iD . On this point, Tokukai Akira
55-139031 uses a square wave with rising and falling points at the zero crossing point as a signal that matches the power supply voltage phase, and multiplies this in the multiplier 14, so the signal S _D is a signal containing harmonic components. This causes unnecessary harmonic components to be generated on the power supply 1 side.

Therefore, according to the present invention, the DC current _iD is changed according to the harmonic component _iLR of the load current _iL , and
Since the compensation signal is obtained by dividing i _LR by i _D , the ratio of the harmonic component i _LR to the DC current i _D is constant, and a compensation current that follows the harmonic current change of the load is supplied, that is, the power loss of the device is reduced. It is possible to increase the efficiency by keeping the modulation rate constant and eliminate unnecessary harmonic generation. In addition, since the signal S _D for flowing DC is obtained through a bandpass filter that passes only the fundamental wave component of power supply 1, it is possible to prevent harmonic current from being generated in the power supply by flowing DC current i _D. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the waveform compensation device of the present invention, FIG. 2 is a waveform diagram of each part of the embodiment,
FIG. 3 is a filter circuit diagram of the embodiment, and FIG. 4 is a circuit diagram showing an example of a rectifier circuit load. 2...Load, 4...Filter, 7...DC reactor, 8, 9...Current detector, 10...Bundle reject filter, 11...Set value determination circuit,
12... Multiplier, 13... Divider, 14... Comparator, 15... Triangular wave generator, 16... Logic circuit, 17... Gate circuit.

Claims (1)

[Claims] 1 In a waveform compensation device that supplies a compensation current for improving the power supply waveform from a power converter having an active element connected in parallel to the load in a system that supplies power from a power source to a load, the current of the load is a band reject filter that detects harmonic current from the filter, a set value determination circuit that sets the DC current of the power converter from the output of this filter, and a set value of the set value determination circuit and the detected DC of the power converter. A multiplier that extracts the difference from the current with a signal synchronized with the power supply, a bandpass filter that extracts only the fundamental frequency component of the power supply from the output of this multiplier, and a DC current between the output of the band reject filter and the power converter. A divider that calculates the ratio to the detected value, and a pulse width signal proportional to the added value is obtained by comparing the added value of the calculated value of this divider and the output of the band pass filter with a triangular wave synchronized with the power supply. A waveform compensation device comprising: a comparator; and a gate circuit that converts the output pulse signal of the comparator into an on/off control signal for an active element of the power converter.