JPH0488571A - Picture processor - Google Patents

Abstract

PURPOSE:To enable various picture processings by using compressed data by extending stored compressed data, converting the one part corresponding to command data and detecting the amount of picture data compressed again. CONSTITUTION:A PDL interpreter (PDLP) 2 reads out the data of a block raster including a picture part to be changed by a PDL command from a compression memory (CM) 5, a decodes the data and simultaneously outputs the decoded data to a synthesizer 3. The PDLP 2 controls the synthesizer 3, and the decoded data is inputted and stored in a buffer. The PDLP 2 overwrites new data to be generated by a command in the relevant area of the block raster completely fetching the decoded data. Afterwards, the relevant block raster area is compressed again, and the data is stored in the relevant position of the CM 5 again. When all the data can not be completely stored in the area for block raster of the CM 5, an empty buffer area managing circuit 9 calculates the position of the area for block raster of the CM 5 to continuously store the remaining data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device that performs image compression processing on image data.

[Conventional technology]

Image recording devices, such as thermal printers and inkjet printers. Laser beam printers have conventionally mainly been used as recording terminals, i.e., white/white printers with a human map memory.
It was used as a black printer. However, in recent years, with the increase in the capacity of semiconductor memories, the development of high-performance LSIs, and advances in computer technology, the use of full-color images for high-definition recording is increasing.

On the other hand, there is an increasing demand for capturing color natural image data into a computer and performing various types of processing and communication. One of the encoding methods for this purpose is a variable length encoding method called the ADCT method, which is published in the Journal of the Institute of Image Electronics Engineers V o 1.
, 18 Na 6 pp 398-407.

When this ADCT method is used as the image memory of the above-mentioned image recording device, full-color natural images can be produced 1/10 to 1/20 times as much as normal original data (uncompressed data).
This is extremely beneficial as it only requires a memory capacity of 1,000 yen, making it possible to significantly reduce the overall cost of the recording device.

On the other hand, when used as a recording device connected to a computer, it is common to use a standardized page description language (PDL) to ensure data compatibility between different recording devices. This is intended to make printers or computers of different specifications from different companies compatible through a common language, and to eliminate the disadvantage that only specific computers and specific printers can be connected. Examples of such a description language include Po5t 5script.

[Problem that the invention is trying to solve]

When such a PDL is used on the compressed memory mentioned above, the PDL itself is created with the concept of override (that is, the concept of overwriting new data on old underlying data), There are problems with the following points.

1) The block in which images are combined within the 8×8 block of ADCT needs to be updated with new code data.

2) If the compression method is a variable length encoding number and you try to overlap another image data on a certain part of the base image, the address for overlapping is not constant.

3) The total code length of the combined new image data changes depending on the image quality.

It was thought that it would be difficult to use PDL on compressed memory from now on.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an image processing device that can eliminate the above drawbacks and perform various image processing using compressed data.

[Means and operations for solving the problems] In order to solve the above problems, the image processing device of the present invention includes means for storing compressed image data, and a part of the compressed image data stored in the storage means. processing means for decompressing, replacing at least part of the decompressed image data with image data converted according to command data from the host, and compressing again;
The image processing apparatus is characterized by comprising a detection means for detecting the amount of image data compressed by the processing means.

〔Example〕

FIG. 1(a) is a drawing that best represents the features of the present invention. In the figure, 1 is a host computer that outputs a command string in the PDL language, and 2 is a drawing that outputs a command string output from the host computer 1. An interpreter (hereinafter referred to as a PDL interpreter) that receives, interprets, and executes the data; 3 is a synthesizer that combines the underlying data with the image data newly generated by the PDL interpreter 2; 4 is a compressor that performs compression by ADCT; 5 6 is a decoder, and 7 is the output of the decoder 6 to be outputted to the synthesizer 3 or to an image forming section of a recording device (not shown). This is a multiplexer that switches the output. 8 is a compressed memory address controller that controls reading and writing of compressed data. Reference numeral 9 denotes an empty buffer area management circuit used by the address controller 8 to manage empty areas within the compressed memory 5.

When receiving a postscript PDL command from the host computer 1, the PDL interpreter 2 determines the image part to be changed by the command, sequentially reads block rask data including the relevant part from the compression memory 5, and decodes and outputs it. Address controllers 8 and 6 control the decoders. At the same time, the multiplexer 7 is controlled to output the data decoded by the decoder 6 to the synthesizer 3. P
The DL interpreter 2 also controls the synthesizer 3, inputs decoded data from the decoder 6, and sets it to be stored in a buffer. The PDL interpreter 2 overwrites the area corresponding to the pixel position of the block rask for which the decoded data has been taken in with new data generated by the above-mentioned command. After writing the data corresponding to the block rask area, the block rask area is again compressed by the compressor 4 and stored in the compression memory 5.
The synthesizer 3, compressor 4, and address controller 8 are controlled so that the data is stored in the corresponding position again. The above procedure is repeated over all necessary block rusks.

FIG. 1(b) is a diagram showing the configuration of the entire system including the interface section shown in FIG. 1(a) above, where 1 is a host computer, 101 is an interface section shown in FIG. 1(a), and 102 is an output. an output controller that controls signals, 103 a display that displays output images;
4 is a transmitting device for transmitting an output image through a public line or local area network, 105 is a laser beam printer that irradiates a laser beam onto a photoreceptor to form a latent image, and forms a visible image from this latent image; This is an operation unit through which an operator sets output light and the like in order to output a desired image.

FIG. 2 shows an example of the configuration of the synthesizer shown at 3 in FIG. 1(a). 21, 22, and 23 each consist of eight raster buffers, each having a capacity to hold decoder data for a block raster. 24 is a selector, which outputs data 27 and 6 from the PDL interpreter 2.
The signal data 28 decoded by the decoder and input via the selector 7 is converted into the 8-line buffer of 21.22.23 above based on the signal 29 output by the selector controller 26 controlled by the PDL interpreter 2. They are each independently connected to different 8-line buffers. Same again <
25 is also a selector, and the aforementioned 8 line buffer 21.2
2.23 is selected and output. The selector controller 26 communicates buffer switching timing with the PDL interpreter 2. That is, when the PDL interpreter 2 issues a request signal indicating that it wants to write data to a new buffer, the selector controller 26 writes the 8-line buffer 21, 22, 23 to 21→22→23→21→... . . and connect to the signal line group 27. At the same time 22 → 23 → 21 →
Switch in the order of 22→... and connect to the signal line group 28,
Next, the PDL interpreter 2 composes and stores the data that forms the basis of the block rask to be overwritten. At the same time, the selector 25 is controlled to 23→21→22→23→・
... and transfer the data that has been overwritten from the PDL interpreter onto the underlying data to the encoder (compressor) 4.
Output to. 30 is an address controller, which controls the scanning line synchronization signal (H3YNC) from the decoder and the pixel synchronization (P
XCLK), the data output address from the PDL interpreter, the scanning line synchronization signal from the encoder, and the pixel synchronization signal are input, and the output address on the corresponding 8-line buffer of the pixel data decoded from the decoder, respectively, is input from the PDL interpreter. The selector controller 2
According to the select signal from 6, each of the 8-line buffers is output to one of three different sets of 8-line buffers.

FIG. 3 shows an example of the configuration of the address controller 30. 3
1 is a counter that counts the scanning synchronization signal (H8YNC) from the decoder, and 32 is a counter that counts the pixel synchronization signal (PXCLK) from the decoder. 32
31 outputs the count as the address corresponding to the position in the main scanning direction within one scanning line, 31 outputs the count as the upper bit of the address of the first pixel of each scanning line in one raster block, By using the output as the upper bit and using the output of 32 as an address signal line for the subsequent lower bit, a storage address for the output data from the decoder on the 8-line buffer is generated. Also, counter 3
2 is reset by a scanning synchronization signal (HSYNC). Similarly, 33 and 34 receive the synchronization signal from the encoder. Counter 33 counts the scanning synchronization signal (HSYN, C) from the encoder, counter 34 counts the pixel synchronization signal (PXCLK) from the encoder,
．． Similarly to 32, the storage address on the corresponding 8-line buffer of the data to be output to the encoder is generated. Selectors 35, 36, and 37 select 8-line buffers 21, 22, and 2 to store the data decoded from the decoder, respectively.
Selector 21.22.3 is selected from among 3 by the select signal from the selector controller 26 to output the address generated by the counter 31.32, and the 8-line buffer to output the data held to the encoder.
Selector 23 is selected from among 23 by the select signal from the selector controller 26 and holds the base data to be overwritten with the address signal output from the selector and PDL interpreter that outputs the address generated by the counter 33 and 34. 8 line batshua 21.22
．． This is a selector that selects and outputs one of 23 in response to a select signal from a selector controller 26.

In this way, the data overwritten on the underlying data is rewritten as 4.
is transferred to the encoder and compressed. The compressed data is output from the encoder 4 to the compression memory 5 and stored therein.

FIG. 4 shows the storage location of compressed data corresponding to each block raster on the compression memory. For example up to 40
96x4096 pixels, 1 pixel 3 bytes (1 byte/color)
We will be dealing with an image consisting of . This maximum image is 48M
It has a capacity of Byte. Assume that the compression ratio by the encoder 4 is set to 1/12. The block raster is compressed so that each block is composed of 8×8 pixels. Therefore, the maximum size image is composed of 512×512 blocks. The maximum size image is approximately 4MBy
The data is compressed to a capacity of te, and the average code length for each block rask is 8 KB.

In this embodiment, the data amount of the average code length is assumed as the memory capacity for each block raster, and the compressed memory area for each block raster is set for each 8 KB as shown in FIG.

The fifth section expresses the state of the data actually held in the compressed memory shown in FIG. Each block in FIG. 5 is the same as the data area of each block raster in FIG. 4, and it is clearly expressed that the compressed memory area for each block raster is set for each average code length. The shaded area indicates the area that actually stores the code for each block raster. In FIG. 5, the 2nd block class, the 4th block class, the 7th block class, the 10th block class, etc. of the original image are shown.
- Regarding the 506th block class and 510th block class, the code amount is longer than the average code length,
The data cannot be stored in one block raster compression memory area set for each data amount of average code length, but is stored using a plurality of areas. In particular, regarding the seventh block class, it cannot be stored even if the second area is used, so three areas are used to store it.

FIG. 6 shows the configuration of the address controller and empty buffer area management circuit 9 shown in the address controller 8 of FIG. Reference numeral 61 denotes a counter for counting block raster synchronization signals, and indicates by a count value whether the area of the second block raster in the compressed memory is to be accessed. The value corresponding to the block address rewritten by the PDL interpreter 62 is set as the initial value of the counter 61 via the signal line 62, and the block raster synchronization signal 63 from the encoder 4 is counted. 64 is a counter for counting transfer locks of block data, which counts transfer locks 65 for each byte from the encoder 4, and the count value indicates in which position in the block raster data the block data is stored. . 64 is reset by the block raster synchronization signal of the encoder. Further, when the data cannot be stored in the memory area for the block rask in the compressed memory, the counter 64 generates a count up (carry) signal 76 and resets itself. In this case, the empty buffer area management circuit shown in FIG. 1(a) 9 is activated by the count-up signal 76 to obtain the location of the block rask memory area on the compression memory where the remaining data is to be subsequently stored. 66
61 is a counter that counts synchronization signals of the block raster, and the first block raster number in the block raster including the pixel position to be overwritten by the PDL interpreter 62 is initially counted and set, and thereafter Count the block raster synchronization signal 67,
The count value indicates which block rusk area in the compressed memory is to be accessed. Like 64, 68 is a counter for counting data transfer locks, which counts transfer locks for each byte from the decoder, and the count value indicates which position in the block raster data is to be read. 68 is reset by the raster synchronization signal of the decoder. Further, even if the data is read out all at once in the memory area for the block raster in the compressed memory, if the data of the block raster is not all read out, the 68 generates a count up (carry) signal 73 and outputs a count up (carry) signal 73. Reset yourself. In this case, the empty buffer management circuit shown in FIG. 1 is activated by the count-up signal 73 to obtain the location of the block rask memory area on the compressed memory from which the remaining data is to be subsequently read. When activated by the count-up (carry) signal 76 from the counter 64 that counts block data transfer locks, the free buffer area management circuit 9 stores the expansion block raster memory area in the image memory of the block raster being written. outputs the address to the signal line 80. At the same time, the selection switching signal 74 of the selector 78 and the latch 79
A latch timing signal 75 is output. The expansion area block raster memory location outputted to the signal line 8° is selected and outputted by the selector 78 at the timing according to the signal 74.
It is held in the latch 79 by the timing of the signal line 75,
It is used as the upper address of the storage address of subsequent image data. Similarly, when the free buffer management circuit 9 is activated by a count-up (carry) signal 73 from the counter 68 that counts clock data transfer locks, the block raster memory for expansion in the image memory of the block raster being read is activated. The address of the area is output to the signal line 81. At the same time, a selection switching signal 87 for the selector 83 and a latch timing signal 88 for the latch 84 are output. The expansion area block raster memory location output to the signal line 81 is determined by the selector 8 at the timing according to the signal 87.
3 is selectively output, and the latch 8 is output at the timing of the signal line 88.
4, and is used as the upper address of the read address for subsequent image data.

FIG. 7 shows a detailed configuration of the image memory empty buffer area management circuit 9. The buffer read/write control circuit 90 uses the signal 76
When input, the signal 102 is output to the flag buffer 91. The flag buffer 91 is a buffer corresponding to the number of extended free area block rasters as shown in FIG. 8, and is composed of 512 cells each consisting of 1 bit. Each cell corresponds to the 0th expansion (block raster) area to the 511th expansion (block raster) area of the image memory shown in FIG. 4, and "1" indicates that the corresponding expansion area is a free area. , and "0" indicates that it is a medium area for several flights. Buffer 91 receives signal 1
02, each of the 512 bits of information held is
It outputs to a signal 98 consisting of 8-0 to 98-511. The sorter 92 receives the input signal 98 and outputs signals 98-0 to 98-5.
This is a 512-output circuit that selects the signal line with the lowest order among the 11 signal lines that are "1" and outputs only the signal in that order as "1" and the others as "0". An example of the configuration of the sorter 92 is shown in FIG.

The output signal 99 of the sorter 92 is encoded by the encoder 93 into a 9-bit binary number according to the order of the "1" signal lines, and is output as a 9-bit signal 8o. A signal 80 outputted by the encoder 93 indicates the position of the extension area in binary representation, and is taken into an extension block address buffer 94. The buffer table 94 is configured as a table as shown in FIG. 11, and receives the block address before expansion input by the signal 86 from the signal 101 as the access position of the buffer table 94 from 90, and stores the contents of the signal 80 at the corresponding position. It incorporates the following.

When the buffer read/write control circuit 90 receives the signal 73, it inputs the block number currently being read as the signal 82, and outputs the block number as the signal 101 to the extended block address buffer 94. The extended block address buffer 98 outputs the contents of the position specified by the signal 101 to the signal line 81.

The signal line 81 outputs the number of the block raster buffer in which the data subsequent to the block rask being read, which is input as the signal 82, is stored. This signal 81 is also output to the decoder 96 at the same time. The decoder 96 sends a signal 81 expressed as a 9-bit binary number to 512 signal lines 100, setting only the signals in the order of the numbers representing the 9-bit binary number as "1", and setting the other signals as "0". signal 100
Output as ~0~100-511. The flag buffer update circuit of 95 outputs the signal 98.99.100,
The flag for the location of the extended block used for writing is “O”.
”, and the flag for the position of the extended block to be read is “
This is to update the usage status of the empty buffer area of the image memory, the details of which are shown in FIG.

The latch 79 and counter 64 use the output of the latch 79 as an upper address signal, and the count value of 64 as a lower address signal, which is combined and used as a write data address for the compressed memory. The upper address signal, the count value of 68, is combined as the lower address signal and used as the read data address from the compressed memory. A read/write control circuit 70 inputs the write data address, read data address, data transfer lock 65 from the encoder, and data transfer lock 69 from the decoder, and reads data from the compressed memory; It controls the write address and timing.

The encoder and decoder are, for example, CL manufactured by C-Cube, USA.
If an LSI such as 550 is used, the structure can be easily configured by adding a circuit for adjusting a synchronization signal or the like as necessary.

The division of the block rasks is controlled using a marker code, and each block rusk is independently encoded and decoded using this marker code. Regarding this marker code, please refer to the above-mentioned literature (
It is explained in the Journal of the Institute of Image Electronics Engineers).

[Embodiment 2] In the embodiment described above, when the PDL interpreter 2 receives a PDL command from the host computer 1, it sequentially determines the part of the image that will be changed by the command, and decodes, rewrites, and rewrites the corresponding part. (For example, as shown in FIG. 12, PDL commands and data received from the host computer 1 using the image buffer 71 and command buffer 72 are It is temporarily stored in a buffer, and the parts changed by each command are determined for each command, and the same block rask is rewritten at once.In other words, decoding → the block rask It is also possible to perform all rewriting related to the data, such as executing all operations → re-encoding.

In this way, by temporarily holding a number of commands in the buffer and processing them for each set of commands, it is possible to reduce the number of times of decoding and re-encoding, and the degree of deterioration in image quality associated with it can be reduced. give birth to It also has the effect of reducing the waiting time caused by command execution for the host computer 1.

As described above, according to the above-mentioned embodiments of the present invention, the compressed memory is divided into fixed-length blocks having a capacity approximately equal to the average code length of a block taser, and the blocks are reproduced and modified in units of blocks. , performs re-encoding. During encoding,
A means for detecting whether the code length exceeds the fixed block length and a means for managing free fixed blocks in the compressed memory are provided, and the code of the block rask whose code length exceeds the fixed block length is provided. , data is held across multiple fixed-length blocks.

This facilitates the use of PDL on compressed memory.

That is, by editing image data using a compressed memory, there is the effect of significantly reducing costs compared to the case where a memory with a data capacity sufficient to hold the actual data is used.

In addition, it is divided into fixed-length blocks with a capacity approximately equal to the average code length of the block rask, and is reproduced, changed, and re-encoded in units of block rusks, and when encoding, the code length exceeding the fixed block length is used. A means for detecting whether or not the length of the block has exceeded the fixed length block and a means for managing free fixed length blocks in the compressed memory are provided. This has the effect of making it easier to edit images using a compression method that uses a variable length code format.

In the above-mentioned embodiment, PS (Postscript) was used as an example of the PDL, but it goes without saying that other PDLs may be used.

Furthermore, the compression format is not limited to ADCT, and may be other orthogonal transform encoding, predictive encoding, run-length encoding, or the like.

Furthermore, editing is not limited to overwriting, but may also include calculations (for example, multiplication, AND, OR, etc.) using previous data and subsequent data. That is, processing such as overlay and modulation can also be performed.

Further, the decoded output signal can be displayed on a display means or the like, or can be hard-copied using a laser beam printer, an inkjet printer, a thermal transfer printer, or the like.

〔Effect of the invention〕

As described above, according to the present invention, various image processing can be performed using compressed data.

[Brief explanation of drawings]

Fig. 1 is a diagram that best represents the features of the present invention, Fig. 2 is a block diagram of the synthesizer, Fig. 3 is a block diagram of the address controller in the synthesizer, and Fig. 4 is a block diagram of each block rask on the compressed memory. A diagram showing the corresponding data area, Figure 5 is a diagram showing the state of data held on the compressed memory, Figure 6 is a configuration diagram of the address controller of the compressed memory, and Figure 7 is a diagram of the empty buffer area management circuit. Fig. 8 is a block diagram of the flag buffer, Fig. 9 is a block diagram of a sorter, Fig. 10 is a block diagram of a flag buffer update circuit, Fig. 11 is a block diagram of an extended block address buffer, and Fig. 12 is a block diagram of a flag buffer. It is a figure showing a 2nd example. 1... Host computer 2... PDL interpreter 3... Synthesizer 4... Encoder 5... Compression memory 6... Decoder 7... Selector 8... Compressed memory address controller 9...Empty buffer area management circuit

Claims (5)

[Claims] (1) means for storing compressed image data, decompressing a portion of the compressed image data stored in the storage means, and converting at least a portion of the decompressed image data in accordance with command data from the host; Replace it with the image data that was
An image processing apparatus comprising: processing means for re-compressing; and detection means for detecting the amount of image data compressed by the processing means. (2) The image processing apparatus according to claim 1, wherein the compressed image data is image data compressed in a variable length in units of blocks each consisting of a plurality of pixels. (3) The image processing apparatus according to claim 1, wherein a part of the compressed image data is compressed image data corresponding to a predetermined area larger than a unit block to be compressed. (4) The processing means is a means for performing decompression, editing processing, and recompression for each predetermined region, and includes a decompressor that decompresses the compressed image data of the predetermined region; means for holding image data; means for overwriting the other image data on the data holding means; a compressor for recompressing the data held in the buffer; the holding means, the compressor, and the compression memory. , and control means for controlling the flow of data between the decoders. (5) When the amount of image data detected by the detection means exceeds a predetermined amount, a memory area for storing the image data is changed.
The image processing device described in section 1).