JPH0485174U - - Google Patents
Info
- Publication number
- JPH0485174U JPH0485174U JP12684890U JP12684890U JPH0485174U JP H0485174 U JPH0485174 U JP H0485174U JP 12684890 U JP12684890 U JP 12684890U JP 12684890 U JP12684890 U JP 12684890U JP H0485174 U JPH0485174 U JP H0485174U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- comparator
- offset voltage
- offset
- memory circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Manipulation Of Pulses (AREA)
- Measurement Of Current Or Voltage (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12684890U JPH0485174U (enExample) | 1990-11-28 | 1990-11-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12684890U JPH0485174U (enExample) | 1990-11-28 | 1990-11-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0485174U true JPH0485174U (enExample) | 1992-07-23 |
Family
ID=31874376
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12684890U Pending JPH0485174U (enExample) | 1990-11-28 | 1990-11-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0485174U (enExample) |
-
1990
- 1990-11-28 JP JP12684890U patent/JPH0485174U/ja active Pending