JPH0484455A - Booster circuit - Google Patents

Abstract

PURPOSE:To obtain a sufficiently higher level of boosting potential by biasing sufficiently the gate source of a second MOS transistor for electric charge transfer during boosting operation with reverse phase clocks. CONSTITUTION:When a precharge signal phiP is under an initial state of 'L', power source potential Vcc is precharged to a second node 2 where a boosting circuit fails to drive a charge pump. When the precharge signal phiP is in a level of 'H', a MOS transistor T3 turns off. When a trigger signal phiT is in a level of 'H', a ring oscillator begins its oscillating motion, thereby providing reverse phase clocks phiA and phiB respectively. While the clock phiA remains in a level of 'L', a first node A is charged from the potential VM to a potential lower by the threshold voltage of the MOS transistor T. When the it turns to the H level, the charge of the first node A is transferred to a second node B.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Field of Industrial Application) The present invention relates to a booster circuit formed in a semiconductor integrated circuit such as a dynamic RAM (DRAM).

(Prior Art) In a DRAM, a word line booster circuit is used that provides a selected word line with a potential boosted higher than the power supply potential. This is to prevent a threshold voltage drop in the transfer gate MO5 transistor of the memory cell driven by the word line.

FIG. 6 shows a conventionally used booster circuit, and FIG. 7 shows its operation timing diagram. The capacitor Cs is for holding the boosted potential. A p-channel MOS transistor T3 is connected to the node B of this capacitor Cs, and the p-channel MOS transistor T3 precharges the power supply potential Vce. Node B has a diode-connected n-channel MO
S transistor T2 and capacitor CA are connected. These MOS transistor T2 and Ushiyabashita CA are
It constitutes a charge pump circuit, and a tarlock φA is applied to the terminal of the capacitor CA during boosting operation. M.O.
A connection node A between the S transistor T2 and the capacitor CA is provided with an n-channel MOS transistor Tl for charging a potential vM higher than the power supply potential vCC.

The operation of this booster circuit will be explained with reference to FIG. 7 as follows. In the initial state, the precharge signal φ is “L”
# level (-VSS) and node B to be boosted is precharged to power supply potential VCC by p channel MOS transistor T3. Precharge signal φ
, reaches the "H" level and inputs the clock signal φ9 generated by a ring oscillator etc., the boosting operation starts. That is, while the clock signal φ6 is at the "L" level, the capacitor CA is charged via the MOS transistor Tl. When the tarokku φ4 becomes "H level", the capacitor CA
The charged charge is transferred to node B via MOS transistor T2.
and distributed to capacitor C5. The above charge pump operation is repeated, and the potential of node B becomes Vc
It gradually rises from e. When the potential of node B increases,
This is fed back to the gate of MOS transistor T1.

As a result, the gate bias of the MOS transistor T1 gradually increases, and eventually the node A is charged to approximately the potential VM when the clock φ4 is at the "L" level. To,
A potential VM-α boosted to a value close to the potential VM is obtained.

In this conventional booster circuit, the VM of the boosted potential obtained is
The drop α from the charge transfer MOS transistor T
2 threshold voltage. This MOS transistor T2
The threshold voltage of becomes gradually higher as the potential of node B rises. This is because a positive increase in the potential of node B, that is, a positive increase in the source potential of MOS transistor T2, is equivalent to applying a negative substrate bias to MOS transistor T2. As a result, the drop α of the obtained boosted potential from vM becomes larger than the design value,
Desired boosted potential cannot be obtained.

(Problems to be Solved by the Invention) As described above, the conventional booster circuit has a problem in that a desired boosted potential cannot be obtained due to the substrate bias effect of the MO8 charge transfer transistor.

The present invention has been made in view of these points, and an object of the present invention is to provide a booster circuit that is not affected by the threshold voltage drop of the MO8 charge transfer transistor and is capable of obtaining a sufficiently high boosted potential. purpose.

[Structure of the Invention] (Means for Solving the Problems) A booster circuit according to the present invention includes a first node to which the gate and drain of a MOS transistor for charge transfer are connected, and a first node to which the source is connected. The 1st and 20th nodes respectively. A second capacitor is provided, and these capacitors are configured to be driven by clocks having opposite phases to each other.

That is, in the booster circuit according to the present invention, the drain is given a potential set to a predetermined value higher than the power supply potential, the source is connected to the first node for transferring charge, and the gate is connected to the second node to be boosted. a first MOS transistor for boosting voltage connected to the node; a second MOS transistor for charge transfer having a gate and a drain connected to the first node and a source connected to the second node; a first capacitor having one end connected to the first node and a first clock input to the other end; a second capacitor to which a second clock of the above is input; and a third MOS transistor having a source connected to the second node to precharge the second node to the power supply potential. It is characterized by

(Function) According to the present invention, during boost operation, the second MO for charge transfer
The gate and source of the S transistor are sufficiently biased by clocks having opposite phases. Therefore, due to the increase in the potential of the second node to be boosted, the second MOS
Even if the threshold voltage of the transistor increases due to the substrate bias effect of the transistor, charge transfer is performed efficiently without being affected by this. In other words, the second node is not clamped by the threshold voltage of the second MOS transistor for charge transfer, and obtains a potential that is boosted to the set potential applied to the drain of the first MOS transistor for boosting. I can do it.

(Example) The present invention will be explained in detail below.

FIG. 1 shows the main part configuration of a booster circuit according to an embodiment. E-type, n-channel boost MO5 transistor (first M
The source of the OS transistor Tl is connected to the first node A, and the potential VM set to a higher value than the power supply potential VCC is applied to the drain. The source of this boosting MO8 transistor T1 is connected to the first node A for charge transfer, and the gate is connected to the second node B to be boosted. The second node B is provided with a capacitor C3 for holding the boosted potential. Between the first node A and the second node B, an E-type, n-channel charge transfer MOS transistor (second MOS transistor) T2 is provided in a diode-connected manner. One end of a first capacitor CA is connected to the first node A, and one end of a second capacitor CB is connected to the second node B. These first. At the other ends of the second carrier (shifter CA, CB) are clocks φ having different phases.
4. φB is applied.

The second node B is provided with an E-type, n-channel precharging MO8I-transistor (third MOS transistor) T3 driven by a precharge signal φ. A power supply potential vce is applied to the drain of this preliminary charging MOS transistor T3.

FIG. 2 shows clocks φ9.0, which are opposite in phase to each other and drive the booster circuit shown in FIG. This is a circuit that generates φ3.

In this circuit, a delay circuit element consisting of an inverter ll-I4 and capacitors 01 to C4 provided at each output terminal is connected in cascade, and these are connected in a ring shape via a gate G to form a ring oscillator 1. There is. A trigger signal φ7 is applied to one input terminal of the gate G via an inverter ■5, and the trigger signal φ7
The ring oscillator 1 oscillates when the level is “H”.The output terminal of the ring oscillator 1 is connected to three stages of inverter buffers 16 to
8 are connected, and clocks φ9. φB is obtained.

FIG. 3 shows a specific example in which the circuit shown in FIG. 2 is implemented using a CMO3 configuration.

The operation of the booster circuit configured as described above will be explained below using the timing chart shown in FIG. Precharge signal φ
, in the initial state of "L level", the power supply potential Vcc is applied to the second node B via the pre-charging MOS transistor T3.
is pre-charged. At this time, the clock φ7 is at "L level" (-VSS), the ring oscillator 1 does not oscillate, and therefore the booster circuit does not operate as a charge pump.

When the precharge signal φ reaches the "H" level -Vcc), the precharge MOS transistor T3 is turned off. Then, the trigger signal φT changes from “L” level to “H” level.
When the level is reached, ring oscillator 1 begins to oscillate.

As a result, clocks φ and φB having mutually opposite phases are obtained. While the clock φ is at “L” level, the first node A is set to the potential VM by the boosting MO8 transistor Tl.
is charged to a potential lower by the threshold voltage of the MOS transistor T. When clock φ9 goes to “H#” level,
The charge at the first node A is transferred to the second node B via the charge transfer MOS transistor T2.

This charging and transfer operation is repeated until the second node B
gradually increases.

In the above boosting operation, during charge transfer, when the clock φ9 is at the "H" level, the clock φ8 becomes the "L" level, so the second node B is forcibly pulled down by capacitive coupling. As a result, the first The potential difference between the node A and the second node B, that is, the gate-source voltage of the charge transfer MO5 transistor T2 increases.As a result, the charge at the first node A is efficiently transferred to the second node B. In other words, the charge transfer MOS transistor T
The 20th node B is boosted to the potential vM applied to the drain of the charging MO5 transistor T1 without being affected by the threshold voltage of 2.

As described above, the booster circuit of this embodiment is not affected by the threshold voltage of the charge transfer MOS transistor.
Therefore, even if the threshold voltage of the MO5 charge transfer transistor increases due to the substrate bias effect, a sufficient boosted potential can be obtained without any problem.

FIG. 5 shows the first part of the booster circuit shown in FIG. A case is shown in which the second capacitors CA and CB are formed by n-channel MOS transistors. Especially capacitor C
A and CB are enhancement (E) type n-channel MOs.
When configured with three transistors, a situation where node B is inadvertently boosted when node B is not precharged can be prevented. This is because an inversion layer is not formed in the E-type n-channel MOS transistor when the gate voltage is oV, and the capacitors CA and CB do not function as capacitors.

In the embodiment, the boosting MOS transistor Tl.

Although we did not explain the specific threshold voltage of the charge transfer MOS transistor T2, etc., the charge transfer MOS transistor T2 etc.
The threshold voltage of the transistor T2 may be set to be lower than that of the boosting MOS transistor T1, for example, to about Ov. This makes the charge transfer operation more efficient and
This is effective in quickly obtaining a boosted potential.

In addition, the present invention can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, MO5I for charge transfer
- It is possible to provide a booster circuit that can obtain a sufficient boosted potential without being affected by the threshold voltage of a transistor.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the main part configuration of a booster circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a ring oscillator that drives the booster circuit, and FIG. 3 is a specific example of the configuration of the ring oscillator. 4 is a timing diagram for explaining the operation of the booster circuit, FIG. 5 is a diagram showing the configuration of a booster circuit of another embodiment, FIG. 6 is a diagram showing a conventional booster circuit, FIG. 7 is a timing diagram for explaining the operation. T1... MOS transistor for boosting (first MOS transistor), T2... MOS transistor for charge transfer (
second Mos transistor), T3...M for preliminary charging
OS transistor (third MOS transistor), A.
...First node, B...Second node, CA...
First capacitor, CB...Second capacitor, cs
・Capacitor for holding boosted potential. Applicant's agent Patent attorney Takehiko Suzue

Claims (2)

[Claims] (1) A booster in which the drain is given a potential set to a predetermined value higher than the power supply potential, the source is connected to the first node for transferring charge, and the gate is connected to the second node to be boosted. a second MOS transistor for charge transfer whose gate and drain are connected to the first node and whose source is connected to the second node; a first capacitor connected to the node and having the other end inputted with a first clock, and one end connected to the second capacitor;
a second capacitor connected to the node and having the other end inputted with a second clock having a phase opposite to the first clock; A booster circuit comprising: a third MOS transistor for pre-charging the battery; (2) The first MOS transistor and the second MO
The S transistor is an n-channel, and the third MOS
2. The booster circuit according to claim 1, wherein the transistor is a p-channel transistor.