JPH0483421A - Complementary semiconductor device - Google Patents

Abstract

PURPOSE:To suppress power consumption by inserting a voltage amplitude restricting MOSFET in addition to two MOSFETs and inserting a resistance means into a current route connecting between power sources. CONSTITUTION:One conductive electrode of a 3rd semiconductor transistor(TR) 5 is connected to an output terminal 1 and a control electrode is connected to a constant voltage source 4. A 1st resistance means 16 is connected between the drain electrode of a 1st semiconductor TR 6 and the other conductive electrode of the TR 5. On the other hand, a 2nd resistance means 17 is connected between the drain electrode of a 2nd conductive semiconductor 7 and the other conductive electrode of the TR 5. Since the p-channel side resistance means 16 and the n-channel side resistance means 17 are inserted in series into a route in which a through current is allowed to flow, the through current is suppressed to a small value. Consequently, a high speed and low power consumption can be attained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides C-Mo5s! The present invention relates to a method for forming an output terminal circuit for outputting an electrical signal from a complementary semiconductor device represented by the above semiconductor device.

[Conventional technology]

Currently, C-MO3 type semiconductor devices are manufactured by many semiconductor manufacturers and are widely used in various industrial fields. The reason for this is that C-MO3 type semiconductor devices have been highly praised by users for their many inherent advantages, such as low power consumption, large noise margin, high input impedance, and high degree of integration. be.

In recent years, as semiconductor devices have become more highly integrated, the number of integrated circuits and input/output terminals has tended to increase. However, it has been found that there is a limit to the power that a package can allow, and therefore even for a C-MOS type, there are cases where the degree of integration and operating frequency are limited by the allowable power consumption. Therefore, even in C-MO3 type semiconductor devices, there has been a demand to further reduce power consumption per unit circuit.

FIG. 3 shows an example in which an output circuit of a C-MO3 type semiconductor device is formed using a conventional technique. This circuit type is a standard circuit in C-MO3 type semiconductor devices that are currently widely used. In the figure, the resistor means 19 is necessary to suppress electrostatic damage and latch-up phenomena in semiconductor devices. . That is, the 1-resistance means 19 increases the impedance of the output terminal, attenuates the electrostatic discharge energy from the outside, and also serves to make it difficult for current to flow, which may cause latch-up.

A thin film of polycrystalline silicon is mainly used as the resistance means, and its value is usually in the range of 5 to 50 ohms.

When a user uses semiconductor devices to build a system horizontally, it is currently mainstream to interface at the TTL level. Specifically, the voltage levels are generally 5V for the power supply voltage, 2.4V for the logic high level, and 0.4V for the logic low level.

As shown in FIG. 3, the output voltage level of a conventional C-MO3 type semiconductor device is normally 5■ for a logic high level side output and 0■ for a logic low level output.

Therefore, even if it is a C-M 03 type semiconductor device, TTL
It is possible to perform a level interface.

[Problem to be solved by the invention]

As mentioned above, even in the conventional C-MO3 type semiconductor device, TT
Although it is possible to interface at the L level, on the high level side, a voltage amplitude larger than that required for the TTL level is output. A voltage amplitude that is larger than necessary requires extra energy and response time for state transition, and thus becomes an obstacle to increasing the speed and reducing power consumption of semiconductor devices. Further, a part of the extra energy consumed becomes electromagnetic waves and is radiated, which may adversely affect other electronic devices.

In addition, in the circuit shown in FIG. 3, when the voltage level of the output terminal 1 changes, both the P-channel side output MO3FET 6 and the N-channel side output MO3FET 7 become conductive,
It is known that a transient current called an inter-power supply through current flows between the power supply terminal 2 and the ground terminal 3. In particular, if the load driving ability of the output MO3FETs 6 and 7 is inappropriate for the load capacity of the output terminal 1, the time required for the level to change will be extended, resulting in an increase in transient current.

Although it is theoretically possible to design a semiconductor device by accurately estimating the load capacity, it lacks versatility because the environment in which it will be used is limited, and it has not been fundamentally solved. MO8FET and N-channel side MO3
The reason why both FETs are momentarily conductive is C-MO.
This is a characteristic of Type 3 semiconductor devices, and is said to be difficult to completely avoid.

In order to keep power consumption low, it is necessary to reduce the through current between the power supplies in the output MO3FET, which accounts for a large portion of the current consumption, and to prevent an unnecessarily large voltage Wt width from being generated.

Furthermore, when the output voltage levels of multiple output terminals change simultaneously, the current flowing through the voltage and the charging/discharging current for the load capacitance cause large voltage fluctuations on the power supply line, which may affect the operating characteristics. It has been reported that this can lead to fluctuations in the operating temperature, and in severe cases, even malfunctions.

The present invention solves the problems of the prior art, and optimizes the output voltage amplitude by adding a minimum number of elements, and effectively reduces the current between the power supplies *4m in the output MO3FET. , thereby C-MO5
What is the response speed of type semiconductor devices? The purpose is to improve CI cost electricity.

[Means to solve the problem]

The complementary semiconductor 1i1i of the present invention includes a first semiconductor having a first conductivity, a transistor, and a second semiconductor having a second conductivity, which is a conductivity type opposite to the first conductivity type. In a complementary semiconductor device including a transistor, a third semiconductor transistor, and an output terminal for outputting an electric signal from the semiconductor device, the third semiconductor transistor has one conductive electrode connected to the output terminal, A control electrode is connected to a constant voltage source, and a first resistance means is provided between the drain electrode of the first semiconductor transistor having the first conductivity and the other conductive electrode of the third semiconductor transistor. and a second resistance means is provided between the drain electrode of the second semiconductor transistor having the second conductivity and the other conductive electrode of the third semiconductor transistor.

〔Example〕

Hereinafter, the present invention will be described in detail based on Examples. 1st
The figure shows an example of an output circuit of a complementary semiconductor device implementing the present invention.

If the logic level of the enable input terminal 15 is high, the logic level of the output terminal 1 will be in a high impedance state, neither high nor low, regardless of the logic level of the data input terminal 14.

Considering the case where the logic level of the data input terminal 14 changes from low level to high level when the logic level of the enable input terminal 15 is low level, the gate voltage level of the P-channel side output MO3FET 6 changes from high level to low level. P channel side output MO3FET6
Almost at the same time, the N-channel voltage output MO3F becomes conductive.
The gate voltage level of ET7 changes from high level to low level, and N-channel output MO3FET7 becomes non-conductive. Therefore, the voltage level at the connection point between the P-channel side resistance means 16 and the N-channel side resistance means 17 changes from the ground voltage level (Ov) to the power supply voltage level (5■). However, between this junction point and output terminal 1, there is an N-channel MO3
Due to the presence of FET 5, the voltage level at output terminal 1 does not rise to the power supply voltage level. In MOSFETs with characteristics commonly used by the inventor, the voltage at the output terminal rises only to a voltage 0.7 to 1.5 V lower than the voltage at the constant voltage input terminal 4 due to an effect called back gate bias effect. Therefore, as a high level output voltage 3.
If Ov is desired, 3.7 to 4.5V may be supplied to the constant voltage input terminal 4.

Further, the gate voltage level of the P-channel side output MO5FET6 changes from high level to low level, the P-channel side output MO3FET 6 becomes conductive, and the gate voltage level of the N-channel side output MO3FET7 changes from high level to low level. Channel output MO3FET7
When becomes non-conductive, both outputs MO3F, albeit momentarily
ET becomes conductive, and a transient through current flows between the power supply terminal 2 and the ground terminal 3.

The same applies when the logic level of the data input terminal 14 changes from high level to low level while the logic level of enable input terminal 15 is low level.

However, since the P-channel side resistance means 16 and the N-channel side resistance means 17 according to the present invention are in series in the path through which the current flows, the through current can be suppressed to a smaller value than when these resistances are not provided. . In other words, these resistor means 16 and 17 have the conventional function of increasing the impedance of the output terminal, attenuating external electrostatic discharge energy, and making it difficult for the latch-up-causing current to flow. Besides the same function, x′i!
It also has the function of suppressing i-current.

For the resistance means 16 and 17, a thin film of polycrystalline silicon can be used as in the conventional case. Or output MO3F
It is also possible to extend the respective drain regions of ET6 and ET7 and use them as resistors. For a standard TTL lehele venter face, the value of the resistance means is between 5 and 50.
The implementation does not require any new technology, since the ohm range is suitable and approximately the same as previously used values.

FIG. 2 is an example of another output circuit of a complementary semiconductor device embodying the present invention. 3.5v as high level output voltage
If 4.3 V is desired, there is no need to apply a voltage using the constant voltage input terminal 4, and it is sufficient to simply supply the power supply voltage.

〔Effect of the invention〕

As described above, according to the present invention, by inserting one MOSFET for voltage amplitude limitation in addition to the two MOSFETs constituting the complementary output circuit, the voltage amplitude of the output terminal can be effectively controlled. By inserting a resistor in the path through which the current flows between the power supplies of the two MOSFETs forming the complementary output circuit, it is possible to reduce the true current in the output circuit. It is now possible to effectively reduce the amount without sacrificing versatility.

Therefore, it is possible to suppress the increase in power consumption of the semiconductor device as a whole, and it has become possible to expand the limits of integration density and operating frequency due to power consumption while suppressing the generation of harmful electromagnetic radiation. .

Furthermore, since it has the effect of reducing voltage fluctuations in the power supply line, it can also be expected to have the effect of reducing characteristic fluctuations and occurrence of malfunctions.

In particular, the invention could be of significant benefit in large scale integrated circuits having a large number of output terminals.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of an output circuit of a complementary semiconductor device embodying the present invention. FIG. 2 is a diagram showing another example of an output circuit of a complementary semiconductor device embodying the present invention. FIG. 3 is a diagram showing an example of an output circuit of a complementary semiconductor device according to the prior art. 1... Output terminal 2... Power supply terminal 3... Ground terminal 4... Constant voltage input terminal 5... N channel MO3FET 6... P channel side output MO3FET 7... N channel side output MO3FET 8 ...P channel side MO3F
ET 9 ・N-channel 67M08FET 10-P f Janel side MO3FET 11...N-channel side MO8FET 12...P-channel side MO3F" ET13...N-channel side MO3FET 14...Data input terminal 15...Enable Input terminal 16...P channel g14 resistance means 17...N channel side resistance means 18...Complementary semiconductor device 19...Resistance means Applicant: Seiko Epson Corporation

Claims (1)

[Claims] A first semiconductor transistor having a first conductivity, a second semiconductor transistor having a second conductivity that is an opposite conductivity type to the first conductivity type, and a third semiconductor transistor having a second conductivity type opposite to the first conductivity type. In a complementary semiconductor device having a semiconductor transistor and an output terminal for outputting an electric signal from the semiconductor device, a third semiconductor transistor has one conductive electrode connected to the output terminal, and a control electrode connected to a constant voltage source. a first resistance means between the drain electrode of the first semiconductor transistor having the first conductivity and the other conductive electrode of the third semiconductor transistor; A complementary semiconductor device comprising a second resistance means between the drain electrode of the second semiconductor transistor and the other conductive electrode of the third semiconductor transistor.