JPH0483377A - Solid state imaging device - Google Patents

Abstract

PURPOSE:To improve conversion efficiency from charge to a voltage at an output unit by so forming a well region formed with the output unit as to isolate from a substrate by an insulating film. CONSTITUTION:An nM0S transistor 6 of an output unit 4 is formed on a p-type well region 2. Here, the region 2 is surrounded at its bottom and side by insulating films 3. Particularly, since the film 3 exists to a silicon substrate 1, the region 2 is electrically isolated from the substrate 1. n<+> type impurity diffused regions 7, 7 which perform functions of the source and drain of the nM0S transistor, are formed on the region 2, and an impurity diffused region 8 for applying a well voltage to the region 2 is formed. The well voltage can be raised to a value higher than a normal well voltage, for example to about 10V. Accordingly, since a problem of a withstand voltage is alleviated, the size of a gate electrode can be reduced, and a charge/voltage conversion efficiency can be enhanced.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to solid-state imaging devices such as CCD images.

[Summary of the invention]

The present invention provides a solid-state imaging device in which an imaging section and an output section are formed on a semiconductor substrate. By forming the well region in which the output section is formed so as to be separated from the substrate by an insulating film, it is possible to improve the conversion efficiency from charge to voltage at the output section.

[Conventional technology]

As a structure in a CCD image, a structure in which a P-type well region is formed on an N-type silicon substrate and an imaging section is formed in the P-type well region is known.

The imaging section includes a plurality of light receiving sections (photosensors) for photoelectric conversion arranged in a matrix, and a vertical charge transfer section for transferring charges for each vertical column of the light receiving sections. The signal charges obtained by these light receiving sections finally pass through a horizontal charge transfer section, and are converted from charges to voltage at an output section also formed in the p-type well region and output. Usually, the output section is configured with a plurality of stages of source followers, and the charge accumulated in the floating diffusion region activates the transistor in the output section to amplify the signal.

[Problem to be solved by the invention]

In a CCD imager using an n-type silicon substrate as described above, it is necessary to reset the potential of the floating diffusion region for each pixel, but due to limitations due to the charge transfer method, it is not possible to lower the reset voltage. In this case, a voltage of about 15V is required.

Also, in order to absorb variations in the dose of ion implantation, etc., the substrate voltage is increased. is the adjusted voltage value (e.g. 7~19
V), and in order to perform electronic shutter operation, the substrate voltage ranges from several volts to several tens of volts.
It varies within the range of.

Since the junction between the well region and the substrate must be reverse biased, the bias voltage is low when viewed from the substrate, for example, 0.
A voltage such as the following voltage is supplied to the well region.

However, when a voltage that is low compared to the substrate voltage is supplied to the well region of the output section and the MOS transistor of the output section is operated with a voltage of about 15V, the voltage between the MOS transistor and the well In order to ensure voltage resistance, it is not possible to reduce the size of the MOS transistor, such as the channel length. Therefore, it is not possible to reduce the gate capacitance of the MOS transistor in the output section, and as a result, it is not possible to improve the conversion efficiency from charge to voltage.

SUMMARY OF THE INVENTION In view of the above-mentioned technical problems, the present invention aims to provide a solid-state image sensor with improved charge-voltage conversion efficiency in its output section.

[Means to solve the problem]

In order to achieve the above object, the solid-state imaging device of the present invention has an imaging section and an output section formed on a semiconductor substrate, and a well region where the output section is formed is electrically isolated from the semiconductor substrate by an insulating film. It is characterized by being separated.

Here, the semiconductor substrate is, for example, an n-type silicon substrate, and the well region in which the output portion is formed is, for example, a p-type well region. The insulating film is, for example, a silicon oxide film, a silicon nitride film, etc., and a MOS transistor such as a source follower is formed in the well region. The method for manufacturing the solid-state image sensor of the present invention can have a structure in which silicon substrates are bonded together, and by placing an insulating film on the bonding surface and bonding, it is possible to easily insulate between the well region and the substrate. A membrane can be interposed.

[Effect]

By electrically isolating the well region from the semiconductor substrate by the insulating film, there is no need to supply a low voltage to the well region to maintain a reverse bias at the junction between the well region and the semiconductor substrate. Therefore, it is possible to supply the well region with a voltage having a potential difference within a range that is not very large with respect to the power supply voltage of the MOS transistor in the output section. As a result, the problem of breakdown voltage is solved, so the size of the MOS transistor can be reduced, and the charge-voltage conversion efficiency can be improved.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

This embodiment is an example of a CCD imager in which the well region of the output portion is surrounded by a silicon oxide film.

The CCD imager of this embodiment is as shown in FIG.
It is constructed using an n-type silicon substrate 1. The surface of this silicon substrate 1 is provided with an output section 4 formed in a P-type well region 2 and an imaging section 5 that receives light and generates signal charges.

Although not shown in the drawings, the imaging section 5 is provided with light receiving sections arranged in a matrix, and signal charges are generated when light is incident on the light receiving sections. Vertical charge transfer sections are formed in each vertical column adjacent to each light receiving section, and signal charges generated in each light receiving section are transferred via these vertical charge transfer sections.

The charges in each vertical charge transfer section are finally transferred to a horizontal charge transfer section, and signal charges are transferred to a floating differential region formed at the end of the horizontal charge transfer section.

The output unit 4 has nM that constitutes a source follower.

An S transistor 6 is formed. nMO of this output section 4
s) A transistor is formed on the surface of the p-type well region 2. Here, the bottom and sides of the p-type well region 2 are surrounded by an insulating film 3, and in particular, the silicon substrate 1
Since the insulating film 3 is present between the p-type well region 2 and the silicon substrate 1, the p-type well region 2 is electrically isolated from the silicon substrate 1. On the surface of this p-type well region 2, an n-type impurity diffusion region 7.7 is formed to function as the source and drain of the transistor (nMOS) transistor, and to apply a well voltage to the p-type well region 2. An impurity diffusion region 8 is formed.

In the case of this embodiment, the well voltage can be set to a higher value than a normal well voltage, for example, about 10V. In this way, when the well voltage is set to IOV, for example, even if 15V is supplied as the power supply voltage to the MOS transistor in the output section, the potential difference is only 5V, so the apparent upper MO3) transistor is connected to the 5V power supply. It will operate. Therefore, since the problem of breakdown voltage is alleviated, it is possible to sufficiently miniaturize the MOS transistor, and since the size of the gate electrode can be reduced, the charge-voltage conversion efficiency can be increased. Furthermore, since the p-type well region 2 is separated by the n-type silicon substrate 1 and the insulating film 3, the well region 2 is no longer affected by changes in the potential of the silicon substrate 1. ) Increased flexibility in transistor design.

For manufacturing such a CCD image, a technique for bonding substrates to each other can be used. The broken line 9 in FIG.
By indicating the position of the bonding surfaces and bonding at the broken line 9, the well region 2 can be easily surrounded by the insulating film 3.

FIGS. 2A to 2C are cross-sectional views schematically showing the method for manufacturing the COD image of this embodiment. First, as shown in FIG. 2a, a groove 22 is formed in a silicon substrate 21, and a silicon oxide film 23 is buried in the groove 22. As shown in FIG. Groove 22
The pattern is such that it surrounds at least the well region in which the output portion is to be formed on a plane, and the groove 22 is formed to be deeper than the depth of the well region. The oxide film 23 is deposited, for example, by a method such as CVD.

The silicon substrate 21 with the silicon oxide film 23 embedded in the groove 22 in this manner is ground or polished from the back side where the groove 22 is not formed. Then, it is gradually scraped from the back side, and the scraping is stopped when the silicon oxide film 23 inside the groove 22 is exposed on the back side. As a result, the silicon oxide film 23 has a pattern penetrating from the front surface to the back surface of the silicon substrate 21 and drawing a closed curve surrounding the well on the main surface of the silicon substrate 21 in which the output portion is to be formed.

While polishing the silicon substrate 21 in this way, a silicon oxide film 25 is formed on a part of the surface 27 of the silicon substrate 24 to be bonded. The region where this silicon oxide film 25 is formed corresponds to the position of the well where the output section is to be formed.

Then, as shown in FIG. 2, the silicon substrate 21 having a polished surface 26 and the silicon substrate 24 having a silicon oxide film 25 formed on a part of the surface 27 are bonded together.

FIG. 2C shows the silicon substrate 21 and the silicon substrate 24 bonded together, and the well region 28 is surrounded by a silicon oxide film 25 at its bottom and by a silicon oxide film 23 at its side. It is electrically isolated from the substrate 24. Therefore, by forming the output section in the well region 28, the size of the transistor in the output section can be miniaturized as described above, and as a result, the charge-voltage conversion efficiency can be improved.

In the above-described embodiment, a silicon oxide film is used as the insulating film, but the present invention is not limited to this, and other insulating films such as a silicon nitride film may be used. In addition, in the explanation of the manufacturing method, the manufacturing method was described as bonding the substrates together after polishing, etc., but after embedding an insulating film in the groove, the substrates are bonded together. It is also possible to use a manufacturing method in which the substrates are polished or the like after bonding.

〔Effect of the invention〕

As described above, in the solid-state imaging device of the present invention, the well region in which the output section is formed is electrically isolated from the semiconductor substrate by the insulating film, so that there is no forward bias between the well region and the semiconductor substrate. Therefore, the voltage supplied to the well region can be set to a voltage with a small potential difference from the power supply voltage of the transistor in the output section. Therefore, the problem of breakdown voltage is solved, and as a result, the size of the transistor can be reduced, and the charge-voltage conversion efficiency in the output section can be improved.

l...Silicon substrate 2...Well area 3...Silicon oxide film 4...Output section 5...Imaging section 6...nMOs transistor Patent applicant: Sony Corporation Representative patent attorney Akira Koike (and 2 others)

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view of an example of the solid-state image sensor of the present invention, and FIGS. 2A to 2C are schematic cross-sectional views for explaining the method for manufacturing the solid-state image sensor of the present invention. It is. Figure 2a 4th Vinegar Shrine / 1 set I Komakamo Sojime stone l Inn Issaichi Fallen surface map Figure 1 Figure 2 Figure 2 C

Claims (1)

[Claims] 1. A solid-state imaging device, characterized in that an imaging section and an output section are formed on a semiconductor substrate, and a well region in which the output section is formed is electrically isolated from the semiconductor substrate by an insulating film.