JPH0481946A - Bank busy control system in distance access of storage device - Google Patents

Abstract

PURPOSE:To simplify the bank busy control mechanism in a distance access and to facilitate the control by setting a bank busy time of the necessary minimum which corresponds to a distance value and can eliminate a bank conflict to each bank, and automatically stopping an access request to the same bank during that time. CONSTITUTION:In the case a distance access request is received, a controller 2 for executing the access control to a storage device 1 takes its priority, and simultaneously, generates an address of a distance access by an address generating part 5 corresponding to a bank. In that case, the access generating part 5 sets a bank busy time determined well-definedly in accordance with a distance value, so that it is inhibited during the bank busy time to send out an access request to the storage device 1 based on the generated address. In such a way, a bank busy control mechanism in the distance access is simplified, and the control is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] This invention relates to a link busy control method for distance access in a storage device with an interleaved configuration having a plurality of banks.

The purpose is to simplify the bank busy control mechanism in distance access and make it easier to control.

The control device that controls access to the storage device takes the priority of a distance access request when there is a distance access request, and at the same time generates a distance access address in an access generation unit corresponding to the bank. At this time, the access generation unit A uniquely determined bank busy time is set, and the sending of an access request to the storage device based on the generated address is inhibited during the bank busy time.

[Industrial Application Field] The present invention relates to a bank busy control method for distance access in an interleaved storage device having multiple banks.

Distance access is with the start address.

This is a process of continuously accessing a plurality of elements at regular intervals by giving a discance, which is the address distance between elements, and a length, which indicates the number of elements.

When performing distance access to a storage device with an interleaved configuration, the discance value and the bank vergence (WA
The banks determined by Y number) are accessed in parallel and sequentially.

Further, a certain bank busy time is set for each access for each bank, and the next access is inhibited during that bank busy time.

The present invention provides means for simplifying bank busy control during distance access.

[Conventional technology]

FIG. 6 shows a conventional SCMP (SCMP) having an interleaved storage device with a plurality of banks to which the present invention is applied.
This is an example of a cluster-coupled multiprocessor system.

In FIG.

CLE@~CLE are +1 clusters of independent processing systems (k≧1).

The SSU is a cluster-shared extended storage device.

CU o to CU are control devices compatible with +1 clusters for performing access request processing such as access address generation and priority control.

CLE, ~ Ao in CLE. ~Ak, is j+1 access sources per cluster such as CPUCHP, MSU included in +1 clusters (j≧1), and ss
u is shared, and when necessary, each independently requests access such as distance access to the SSU via the subordinate CU.

MEM o to MEMl in the SSU are n+1 storage devices divided into blocks, each of which has an interleaved configuration of m banks (n, m≧1).

Mo in CU, ~CUK. ~Mk is an access generation unit, which is provided corresponding to each bank and each has a distance register and a 1iiX circuit (not shown), C
Uo~CUK is Ao. When it accepts a distance access request from ~A0, it sequentially generates element addresses corresponding to banks based on the 8 values of that star's address, discance, and length.

Mo. The address of the element generated by ~Mk is.

The data is sent to PR10RTY, where a priority is assigned to each element in consideration of bank busy conditions, and an access request to the SSU is issued.

PREORITY in CU, .about.CU is a priority circuit that performs priority determination control of the addresses of each element generated in 1M0.about.M, and in the conventional system, bank busy control is also performed here.

PRI 0RTY has a number of bank busy registers equal to the bank width in order to manage the bank busy state of each bank, and when an access request is issued to a certain bank, the bank busy register corresponding to that bank is set to the busy state. is set to suppress access requests to the same bank during a certain bank busy time.

[Problems to be Solved by the Invention] In the conventional system, in order to manage bank busy in distance access, it is necessary to provide bank busy registers in a number equal to the bank width, which increases the amount of hardware and also requires priority every cycle to take
That is, it is necessary to refer to the state of the bank busy register for each element, resulting in a problem that control is complicated.

The present invention aims to simplify the bank busy control l1m structure in distance access and facilitate control.

[Means to solve the problem]

The present invention provides busy time management on a bank-by-bank basis without prioritizing distance access requests in each memory cycle until each element within a specified length has been accessed. Priority control is simplified by using the access generation unit that is installed. However, by not taking priority in each memory cycle, a bank conflict may occur, so each bank must correspond to a distance value.

A minimum necessary bank busy time that can eliminate bank conflicts is set, and requests for access to the same bank are automatically suppressed during that time.

FIG. 1 is a diagram showing the basic configuration of the present invention.

1 is a storage device, ? It has an interleaved structure with JI number banks.

2 is a control device that controls access to the storage device 1;

3 is a command register in which a command for an access request sent from the access source is set. The illustrated command is a distance access request command, which includes command codes such as store (S) and fetch (F), and distance.

It has length and start address fields.

4 is a priority circuit, and command register 3
When a distance access command is input to the memory device W1, it is confirmed that all banks of the storage device W1 are not busy, and priority is given to the memory device W1.

When access requests are sent to the storage device for all elements to be accessed by this command, the priority is released.

Reference numeral 5 denotes an access generation unit, which is provided corresponding to the bank width. A real address for the storage device 1 is generated based on the start address and distance value given by the command, and bank busy control according to the present invention is performed.

6 is an address conversion circuit that generates a real address.

6a is a real address register that stores the generated real address.

7 is a distance value decoder, which outputs a bank busy time according to the distance value.

Bank busy time is specified by the number of memory cycles.

8 is a bank busy counter, and the bank busy time of the output of the decoder 7 is preset.

The bank is counted down every memory cycle, and when the count value reaches "0", the bank busy time ends, that is, the bank becomes empty.

p is an AND gate, and is determined by the end of the bank busy time and the priority output.

Address transmission from the real address register 6a to the storage device 1 is enabled and an access request is made.

[For production]

According to the present invention, there is no need for the priority circuit to provide bank busy registers corresponding to banks and perform bank busy control every cycle as in the conventional system, and bank busy control is performed within the access generation unit, so distance access processing is performed. priority control becomes simple.

〔Example〕

Although the present invention can be implemented in any system having a 5-interleave configuration of storage devices.

Here, a case will be explained using the SCMP system shown in FIG. 6 as an example. In this case, the control devices CU, ~CU in FIG.
, is changed as in the configuration of the present invention shown in FIG. The memory device is assumed to be one MEM, to MEM, l, and its bank width (number of WAYs) is 32. Furthermore, the correspondence between the distance value in the decoder 7 in FIG. 1 and the bank busy time, that is, the set value of the bank busy counter 8 in FIG. 1, is as shown in FIG. 2(a).

The distance values are 2, 4, 8°16.3 for simplicity.
The bank busy time is limited to each multiple of 2, and the corresponding bank busy time is 1, 3.6, and 12.25 cycles, respectively.

FIG. 2(b) shows an example of bank busy control when the distance value is a multiple of 4. The horizontal direction of the figure shows the arrangement of banks, and the vertical direction shows the numbers of distance access elements for which access requests are generated for each memory cycle.

If the distance value is a multiple of 4, the bank busy time will be 3 cycles from FIG. 2(a), so the value "3" is set in the bank busy counter 8 of FIG. Therefore, in the first cycle in FIG. 2(b), 8 elements are accessed in 8 banks, but in the next 3 cycles, the bank busy counter 8 indicates a busy state, resulting in WAIT, and access is is suppressed.

Then, in the next cycle, bank busy counter 8 becomes “0”
Therefore, it is made accessible.

FIG. 3 shows an example circuit of the decoder 7 shown in FIG.

In the figure, 10 is a distance, and D, to D8 indicate its bit arrangement.

11-1 to 11-5 are AND gates, each with “
The least significant bit with a value of 1” is Dll, Di −2
, Di -3, D=-4+D, -5, that is, the multiple values of 2, 4.8, and 16°32 are detected. The outputs of the AND gates 11-1 to 11-5 are 1.3, 6, and 12.2 of the bank busy time, respectively.
Specify each cycle of 5.

12-1 to 12-4 are OR gates that convert each output of the AND gates 11-1 to 11-5 into corresponding binary values. For example, if the bank busy time is 3 cycles, 2
The base value is 00011.

OR game) The binary values of the outputs of 12-1 to 12-4 are.

The bank busy counter 8 is set.

FIG. 4 shows an example circuit of a bank busy control mechanism using the bank busy counter 8 of FIG.

In the figure, 13 is a NOR gate, and when the output of the bank busy counter 8 is "ooooo".

to one input of AND gate 9 BANK BUSY Tength "1" is output to notify the bank of free space.

The other input of AND gate 9 is the output Pt0RITY OK of priority circuit 4 in FIG.

AND when PRIORITY OK = “1”
Gate 9 outputs "1".

14 is a valid flag, and “1” of AND gate 9
When the output is set, the output of the 5 real address register 6a is displayed as valid, and an access request to the storage device 1 of FIG. 1 is made.

FIG. 5 is a time chart of bank busy control according to the embodiment of the present invention.
07'', bank busy time = "03" (a multiple of distance - 4).The figure is shown in detail based on an actual circuit, so it corresponds to the circuit configuration of the present invention described above. Only parts will be explained briefly.

In FIG.

■ is a memory cycle, ■ is a block valid,
The target block (MEM,
) is accessible.

(2) is a start trigger created from block valid, and (2) is a start control timing consisting of TO to T5.

■ is the command and distance read from the access source at timing To, and ■ is the length and start address read at timing T1.

(2) is the state of the bank busy counter, in which the number of cycles (03) of the bank busy time as a result of decoding the distance value is set, and thereafter it is counted down every memory cycle to continue the cyclic counting operation.

3 is a bank busy signal based on the bank busy counter output.

3 is a priority request signal issued to the priority circuit at the timing T5.

[Phase] is a priority release signal indicating acquisition of priority as a result of taking priority.

(2) is the logical address of each element (00 to 07) calculated by the address conversion circuit based on the start address and distance.

(2) is the real address of MEM generated by converting the logical address.

@ is a count of generated real addresses.

(2) is a priority release signal sent to the priority circuit when the count value of the real address matches the length (07).

(Effects of the Invention) According to the present invention, in distance access, the priority circuit does not need to monitor the busy state of each bank every cycle (no bank busy register is required, and control is significantly simplified).

[Brief explanation of drawings]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIGS. 2(a) and 2(b) are diagrams explaining the correspondence between the distance and the set value of the bank busy counter according to the embodiment of the present invention, and FIG. 3 is according to the embodiment of the present invention. 4 is a circuit diagram of a bank busy control mechanism according to an embodiment of the present invention, FIG. 5 is a time chart of bank busy control according to an embodiment of the present invention, and FIG. 6 is a configuration diagram of a conventional SCMP system. be. In Figure 1. 1: Storage device 2: Control device 3: Command register 4 Ni priority circuit 5: Access generation section 6: Address conversion circuit 7: Decoder 8: Bank busy counter 9: Gate

Claims (3)

[Claims] (1) It has a storage device with an interleaved configuration consisting of a plurality of banks, and a plurality of control devices that perform access to the storage device in consideration of the bank busy time of the corresponding bank in response to access requests from a plurality of access sources, In a storage system in which each control device is provided with an access generation unit that generates a series of addresses for distance access in a bank-compatible manner, each of the plurality of control devices described above takes priority when there is a distance access request. At the same time, the bank-compatible access generation unit generates a distance access address, and at this time, the access generation unit sets a bank busy time that is uniquely determined according to the distance value, and accesses the storage device based on the generated address. A bank busy control method for distance access of a storage device, characterized in that sending of requests is suppressed during the bank busy time. (2) In claim (1), the access generation unit includes a decoder that specifies the bank busy time by the number of memory cycles according to the distance value, and a bank busy counter that has the decoder output set and counts down according to the memory cycles. , a gate that sends an access request to the storage device when the value of the bank busy counter becomes "0" in accordance with a match with the priority output. method. (3) According to claim (1) or (2), the storage device is a block-divided storage device in an expanded storage device of a cluster-coupled processor system, and bank busy control in distance access of a storage device. method.