JPH0480584B2 - - Google Patents

Description

Claim 1: A data communication subsystem for controlling data transfer operations to and from a plurality of remote data terminals via a plurality of telephone lines, comprising: (b) a plurality of line adapters LA0-LA3 provided corresponding to each of the telephone lines for transmitting and receiving data via the telephone line; (b) transmitting and receiving data by each of the plurality of line adapters; and a microprocessor 600 for controlling (b1) the I/O bus 10, and (b2) holding control data necessary for transmitting and receiving data via the telephone line. (c) based on a designation signal of the control data supplied from the first output control register, one of the plurality of line adapters is selected. (d) a plurality of automatic calling devices 505u _{0 -5} provided corresponding to each of the plurality of line adapters _;
05u ₃ and associated dataset 800ds ₀
-800ds ₃ , each of the plurality of automatic calling devices includes means for generating a signal indicating the state of the corresponding telephone line, and one of the plurality of automatic calling devices is selected by the designated logic means. (e) is controlled by said microprocessor and corresponds to said designated line adapter to establish a telephone line connection to a remote data terminal; (f) multiplexer means 504, 506 for receiving data and signals indicative of telephone line status from the automatic calling device and routing them to the I/O bus of the microprocessor; (f) for each of the plurality of line adapters; A plurality of automatic calling device output registers 505 ₀ correspondingly provided and connected to each of the microprocessor and the plurality of automatic calling devices.
-505 ₃ , each of the automatic calling device output registers holding dial data of the control data supplied from the second output control register; (g) controlled by the microprocessor; addressing means 80p for addressing one of the plurality of automatic calling device output registers that corresponds to the designated line adapter;
(h) gate means N3 ₀ -N3 ₃ activated by said addressing means and said designation logic means to provide a clock signal to said designated automatic calling device output register, the automatic calling device output register supplied with the automatic calling device output register supplies the dial data to the corresponding automatic calling device in response to the supplied clock signal; further comprising a bit line connection means for transmitting the dialing data to the device, the dialing data including a numeric dialing signal and a control signal that enables the automatic calling device to receive the numeric dialing signal. , data communications subsystem. 2. The bit line connection means according to the claim includes: (a) a 4-bit line for transmitting the binary coded data of the numeric dial signal; and (b) a 2-bit line for transmitting the control signal. The data communication subsystem according to scope 1. 3. One of said 4-bit lines is used to control the operating state of said data set associated with said automatic calling device during periods when said 2-bit line is inactivated. Data communications subsystem as described in Section 1. FIELD OF THE INVENTION This invention relates to data communications subsystems that employ multiple line adapters (multiline adapters) each handling separate telephone communication lines to remote data terminals. CROSS-REFERENCE TO RELATED PATENT APPLICATIONS This invention also relates to Richard A. Loskorn, Philip
D. Biehl and Robert D. Catiller, and filed on March 5, 1982 under U.S. Patent Application Nos. 355135 and 355134, entitled "Line Adapter System for Part-Time Users" and "Line Adapter for Part-time Users" It is also related to two applications entitled ``Systems''. In the data communication subsystem of this invention,
Several patents are incorporated by reference that form the background and description of microprocessors used with line adapters. These patents, which are incorporated by reference, are: U.S. Pat. U.S. Patent No. 4,291,372 entitled "Microprocessor System with Encrypted Instruction Format"; U.S. Pat.
No. 4292667; and “Input for Digital Data Processing Systems -
No. 4,189,769 entitled ``Output Subsystem.'' SUMMARY OF THE INVENTION The present invention provides a system for controlling data transfer operations to and from multiple remote data terminals over multiple telephone lines. A data communications subsystem comprising multiple line adapters and
a microprocessor, a specification logic means, a plurality of automatic calling devices and associated data sets, a multiplexer means, a plurality of automatic calling device output registers, addressing means, gating means;
bit line connection means. A plurality of line adapters are provided corresponding to each of the plurality of telephone lines, and transmit and receive data via the telephone lines. The microprocessor controls data transmission and reception operations by each of the plurality of line adapters, and also maintains the I/O bus and control data necessary for transmitting and receiving data over the telephone line. first and second output control registers. The designation logic means designates and activates a specific one of the plurality of line adapters based on a designation signal of control data supplied from the first output control register. A plurality of automatic calling devices and associated data sets are provided corresponding to each of the plurality of line adapters, and each of the plurality of automatic calling devices includes means for generating a signal indicative of the status of the corresponding telephone line. The one of the plurality of automatic calling devices corresponding to the line adapter designated by the designation logic establishes a telephone line connection to the remote data terminal. Multiplexer means is controlled by the microprocessor to receive data received by the designated line adapter and signals indicating the state of the telephone line from the automatic calling device and to route the data to the I/O bus of the microprocessor. route to. The plurality of automatic calling device output registers are provided corresponding to each of the plurality of line adapters, and are connected to the microprocessor and each of the plurality of automatic calling devices, and are connected to the dials supplied from the second output control register. Retain data. The addressing means is controlled by the microprocessor to address one of the plurality of automatic calling device output registers that corresponds to the designated line adapter. The gating means is activated by the addressing means and the specifying logic means to provide a clock signal to the designated automatic calling device output register, and the designated automatic calling device output register is responsive to the applied clock signal. and supplies the dialing data to the corresponding automatic calling device. The bit line connection means transmits dial data from each of the plurality of automatic calling device output registers to the corresponding automatic calling device, and the dialing data allows the automatic calling device to receive a numeric dialing signal and a numeric dialing signal. control signals to

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a data communications subsystem showing a plurality of slide-in cards that fit into the back of its main module and front connectors therebetween. FIG. 2 is a block diagram showing the basic configuration of a data communications subsystem including a single byte-oriented line adapter. FIG. 3 is a block diagram showing the configuration of a data communication subsystem including a plurality of byte-oriented line adapters. Fourth
The figure is a block diagram showing the configuration of a state machine processor that controls a single or multiple line adapter. FIG. 5 is a diagram schematically showing a format for operators of the state machine processor shown in FIG. FIG. 6 is a block diagram illustrating the logic used to select memory or other components for any line adapter. FIG. 7 is a schematic block diagram illustrating a circuit for identifying a line adapter or its subcomponents. Figure 8 shows automatic calling unit (ACU)
FIG. 2 is a timing diagram for dialing. 9th
The figure is a block diagram illustrating circuitry for addressing and loading selected ACU output registers. FIG. 10 is a timing diagram showing the sequence of operations. DESCRIPTION OF PREFERRED EMBODIMENTS FIG. 1 is a schematic diagram showing the configuration of a data communication subsystem 300 according to the present invention. In this data communication subsystem 300, a card 600 on which a state machine processor (microprocessor) is mounted works in cooperation with various cards 400, 500, 700 equipped with line adapters via front connectors. Card 700 has a single line adapter (LA)
and data link interface equipment (DLI)
will be installed. On the other hand, cards 400 and 50
Each of the 0's is a quadruple line adapter card with four addressable line adapters. Each of the multiple line adapters mounted on these cards can handle sending and receiving data to and from a single remote data terminal via an electrical interface. Next, FIG. 2 is a block diagram showing the configuration of a data communication subsystem including a single byte-oriented line adapter, which is a basic component of the present invention. In FIG. 2, a remote data terminal (not shown) connects a telephone line connection (dashed line) and electrical interface (EI) ₈₀₀₀ established by ACU 505u and associated data set 800ds.
A timer 507 and a general-purpose synchronous/asynchronous receiver/transmitter (hereinafter referred to as USART) 508
The telephone line is connected to a line adapter (LA) consisting of a telephone line, and allows data to be transmitted and received between the remote data terminal and the line adapter via the telephone line. Note that the electrical interface 800 ₀ (for example
The RS-232 electrical interface (RS-232 electrical interface) performs the necessary conversion of signal levels. The line adapter is coupled to a transceiver bus controller (bus driver) 503 that transfers data via I/O bus 10 to state machine processor 600 or to RAM.
Data can be routed to multiplexer 504 for transmission to buffer 550m. On the other hand, the data in the state machine processor 600 is stored in the state machine output control register 3.
8 to the transceiver bus controller 503 along bus 17 ₂ and further routed along bus 17 2 to the line adapter
Transmitted to LA. Control signals for dialing remote data terminals on the telephone line also flow from state machine output control register 38 to bus 1.
7 ₂ via autocaller output register 505
given to. This control signal is used for the purpose of dialing the remote data terminal over the telephone line and establishing a telephone line connection so that data can be transferred from the line adapter to/from the remote data terminal to the line adapter. , electrical interface 8
After the signal level is changed through 00 ₀ , it is provided to automatic calling unit (ACU) 505u. This automatic calling device 505u then retrieves the data set 8.
00ds can be operated to dial and connect a telephone line to data set 800ds. The multiplexer 504 also receives control signals from the data link interface device (DLI) of the card 700 shown in FIG. 1, as well as other control signals specifying the line adapter. Furthermore, once the data set 800ds is connected to the remote data terminal via the telephone line, the associated ACU 505u sends a status signal (ACUST) to the second multiplexer input of the multiplexer 504, which
4 can then communicate this signal to state machine processor 600 via I/O bus 10. The microprocessor 600 performs data transmission or data reception as the case may be.
The USART 508 can be commanded. As a result, the USART can send data through or retrieve data from dataset 800ds, depending on whether a "write" or "read" operation is requested. You can receive it. Next, FIG. 3 is a block diagram showing the overall configuration of a data communication subsystem including a multi-line adapter card equipped with a plurality of byte-oriented line adapters according to an embodiment of the present invention. To first briefly explain the data communication subsystem of FIG. 3, a plurality of line adapters LA0-LA3, each connected to a remote data terminal (not shown) via a telephone line, are integrated into a single microprocessor. The telephone line connection to the selected line adapter is controlled by the processor (state machine processor) 600 and the automatic calling unit (ACU) 505u ₀ -
_505u3 . In addition, each of the plurality of line adapters (four in the embodiment of FIG. 3) has one timer and one
It is composed of USART. To explain in more detail, line adapter LA0 and timer 0
Consists of USART0 and line adapter LA1
is composed of timer 1 and USART1, line adapter LA2 is composed of timer 2 and USART2, and line adapter LA3 is composed of timer 3 and USART2.
Consists of USART3. Any of these line adapters is designated by the state of the corresponding one of the designated flip-flops _DESF0 to _DESF3 . This specification applies to the state machine processor 600.
is controlled by control signals from the I/O bus 10. On the other hand, the specified flip-flop DESF ₀
-DESF ₃ is a state machine processor 600
selects the timer and USART of the specified line adapter. The output of each selected line adapter is transferred from the USART to the data set 800ds via the corresponding electrical interface 800.
and further communicated to a remote data terminal via a telephone line connection. A telephone line connection to such a designated line adapter is established by the corresponding automatic calling device 505u. Such automatic calling device 505u
The second processor in the state machine processor 600
Dial digit data is provided from the output control registers 38 of the automatic caller output registers 505 ₀ -505 ₃ and through corresponding ones of the electrical interfaces 800 ₀ -800 ₃ . The data in the register 38 is also transferred to the bus driver 5.
03 to the line adapters, while each line adapter has a multiplexer 504 and an I/O
It is connected to microprocessor 600 via bus 10. Further selected automatic calling device output register 5
Gate means N3 ₀ to _{N3 3} for activating 05
is provided, and this gate means corresponds to
DESF output and state machine processor 60
It is activated by the output of address decoder 80p operated by the instruction from 0. Furthermore, whether the telephone line connection is completed or not,
A signal ACUST is transmitted from automatic calling device 505u to state machine processor 600 via corresponding electrical interface 800, multiplexer and I/O bus 10. The line adapter, on the other hand, uses a set of multiplexers 504 and 506. 504 and 5
Each multiplexer, such as 06, is essentially a set of "dual" operating multiplexers in that it receives control signals from two different line adapters. Multiplexer 504 receives input signals from line adapters 0 and 1, while multiplexer 506 receives input signals from line adapters 2 and 3. Also, for this quadruple line adapter,
RAM buffer memory 550m ₁ and 550m ₂
A special collection of Next, the configuration and operation of each element constituting the data communication subsystem shown in FIG. 3 will be explained individually and in detail. FIG. 4 is a block diagram of a state machine processor 600 used to control a single line adapter as shown in FIG. 2 or a multiplexed line adapter as shown in FIG. . A state machine processor 600 (often referred to as a general purpose input/output (UIO) state machine) is mounted on a circuit board of a chip that can be inserted as a slide card into a main body module (FIG. 1). At the slide card is connected to its back. As shown in FIG. 1, the state machine processor is connected to a logic circuit depending on the application via a front connector. A detailed description of the elements and use of the UIO state machine processor is the subject of several prior art publications included in the references. These patents are: Invented by Robert D. Catiller and Brian K. Forbes, United States Patent No.
No. 4293909; United States Patent No. 4291372, invented by Brian K. Forbes and Robert D. Catiller and entitled “Microprocessor System with Specified Instruction Formats”; and Robert D. Catiller and Brian K. US Pat. No. 4,292,667, entitled "Microprocessor System to Facilitate Instruction Repetition," invented by .Forbes. The use of a host computer to operate in conjunction with an input/output (I/O) subsystem that uses unique instructions called input/output (I/O) descriptors, data link descriptors, and result descriptors is “Input-Output Subsystems for Digital Data Processing Systems” by Darwen J.Cook and
No. 4,189,769 issued February 19, 1980 by Donald A. Millers,
This patent is also included by reference. UIO state machine processor 600 in Figure 4
A microprocessor (microprocessor) is configured to implement a useful set of general purpose operators (OPs).
These operators include the following (the following descriptions are included in the above-mentioned US Pat. Arithmetic operators Logical operators Read/Write Memory operators PUT/GET operators Program stack operators “branch,”
All input/output lines shown at the bottom of Figure 4 are front lines that connect to peripheral control logic. In the circuit of Figure 4, a group of interconnects line 1
6,17 ₁ ,17 ₂ ,18,10,19,11,1
2 and 20 are respectively connected to peripheral logic circuits. These lines are displayed as follows. External memory data output bus 12 I/O and memory write parity lines 18 Memory address bus 16 Memory write enable 19 (and other functions listed in FIG. 4) Direct memory access DMA request line 11 (and Other functions in the figure) Main I/O bus 10 Instruction output bus 1 from program PROM 50
5 The program counter 41 is connected to the stack memory 4.
5 and an I/O bus 10, and an output line for providing input signals to a program PROM 50 (internal memory 50). The memory reference register 40 (MRR) is
It receives input signals via I/O bus 10 from an accumulator register 30, a memory operand 31 and a save-MRR 47 (memory reference register-save). Repetition counter 42 also includes accumulator register 30 and memory operand 3.
1 receives an input line via an I/O bus 10 for signals from the I/O bus 10. Stack memory 45, controlled by stack pointer 46, provides an output line to program counter 41. The repetition counter 42 is
It provides an output that returns to the accumulator register 30 via the I/O bus 10. First control register 37 , second control register 38 , and parity register 39 receive input from I/O bus 10 . and control registers 37 and 38 on lines 17 ₁ and 17 ₂
This causes a signal buffeting. Parity register 39 has an output line 18 that is part of I/O bus 10 and provides "I/O and memory write" parity. A memory output data bus 12 from the RAM external memory is connected to a memory operand register 31, and the output of the register 31 is given to an ALU 32 and a parity check circuit 21, which outputs memory read parity to the external memory. It has an output line 20 for supplying. Data bus 12 also provides input to an instruction register 22, which has an output line connected to an input of an instruction decoder and controller 23. Arranged inside the instruction decoder-controller 23 are an external flag register, an interrupt mask, and a state counter (not shown). I/O bus 10 is an accumulator register 30
register 30 provides an output to one input of arithmetic logic unit 32.
The other input of arithmetic logic unit 32 comes from memory operand register 31;
receives its input from external memory via memory output bus 12 or from internal memory via bus 15. The arithmetic logic unit 32 (ALU) has a set of outputs provided to a "front" flag register 35 and a "back"
and another set of outputs provided to flag register 36. These flag registers 35 and 36 constitute the output provided to the instruction decoder-controller 23. They are used to signal a "front mode" condition for normal operation and a "rear mode" condition for interrupt or emergency operations. The F output of arithmetic logic unit 32 is communicated to shift logic circuit 33 and byte swap circuit 34. The outputs of these circuits 33 and 34 are connected to I/O bus 10. FIG. 5 is a diagram schematically showing an instruction format for operators of a state machine processor (microprocessor) 600. The PUT operation (operator) writes a 16-bit word (two bytes denoted as A and B) from the I/O bus 10 to a selected external register;
addressed by. The PUT operator can address any external register. The GUT operator transfers data from selected external registers to accumulator registers 30 on state machine processor 600 or to I/O bus 10.
Read a 16-bit word into RAM memory via The GET operator can address any selected external register. The state machine processor 600 loads the number N (from software) into the iteration counter 42 and sets the memory reference register to be used as a counter after being loaded with the starting address of the data block to be used in the "iterated" operation. By controlling (MRR) 40, it has the ability to repeat certain operators (PUT, GET and logical operators). To hold “PUT data”, two 8
Bit registers (control registers 37, 38) are provided and these registers are located within the microprocessor 600. The strobes of these registers 37, 38 are controlled by external registers. The ``WAIT'' line on bus 11 indicates that when external ``slow memory'' is addressed, the ``slow memory'' is processed by the state machine program, no matter how long it takes for a read or write to become valid. It is incorporated into the state machine processor 600 so that the processor 600 can be forced to write. This is shown on bus 11 in FIG. 4, which signals an instruction decoder-controller 23. This line can also be used to stop the machine.
A clock enable line on bus 11 is included to allow external registers to control the state machine clock for single pulse and direct memory access (DMA) operations. The timing of this signal is the same as the WAIT signal on bus 11. As shown in FIG. 4, state machine processor 600 can check each memory fetch through circuit 21 for odd parity. All memory fetches from external memory travel on a memory output data bus, shown as bus 12 and connected to instruction register 22 and memory operand register 31. All memory writes exit on I/O bus 10 with odd parity on line 18. The microprocessor can contain an 8K word user-specified instruction program in PROM 50;
50 can be expanded to 60K words. In FIG. 4, memory addresses originate from two sources: a program counter 41 and a memory reference register (MRR) 40. The microprocessor can perform conditional or unconditional branching,
Provides the ability to call and return. "Calls" can be nested up to 16 levels from stack memory 45. The memory reference register 40 is
It is used to store addresses and address RAM data memory, which will provide programs applicable to peripherals that connect to external registers. This external memory also functions to store data being transferred between the host computer and the peripheral terminal device. External and internal memory are configured to be 2 bytes wide (16 bits + parity),
Data for transfer is often required in single byte format when the peripheral device is a card reader, and the memory reference register (MRR) 40 is
Only 15 bits are designed to be used to address external memory. The lower bit (BYTESWP) is stored in the external memory before being stored in the accumulator register 30 in "external data memory read" or in "data memory write".
Used by byte-oriented read/write operators to determine whether to byte-swap 2-byte data words before writing to RAM data memory. These particular features ensure that a "data memory write" is automatically written to the correct byte location from the "lower" byte location, and
This allows the microprocessor to easily process byte oriented data in that on a "data memory read" the desired byte is automatically read into the "lower" byte location of the accumulator register 30. The "high" byte location of accumulator register 30 must contain the last byte written, if any. Next, FIG. 6 selects the selected memory of a particular one of the RAM buffer memory on a card with a single line adapter or the four line adapter memories on a card with a quadruple line adapter. used to designate or “specify”
2 is a diagram of certain logic circuits of DLI/LA card 700 (FIG. 1). FIG. Shown in FIG. 6 as RAM storage means 550m is the specific memory used for a single line adapter. However, “multiple”
In the case of line adapters, each line adapter has 550 m <sub>1</sub> and 550 m <sub>2</sub> of local RAM memory.
3 with a similar selection system for selecting the particular memory associated with that line adapter. In FIG. 6, state machine processor 6
The address line (MADDRnn) from 00 is connected to the comparator 100c and the RAM buffer 550.
connected to m. Chip select signal CS/ is activated to buffer memory 550m by a logic signal from comparator 100c and designated flip-flop (DESF). A unique jumper bit is used to specifically identify any selected buffer memory in the system.
An input is provided from the I/O bus 10 to a designated flip-flop. The particular bit line to be selected on I/O bus 10 is set by state machine processor 600 of FIG. "Byte-oriented" line adapter A functional section of the line support processor (also referred to as frame recognition data link processor and/or line support processor - DLP) is a line adapter called a "byte-oriented line adapter." It is also often referred to as a "character-oriented line adapter." A data communications line adapter essentially connects a data communications line with an "electrical interface" at one end.
and UIO at the other end.
A device that interfaces to a processor shown as state machine processor 600 (UIOSM). The first function of a line adapter is to convert "bit" information to "byte" information and from "byte" information to "bit" information, provide timing, and generate requests for service.
To provide RAM memory, to provide an autocall interface, and to provide a connection to a level converter that would be compatible with the data communication line. Part-time line adapters are also comprised of two basic shapes designated as (i) quadruple line adapters and (ii) single line adapters. The single line adapter is part of the line support processor, and the single line adapter is allocated on the same board as the data link interface (DLI) circuit. Line adapters are required regardless of the amount of lines being controlled by the line support processor. A quad line adapter essentially includes four line adapters on one board. These boards are
It is typically a 10" x 13" board that plugs into the back of the base connection module (Figure 1). As shown in FIG. 1, each line adapter card 400, 500 is connected to both a state machine processor 600 and a DLI/LA 700 (data link interface/single line adapter). As shown in FIGS. 2 and 3, the connection to the data communication line is through an electrical interface (EI) that connects to a line adapter. There are various types of electrical interface boards that can exist and be mounted in different combinations on a quad line adapter. Therefore, the only change required according to the electrical characteristics of the data communication line is that of the electrical interface, and the line adapter remains the same. Line adapters 1 through 16 are addressed differently by state machine processor 600, so each line adapter is uniquely jumpered to identify its address. A line adapter must be "designated" to the state machine processor to communicate with it. Included on the line adapter are several addressable components with which the state machine processor communicates in the form of write/read data or "status" or "control" signals. The addressable components of the byte-oriented line adapter are: (i) USART (508, 510, 512, 514,
(Figure 3) (ii) Timer (507, 509, 511, 513,
(Figure 3) (iii) Automatic call output registers 505 <sub>0</sub> , 505 <sub>1</sub> , 5
05 <sub>2</sub> , 505 <sub>3</sub> (iv) Automatic call state ACU <sub>0</sub> , for each ACU
ACU <sub>1</sub> , ACU <sub>2</sub> , ACU <sub>3</sub> (v) Component requestors (devices inside the USART and timers) (vi) Memory (RAM) (RAM in single card LA or RAM in quadruple card LA) machine processor 600
The USART also receives serial bit data and converts it to parallel data bytes. A USART device is initialized by writing to two internal control registers that specify the manner in which it operates. Preferred typical USART for this purpose
Western Digital Corporation (3128 Redhill
Avenue, Newport Beach, California) and designated UC1671, and
The UC1671 asynchronous/synchronous receiver/transmitter is described in the technical manual dated August 1978. Various bits in the internal control registers of this USART unit specify: synchronous/asynchronous mode; bits per character; parity; baud rate;
And it's in echo mode. The timer used on the part-time line adapter performs two basic functions. (i) as a program timer; and (ii) as a baud rate generator for asynchronous operation. Three independent internal timers are included in each chip, two of which are used by the software for timing purposes with respect to line operations for "transmit" and "receive" operations. A third timer is used to generate a square wave clock signal used by the USART for asynchronous operation. Each timer is independently initialized to indicate the "mode" in which it should operate. The two program timers may activate flag signals to state machine processor 600 when predetermined timing values are reached. Automatic call output register (ACUOR50) in Figure 3
5) are registers loaded with "dial digits" and control information by the state machine processor. The output of this register is a logic signal.
Drives a level conversion chip that converts to EIA RS-232 voltage. These signals drive an automatic calling unit (ACU), such as the Bell 801, which provides dial-out capability. Automatic call state (ACUST0, ACUST in Figure 3)
1, ACUST 3) is means for providing the state or situation of the input line from the automatic calling unit (ACU) to the state machine processor 600. ACU
The line from is received by a level converter chip that converts the EIA voltage to TTL logic levels.
These logic levels are read by the state machine processor to determine the current situation. The component requestor from the line adapter is as follows. That is, (i) USART; (ii) program timer 1; and (iii) program timer 2. These three components can generate "service requests" independently of each other at their own times regarding their initialization. "Service Request" activates a flag signal to the state machine processor indicating that the line adapter is requesting service. After the state machine processor determines which line adapter is requesting service, it must determine which "component" on a particular line adapter is requesting service. The memory on the line adapter consists of 2048 x 17 bit words of RAM for each line. Therefore, each quad line adapter card actually has 8192 x 17 bit words of RAM.
Contains. A single line adapter card (FIG. 2) contains 550m of RAM with 4096 words, half of which is for the data communication lines and the remainder for the DLI 700.
The RAM is used by the software for transmitting/receiving message buffers, for tables, and for statements related to line operations. Byte-Oriented Line Adapter - Operation Assignment: When the state machine processor 600 executes code for an addressable component on a line adapter (LA), the LA is "assigned".
It must be. Each line adapter (as shown in FIG. 6) includes a flip-flop whose inputs are jumpered to particular bits of the I/O bus of FIG. To “designate” a line adapter, the state machine processor uses strobe no.
A 1 performs a PUT operation (placing data in a particular location, such as a register or memory), and the corresponding bit on the I/O bus must be equal to 1. Performing the same operation with the I/O bus bit equal to 0 will reset the designated flip-flop, typically shown as "DESF" in FIG. Flag operations: Various components of the line adapter can generate "service requests."
These "service requests" are essentially ORed together to drive a common flag line for all line adapters. The signal line, flag 2/, when low active, indicates to state machine processor 60 that some line adapter is requesting service.
Inform 0. The state machine processor is
Variant field V-FLD equal to 00001
(4:5) to determine which line adapter is requesting service by performing a GET operation (the act of retrieving or accessing a data word or information from a circuit such as a memory or register). can be determined. The line adapter is
It does not need to be "specified" to perform this operation. “Register address” in line adapter
The (REGADRn) signals are the five V-FLD signals from the state machine processor. The flag operations associated with FIG. 7 are completed by Flag 2/Line, which when active low indicates to the state machine processor that the line adapter is requesting service. For example, in FIG. 7, if line adapter 0 requests service, then NOR gate G <sub>0</sub> is activated and provides a signal (low) on flag 2/line. Upon receiving this signal, the state machine processor initiates a GET operation on the GET flag ID line. This sends the output signal of gate G <sub>0</sub> to a particular line of the I/O bus (dedicated to a particular one of the line adapters), which line, when read by the state machine, , in this case line adapter 0. Similarly, each line adapter, 1, 2, 3, etc., activates flag 2/line in gate G <sub>1</sub> , G <sub>2</sub> or G <sub>3</sub> and causes the state machine to ``Read'' a particular ``jumper'' bond for a line. Data Bus Structure: All data sent to the addressable components on the line adapter, except for the RAM (Figure 6) or memory 550m ₁ , 550m ₂ , is sent to the "second" output in the state machine processor. Generated from control register 38 (FIG. 4). All data "read" by the state machine processor from addressable components on the line adapter, except for RAM, is sent to the state machine processor via I/O bus 10. With reference to FIG. 2 (DLI/LA Data Bus Structure), a single line adapter data bus structure is shown. As shown in FIG. 2, line 17 ₂ (OCREG20n) of the second output control register 38 (FIG. 4)
is automatic calling device output register 505
(ACUOR) and is also coupled directly to a transceiver bus controller chip 503 that provides a bidirectional bus driver. Automatic caller output register 505 is a 6-bit "D" type flip-flop register (DR6n). When the clock input is enabled, the data from the second output register 38 is
Strobed by ACUOR505. The data sent to both timer 507 and USART 508 in Figure 2 is sent to the second output register 3 in the state machine processor (Figure 4).
8 and transmitted via transceiver bus controller 503 and then to the addressed component. The data line to the timer component is high active and USART
The data lines are low active for the components. Since both components share the same data bus, data to one of the components must be inverted. Timer 507 is used to receive "inverted" data, i.e. 1=0 and 0=1, while USART 508
receives the conventional format. In this way, the "1" bit from the second output register 38 in the state machine processor (FIG. 4) is
Appears as a “1” bit to the USART (active low) and as a “0” bit to the timer. Transceiver bus control device 503
is a three-state device, but is not used in its third or high impedance state. It depends on the state of the RE signal generated from bit 4 of the first output control register 37 in the state machine processor.
to DOUT (data out) or DOUT
Used to drive to ROUT. register 3
When bit 4 of 7 is on, signal RE is positive and
“Activate” DIN toward DOUT. Reading information from the line adapter (other than RAM reading) is performed by a decoded GET operation, and the information read is valid on the lower eight bits of I/O bus 10. 8-1 multiplexer 504 is the source of the read information. On a “single” line adapter (Figure 2),
Four of the eight inputs to multiplexer (MUX) 504 are used by line adapters;
The remainder is used by the data link interface (DLI). V-FLD (3:2) is “11”
and V-FLD(4:1) is either equal to 0 (DLI GET) or the designated flip-flop (DESF) is on (LA GET), the multiplexer (MUX) is turned on during the GET operation. Chip selected (low level). On the "quad" line adapter card (Figure 3), there are 16 multiplexers, each with an 8-1 ratio. There are eight multiplexers for each "pair" of line adapters. 8 to MUX 504, as shown in FIG.
The input lines are 4 lines coupled to the DLI (Data Link Interface) and 4 lines connected to the DLI (Data Link Interface).
The two lines are split in half to be joined to the line adapter. Similarly in FIG. 3, in the quad line adapter, the eight input lines of each group of eight multiplexers are split in half, thereby creating four groups, similar to the single line adapter. Any group of four input lines is selected by the "designated flip-flop" (DESF (FIG. 6)) being on.
The selection of any of the four lines of any such group is performed by the two lower bits of V-FLD of the GET operation. In the line adapter (Figures 3 and 6)
The data to be “written” to RAM memory is 16
It is transmitted over the I/O bus 10 in bit+parity format. RAM in line adapter
The data “read” from memory is 16 bits +
It is placed on the MEMOUT bus 12 with parity. Component address: As shown in Figure 2,
The output of the component to be "read" is directed to the input of an 8-1 multiplexer 504 that drives I/O bus 10. There are five components on the line adapter that can be "read" by the state machine processor. These five components on the line adapter can be read: Component Requester ID (CRID) USART (508) Timer (507) Automatic Caller Status (ACUST) Adapter Type ID (ADPT.ID) and timer 50
7 is the same input line to the multiplexer
Share ROUT. One of the four inputs to any group (of the inputs to the 8-1 multiplexer)
The selection is performed by the two lower bits of V-FLD of the GET operation. V-FLD (3:4)
is equal to 11XX and the selection of one of the four inputs is determined as shown in Table Y-1.

In FIG. 2, the single line adapter multiplexer 504 causes three components on the line adapter to be written (not including RAM). They are,
Automatic calling device output register 505 (ACUOR),
USART 508 and timer 507. Addressing these three components is done in two different formats. That is, PUT
The decoding of the V-FLD of the operation and the decoding of the bits from the first output control register 37 in the state machine processor (FIG. 4). The 8-1 decoder 80p in FIG. 9 decodes the PUT operation V-FLF (4:5) equal to 01111,
And when strobe No. 2 is sent from the state machine processor, ACUOR 505 is addressed. This decoding is performed only on a single line adapter card and is sent to other line adapter cards via the front connector. This decoded signal is received by a three input NOR gate (N3, FIG. 9) in each line adapter (other inputs being a clock and designated flip-flop). The output of this gate drives the clock input of the 6-bit ACU output register. Data from the second output control register 38 (FIG. 4) is then strobed into the ACUOR 505 of FIG. In FIG. 9, decoder 80p receives as input bits 0-4 from decoder controller 23 of FIG. 4 and also receives the strobe #2 signal from state machine processor 600. When register address RA=01111,
NOR gate N3 clocks data (from register 38 in FIG. 4) into ACU output register 505. Figure 10 shows the PUT strobe,
The register address and ACUOR−CLK signal are
5 shows a timing sequence for loading the ACU-output register 505; To specify the use of the ACU-output registers for their function of transmitting dialed numbers and control signals to automatic calling device 505u, (a) state machine processor 600 accumulates dialed numbers and control signals; for that second
output control register 38 is used. (b) The state machine processor 600 performs PUT
Strobe 2 is used to set the dial number and control bits to the second output control register 38 (fourth
Initiate a PUT operation to load the data into (Figure).
The fields used are: Operation V-FLD D-FLD data PUT 01110 PUT
These fields using operations are: Operation V-FLD D-FLD PUT 01111 X001 As a result, the selected ACU-output register holds the dial number data and control data received from OCREG 20n on line 17 ₂ (FIG. 9). (d) Gate N3 in Figure 9 is CLK, DESF/ and
When activated by the signal RA = 01111, the ACU output register is set to 505 in FIG.
is clocked to pass the data onto the automatic caller. ACU output registers 505 ₀ , 505 ₁ , in FIG.
It should be understood that each of 505 ₂ , 505 ₃ can be selected to convey dialing and control data to its own automatic calling device. The second output control register 38 (FIG. 4) is given the acronym OCREG20n in FIGS. 3 and 9. Using 6 of the 8 bits of output control register 38, bit positions 0-5 are used as follows.

Table: When the OC register 38 has a “0” placed in bit positions 4:5 (i.e., starting at bit position #4,
3,2,1,0 are set to "0"), which represents the "on state" for the automatic calling device. If a "1" is placed in bit position #5, it represents an "on" state for a call request. A CRQ is a signal from a line adapter to an ACU (Automatic Calling Unit), such as an 801C, indicating that the line adapter wishes to place a call (i.e., dial a number). DPR (Next Digit Display) is a signal from the line adapter to the ACU in response to the PND (Next Digit Display) signal from the ACU shown in FIG. This is NB1−
This means that the data at NB8 is one of the dialed numbers. The RS-232 electrical interface (EI) allows many different formats and types of data sets (modulation/demodulation circuits) to be connected. Some of these modem circuits have extra or special functions that can be controlled via the electrical interface. For example, the Western Electric 201-A data set is
The 202C/D data set contains the signal-NS.
Including the "Supervised Transmission Data" signal -SA, the 811-B data set has the "EOT detected" signal ED (End of Transmission Detection). To take advantage of several active lines on the interface between the line adapter and the electrical interface (EI), these lines are dually used to control these “special function” signals. It's here. In this way, the logic circuit
The lines located and present on the EI card (CRQ and NB1) were used to provide control functions. Jumpers were used to connect the "special control" functions to the appropriate pins on the junction cable. When CRQ is “off”, this means that no dialing is being done, so the NBn line is valid for use, and the firmware in the state machine processor controls the logic as desired. It represents a waxy state. Special control function signals NS, SA, ED are shown below for several data sets. The Bell Telephone Co. manual is NS,
Helpful for detailed usage of SA and ED signals. For some data sets, ACU-output register 505 is used as a "special control" function. By maintaining the OC register 38 (FIG. 4) so that bit position #5 is off (="0") and controlling bit position #0, the control that directs the data set is turned on or off. Switched off. This "special control" function is jumpered to one of the signals listed below on the electrical interface card and provides the following functionality: Signal Function Dataset NS New Synchronization 201 SA Reverse Channel Transmission 202 ED Immediate Disconnect 811-B Thus, in operational terms the special control functions can be summarized as follows. (a) Bit position #0 of the OC-register 38 is
Can be loaded via the strobe #2 signal to read a “0” (=off) or “1” (=on). This is accomplished by the following instruction fields. Operation V-FLD D-FLD data PUT 01110 X001 XX0n n is “0” or “1” (b) ACU-output register (505, Figure 9) is
Loaded (with data present in second output control register 38) by the following instruction field: Operation V-FLD D-FLD PUT 01111 X001 (c) In this state, if OC-register 3
If bit position #0 of 8 were to hold a "1", then the "special function" control signal would be in the "on" state. If bit position #0 were to hold a "0", then the "special function" control signal would be in the "off" state. Chip selection: on the specified line adapter
Addressing the SART or timer is
This is the same as "chip selection" of components. This is accomplished by bits 0 and 1 of the first output control register 37 in the state machine processor, along with a designated flip-flop (FIG. 5) in the line adapter. Each line adapter has its own UCS (USART chip selection) or TCS (timer chip selection).
"AND" the designated flip-flop with bits 0 and 1 to bring to the USART or timer. Bit 0 in first output control register 37
The use of and 1 is as follows.

[Table] The remaining bits of register 37 are mainly USART
and used as a control signal for timers. Random Access Memory (550, Figure 6): Each data communication line has 2048 words of RAM available for its use. One word is equal to 16 data bits + 1 parity bit. In FIG. 6, RAM chip 55
0m is a 4096 x 1 bit static RAM with a read access time of 180 nanoseconds,
It consists of 17 chips to create 4096 words. On the DLI/LA card, 2048 words are for a “single” line adapter;
Word is Data Link Interface (DLI)
It is for. The "quadruple" line adapter card (FIG. 3) provides 34 memory chips or 8192 words, 2048 of which are valid for each line. Data communication line adapter memory (for any of the lines) is MADDR (15:5) equal to 01110
is "designated" by a memory address line. This is illustrated in Figure 6 which shows the data link interface/line adapter RAM 550m. The 5-bit comparator 100c on the DLI/LA card compares (i) for the DLI memory selection (for the "equal to"condition); or (for the "greater than" condition (MADDRnn01110)); ii) Compare against line adapter RAM selections such as 550m ₁ or 550m ₂ . The signal "RARAMSEL" (line adapter RAM selection) is sent to all line adapter cards via the front cable to select the "designated" line adapter RAM memory. Moshiro memory address line MADDR (15:
5) is equal to 0111x (DLI or LA selection), the slow memory flip-flop (SLMF)
100sf will be set equal to 1. Output of flip-flop 100sf (Figure 6)
whose output goes to the state machine processor
WAIT/Drives the open collector NAND gate connected to the front signal line. When low, this signal (WAIT/) forces the state machine processor into a "wait" state until the signal goes high. The use of a RAM chip with a read access time of 180 nanoseconds requires the state machine processor to wait one clock period, thereby reducing the
SLMF (slow memory flip-flop) is turned “on” for one clock when either the
and is then toggled off. Selection of 550m of RAM memory on the DLI/LA card is done via MADDR(15:5) equal to 01110 or if MADDR(15:5)
01111, and if the specified flip-flop is on, then the specified line adapter
RAM is selected. This logic controls the chip select inputs on the RAM chips. RAM selection for DLI or line adapter memory is
This is handled by controlling the "A-11" address pin on the RAM chip. Figure 6 shows
Each RAM in the system as having its own A-11 input from its own DESF
A typical setup for If
If MADDR(15:5) is equal to 01111 and the line adapter designation flip-flop (DESF) is on, the particular RAM is chip selected and the A-11 address input is true. The “quadruple” line adapter card (Figure 3) has two
two groups of memory chips (550m ₁ , 55
0m ₂ ), where data communication (DC) lines 0 and 1 on the card share the same group of RAM chips, and data communication lines 2 and 3 share the same group of RAM chips.
share other groups of RAM chips. Signal LARAMSEL (line adapter RAM selection, 6th
(Fig.) is communicated to all line adapters and then effectively ANDed with the appropriate specified state to cause the desired RAM group to be chip selected.
1st or 2nd on a “quadruple” line adapter
The “partition” of RAM for data communication lines is
“A-11” address pin (6th
(Fig.) (signal DESn with n=1) and for the third and fourth lines, the “A-11” pins on the second group of RAM chips are , DESn with n=3 (Figure 6)
controlled by. A "dual" line adapter contains only one group of memory chips 17 and operates similarly to line 0 and line 1 on a quad line adapter. The data to be written to RAM must be placed on the I/O bus 10 by the state machine processor, and the "read data"
MEMOUTnn bus 12 (nn equals 00-16)
is sent to the state machine processor above. Clear: There are two clear methods used to clear a line adapter. Namely, these are "power up" clear and "designated" clear. Power Up Clear is a signal generated during a power up sequence for the cabinet housing the line adapter. This signal is transmitted from the back of the main module cabinet and is active low. Directed clearing is a function controlled by the state machine processor, and only designated line adapters can be cleared. The clear signal is the first signal in the state machine processor (Figure 4).
is generated from bit 7 of the output control register 37. The "power up" clear operates to clear three components on the line adapter. These are the designated flip-flop, autocall output register, and USART. The "designated" clear signal clears two components on the line adapter. These are the automatic calling unit output register (ACUOR) and the USART. USART Configuration and Operation: The USART is housed in a 40-pin dual inline package.
It is a MOS/LSI device and is TLL compatible on all inputs and outputs. USART performs the function of interfacing "serial" data communication channels to parallel digital systems, and is capable of full-duplex communication with synchronous or asynchronous systems. One preferred embodiment of USART is Western
Digital Corporation (3128 Redhill Avenue,
Model UC1671 Asynchronous/Synchronous Receiver/
The transmitter is designated as a transmitter and is described in the August 1978 Technical Data publication including a block diagram showing the various registers, controls and components briefly described below. (i) Receiver Register (RR): This is an 8-bit shift register that inputs received data at a clock rate determined by an internal control register. The incoming data is organized into selected characters in length and then transferred to the receiver holding registers, filling unused upper bit positions with logic zeros. At this time, the INTR (interrupt) output is activated to inform the state machine processor (600, FIG. 4) that the receiver holding registers contain valid data. (ii) Receiver Holding Register (RHR): This is an 8-bit parallel register that provides the configured receiver character to the DAL (Data Access Line) bus line (Figure 3) when requested through a read operation. It is a buffer register. (iii) Comparator: An 8-bit comparator is used in synchronous mode to compare the configured contents of the receiver register and the SYN or DLE register. "Matching" between registers sets up a strip of received characters (when programmed) by preventing data from being loaded into the receiver holding registers. A bit in the internal status register is set after the strip is complete. The comparator output also allows character synchronization of the receiver for two consecutive matches with the SYN register. (iv) SYN register: This is set by a write operation.
An 8-bit register loaded from the DAL (Data Access Line) line (Figure 3) that holds the synchronization code used to establish receiver character synchronization. It operates as a fill character when there is no new data available in the transmitter holding register during the transmission period. This register cannot be read on the DAL line. It must be loaded with logic zeros in all unused high order bits. (v) DLE register: This is
An 8-bit register loaded from the DAL line that holds the “DLE” character used in the transparent mode of operation; filled with a combination of Additionally, the USART is programmed to force a single DLE character to precede any data character transmission during "transmitter transparent mode." (vi) Transmitter Holding Register (THR): This is an 8-bit parallel buffer register that holds parallel transmission data transferred from the DAL line by write operations. This data is transferred to the transmitter register (TR) when the transmitter section is enabled and the transmitter register is capable of transmitting new data. During this transfer,
A signal interrupt (INTR) is activated to inform the line support processor that the transmitter holding register is empty. (vii) Transmitter Register: This is an 8-bit shift register loaded from the THR (Transmitter Holding Register), SYN register, or DLE register. The purpose of this register is to serialize the data and provide it to the transmitted data output line. (viii) Control register: USART contains mode selection,
There are two 8-bit control registers CR1 and CR2 that hold device program signals such as clock selection, interface signal control, and data format. Each of the control registers can be loaded from the data access line (DAL) by a write operation or read onto the DAL line by a read operation. By designation, "CR16" represents bit 6 of control register 1. "CR23" represents bit 3 of control register 2. (ix) Status Register: This is an 8-bit register that holds information based on communication errors, interface data register status, matching character status, and communication device status. This register is readable on the DAL line by a read operation. (x) Data Access Line (DAL): The DAL is an 8-bit bidirectional bus port through which all address, data, control, and state transfers occur. In addition to transferring data and control words, DAL lines also transfer information regarding device addressing, read and write requests, and interrupt information. Operation of the USART for byte-oriented line adapters: Asynchronous mode: The framing of an asynchronous character is by a start bit (logic low) at the beginning of the character and by one or more stop bits (logic high) at the "end" of the character. It will be provided accordingly. Reception of the character begins upon recognition of the first start bit by a positive transition of the receiver clock immediately after the previous stop bit. The start and stop bits are "stripped off" while assembling the serial bit input into parallel characters. Character assembly is completed by receiving a stop bit after the last character bit is received. If this bit is logic high, the character is determined to have the "correct" framing and the USART is prepared to receive the next character. If the stop bit is logic low, the framing error condition flag is set and the receiver assumes this bit is the start bit of the next character. If the input is still logic low when sampled at the theoretical center of the inferred start bit, then
Character assembly continues from this point. If the receiver's input is a "space" (i.e. receives more spaces than marks), then all zero characters are assembled and the error flag and data receive interrupt are set so that line breaks can be determined. occurs in After all the 0 characters are assembled with the 0 in the stop bit position, the first received logic high is determined as the stop bit, and this makes the receiver circuit ``ready'' for the assembly of the next character. ”Reset to state. In asynchronous mode, character transmission occurs when the information contained in the THR (transmitter holding register) is transferred to the TR (transmitter register). The transmission is initiated by the insertion of a start bit, which, once activated, is followed by the serial output of the characters with parity (least significant bit first), followed by the most significant bit, 1-,
There is insertion of a 1.5- or 2-bit long stop condition. If the THR (Transmitter Holding Register) is filled, the next character transmission begins after the transmission of the current character's stop bit in the TR (Transmitter Register). Otherwise, “mark” (logic high)
Status is transmitted continuously until the THR (Transmitter Holding Register) is loaded. Synchronous Messages: Message synchronization is performed by a special synchronization character code (SYN) sent at the beginning of a block of characters. When the receiver is activated,
Examine two consecutive characters that match the pattern of bits contained in the SYN register. During the period the receiver is investigating, the data is
It is not transferred to THR (transmitter holding register),
The status bits are then not updated and no receiver interrupts are activated. After detection of the first SYN character, the receiver transmits subsequent bits whose length is
Assembles into a character determined by the contents of the USART internal control registers. If after the detection of the first SYN character, the second SYN
If the character is present, the receiver will enter synchronous mode until the receiver enable bit goes "off". If a second consecutive SYN character is not found, then the receiver returns to search mode. In synchronous mode, the transmitter is activated once a continuous stream of characters has been transmitted. If the THR (transmitter holding register)
If the transmitter register is not loaded when it completes transmitting a character, this “idle”
The time is filled by the transmission of the characters contained in the SYN register in non-transparent mode,
or (in transparent mode of operation) DLE
and the characters contained in the SYN register, respectively. Receive operation: Receiver data input is provided by the 1X receiver clock from the modem data set.
or locked into the receiver register by a local 32X bit transmission rate clock (asynchronous) selected from one of four timer chips. When using a 1X receiver clock, receiver data is sampled on positive transitions of the clock in synchronous mode. When using a 32X clock in asynchronous mode, the receive sampling clock is phase-adjusted to the “mark-space” transition of the received data start bit and (through clock counting) defines the center of each received data at the transition of . When a complete character is shifted into the receiver register, it is transferred to the RHR (receiver holding register) and the unused higher order bits are filled with zeros. At this time, the “receiver status bits” (framing error/sync detection, parity error/DLE detection, overrun error, and data received) are updated in the status register, and the data receive “interrupt” is will be activated. During the period when the receiver parity check is "enabled" in the internal control register, parity errors are set if found. An overrun error is set if this data receive status bit is not cleared via a read operation by an external device when a new character is ready to be transferred to the RHR (Receive Hold Register).
This error flag indicates that the character has been lost, ie the new data has been lost, and the old data and its status flag have been saved. assembled in receiver registers;
Characters that match the contents of the SYN or DLE registers are not loaded into the RHR (receiver holding register), and if the USART
Bit 3 of control register 2 (CR23 = SYN strip) or USART control register 1 (CR14
If bit 4 of each DLE strip is set, no DR (data receive) interrupt will occur. The SYN-DET and DLE-DET status bits are set by the next non-SYN or DLE character. The DLE-SYN combination is stripped when control register bits CR23 and CR14 are both set (transparent mode). SYN comparisons are only made with characters received after the DLE character. If two consecutive DLE characters are received, only the first DLE character is stripped. No parity check is performed in this mode. Transmitter operation: information is transmitted by write operation
Transferred to THR (transmitter holding register). Information can be loaded into this THR at any time, even when the transmitter is not activated.
Transmission of data is only initiated when the Send Request bit is set to a logic ``1'' in the USART control register and the Send Clear input is logic ``low''. Information is typically transferred from the THR to the transmitter register when the transmitter register completes transmitting a character. However, the information in the DLE register is
If the forced DLE signal state is activated (CR15=forced, DLE and CR16=TX transparent and set to logic "1"), it is transferred ahead of the information contained in THR. Control bit CR15 is used to ensure that the DLE character is forced prior to the transmission of the data character.
It must be "set" prior to loading a new character in THR.
The transmitter register output is passed through a flip-flop that delays the output by one clock period. generated by the modulation and demodulation data set.
When using a 1X clock, the output data changes state on negative clock transitions and the delay is one bit period. Transmit “interrupt” when transmitter is activated
occurs every time THR is empty. If THR is empty when the transmitter register is ready to receive a new character, the transmitter is “idle”.
enter the state. During this idle period, a logic high is applied to the transmitted data output in asynchronous mode, or the contents of the SYN register is set to synchronous non-transparent mode (CR16 = 0).
given in. In synchronous transmission transparent mode (enabled by USART control register 1 = logic 1), idle states are
Fulfilled by DLE-SYN character transmission. When entering transparent mode, filling of DLE-SYN does not occur until the first forced DLE. If the transmitter section is disabled by resetting the request-to-send signal (RTS), any partially transmitted character
The USART transmit section is completed before being disabled. As soon as the CTS signal (transmit clear) goes high, the transmitted data output goes high. When transmit parity is enabled, the selected odd or even parity bit is inserted into the last bit of the character instead of the last bit of the transmitter register. This limits the transfer of character information to a maximum of 7 bits plus parity or 8 bits without parity. Parity cannot be enabled in synchronous transparent mode. USART Input/Output Operation: All data, control and status words are located in the DLA of Figure 3.
The data access line (DAL0
-7). Additional input lines provide control for addressing specific units and coordinating all input and output operations. For other lines, the input operation is
Provides interrupt capability to indicate to the controller what is required by the USART. All input/output related terms are referred to with respect to bus controller transceiver 503 in FIG. “Write” or output from transceiver 503 on the DAL line and USART
Place data within. Inputs/
Output-related terminology is referred to with respect to bus controller transceiver 503. (i) Read: A read operation is initiated by bus controller 503 of FIG. 3 by placing an 8-bit address from state machine processor 600 on the DAL. When the chip select signal goes to logic “low” state (CS/, Figure 6),
USART (508) transfers bits 7-3 of DAL to its wired ID code (USART pins 17, 2).
2, 24, 25, 26 above) and selected in the "matching" state.
The USART sets its RPLY line low, recognizes the read, and transfers the data. Bits 2-0 of the address are used to select which USART register to "read" as follows. Table Y-3 Bit 2-0 USART Selected Register 000 Control Register 1 010 Control Register 2 100 Status Register 110 Receiver Holding Register The readable (RE) input line of the USART is selected by the state machine processor 600. When set to “low” state,
The USART reads the contents of the addressed register.
Gate output on DAL bus. The read operation is completed, and the device becomes unselected.
Chip select and read enable both return to logic high states. Reading the receiver holding register clears the DR (data receive) status bit. Bit 0 must be logic low for read or write operations. (ii) Write: A write operation is initiated by forcing the chip select input to a logic low state. Bits 2-0 of the address are used to select the USART register to be written to as follows. Table Y-4 Bits 2-0 USART Selected Register 000 Control Register 1 010 Control Register 2 100 SYN and DLE Registers 110 Transmitter Holding Register Write Enable (WE) line is set to logic “low” state by state machine. When set to , USART gates data from transceiver 503 onto the DAL bus and into the addressed register. If data is written to the transmitter holding register (THR), the THRE (THR blank) status bit is cleared to logic 0. A "100" address loads both the SYN and DLE registers. After writing to the SYN register, if followed by another write pulse with a "100" address, the device is conditioned to write to the DLE register. Any intervening read or write operation with another address will reset this state such that the next "100" addresses the SYN register. (iii) Interrupt: The following conditions will generate an interrupt. 1 Received Data (DR) - indicates the transfer of new characters to the receiver holding register (RHR) during the period when the receiver is activated. 2 Blank space in transmitter holding register (THRE)...
Indicates that the THR register is blank while the transmitter is enabled. If the transmitter is activated while a "blank" THR is present, or after the character has been transferred to the transmitter register, a first interrupt occurs, thus creating a THR blank. 3 Carrier on…This means that DTR is “on”
Indicates that the carrier detection input is “low” when (DTR = data terminal ready). 4 Carrier off...Indicates that the carrier detection input is "high" when DTR is "on". 5 DSR on...Indicates that the data set ready input is "low" when DTR is "on". 6 DSR off...Indicates that the data set ready input is "high" when DTR is "on". 7 Ring on…Indicates that the ring display input is “low” when DTR is off. Whenever an interrupt condition exists, the
The INTR output is pulled logic low. The state machine then selects CS (chip select) and
Acknowledge the interrupt request by setting the interrupt acknowledge input (IACK) to the USART to a “low” state, otherwise the interrupt state (INTR)
is never reset. Automatic Calling Operation: (Operation Using 801 Automatic Calling Device) The 801ACU has a 4-bit interface that receives the digits of the calling number to be dialed. This interface complies with EIA standard RS−
366 and includes the following signals: Table Y-5 Call request CRQ Data line occupancy DLO Next digit display PND digit display DPR Data set status DSS Call abort and retry ACR NB8 digit NB4 〃 NB2 〃 NB1 〃 The dialing sequence shown in Figure 8 is as follows. works. The line adapter turns CRQ "on" if DLO is "off". After the detection of the dial tone performed by the 801, the digits are transferred to the 801 one at a time. The 801 converts the digits into a signal that replicates the function of a rotary dial pulse or touch tone frequency compatible signal. These signals are transmitted to the telephone line. Upon completion of reading, DSS
is "on", meaning that an answer tone from the called data set is received. Receipt of the DSS causes the line to be transferred to the associated data set in the ACU. If DSS is turned "on", the call abort and retry (ACR) timer begins timing. With pulse dialing, a typical decimal number takes 15 seconds to dial, and touch-tone dialing the same digit requires almost 1 second. The response sequence often begins after the last digit is transmitted by 801. Interface Operation (Data Communication Line Adapter/State Machine): The UIO data communication line adapter is an application dependent device controlled by the UIO state machine processor 600. Two basic types of line adapters are available. That is, there are "character-oriented" line adapters and "bit-oriented" line adapters, each of which has a different electrical interface to the data communication line. One to eight line adapters can be individually serviced by one state machine processor. Each line adapter includes components that are addressable and serviced by a state machine processor with PUT or GET instructions. Components on a line adapter are, in some cases, serviced with one or a series of instructions that provide sequential control of the components. The “communication” between the state machine processor and the line adapter is
Separated into two basic groups. (i) Not specified. (ii) Specified “unspecified” behavior does not require that the line adapter be specified to execute these instructions. A "designated" type of operation requires that the line adapter be designated or "identified" to execute these instructions or series of instructions. In addition to requiring line adapters to be “specified,” the following behaviors (excluding ACUOR)
uses the first control register 37 in state machine processor 600 for the purpose of controlling components on the line adapter. Except for the clear operation, all other operations are a series of PUT/GET operations that provide the necessary sequential control. The “data” output to the line adapter for these operations is sent to the second state machine in Figure 4.
is generated from the output control register 38 of. The bits in the first output control register 37 of the state machine (FIG. 4) are configured for the following control functions. Table Y-6 (Output Control Register Bits for First Control Register 37) Bit Signal 0 UCS...USART Chip Select This bit must be "1" when the USART requests chip selection. 1 TCS...Timer Chip Selection This bit must be ``1'' when the program timer/baud rate generator requests chip selection. 2 IACKI...Interrupt Acknowledge Input This bit must be ``0'' to acknowledge an interrupt from the specified and chip-selected USART. 3 WE…Writable This bit must be set to “0” to enable writing to the USART or timer.
Must. 4 RE...Readable This bit is set to “0” to enable reading from the USART or timer.
Must. 5, 6 A0, A1... Address bits 0 or 1 These two bits select registers inside the timer. 7 CLR...Clear This bit must be ``1'' to give a clear to the line adapter. Read and Write System Procedures for USART Regarding (i) Read and (ii) Write sections above,
USART read procedure is “USART configuration and calculation”
The USART data register, mentioned above under the heading
Used when reading status or control registers. Thus, in (i) reading procedure, the following series of operations occur. (a) Data calculation V-FLD D-FLD (Hexadecimal