JPH0480574B2 - - Google Patents

Description

[Detailed description of the invention]

(Industrial Application Field) The present invention is a “data highway”
The axial cable or equivalent means
Numerous distributed individual “drops” that serve as transmission/transmission locations.
A process control system for factories that connects
related to the system. More specifically, the present invention
local data collection and control processes installed on the
Such a process control system with relaxed memory requirements on the
Related to the stem. (Conventional technology) In various technical fields, year after year, various operations in factories have been improved.
Control is becoming increasingly complex. Steel manufacturing, hydrocarbons
subject to automatic control such as chemical processing, power generation, etc.
There are many types of industrial processes available. Increasing complexity
together with various new technologies for process control systems.
Demand is being created. Examples of these demands include;
Improving data processing ability, improving data acquisition ability,
of the ability to control the interaction of the dynamic variables of a given process.
improvement, response time reduction, etc. these demands
As much as possible, rely on experienced operators to meet
to ensure that the system is almost error-free.
Needless to say, it is desirable to maintain it as a system.
not. The control system is adjusted according to the scale of the factory to be controlled.
The system allows the stem to “grow” and the system by which this growth is provided.
Expandable system so as not to limit the nature of your operation.
It is also desirable that it is a stem. Also, hardware
i.e. without changing the microcontroller
Various works can be done simply by reprogramming the controller means.
We aim to provide control systems that can respond to
is desirable. Furthermore, when providing such a control system,
Various prepackaged units as modules
Easy system assembly from start to finish, and
It is also desirable to provide a means to reduce design effort as much as possible.
Delicious. Regarding conventional technology, various process control systems
The system interfaces with local data acquisition and control equipment.
using a central or “host” computer that
use Avoid such approaches and use traditional
The system uses information provided by the host computer.
provided at the location of various physical subcomponents of
This may cause one of these lower components to malfunction.
The system and overall operation will not be stopped even if the
It is desirable to configure the system so that it is easy to use. process control system to host computer
There are several reasons why it should be excluded. Sky
The most important reason is to use a host computer.
If the system is already qualified and complied with before installation,
For example, a host computer and various controlled
The exact configuration of the communication relationship between
This will result in Naturally, the above
There is no need to limit the number of modules in advance.
In addition to providing a system that is
Automatic control of certain controlled processes is required.
It is also desirable to provide a system that can be expanded upon.
Delicious. If possible, configure your system
transmission of various messages between various subsystems
There is a need for flexibility that allows
Not even. For example, in a process control system
pressure and temperature at critical points in the process.
Being able to monitor variable values almost continuously
is necessary. What data communication channel
However, there is a limit to the amount of information that can be transmitted.
There is a limit. However, especially as it grows over time
In such a system, how many processes
Specify whether variable values must be constantly monitored.
It is impossible to determine exactly in advance. There
, some variable values are repeated throughout the system.
In a distributed process control system
other than variable values that require continuous monitoring.
data from a processor, e.g.
A communication method that allows transmission only when requested by
must be provided. Communication between operators
Download the program to the acquisition unit and control unit
Functions that are required non-regularly, such as actions to perform
It is also necessary to be able to achieve this without establishing a separate communication path.
It is. In addition, each droplet of the distributed process control system
Even if a program uses only a certain number of variable values,
Any drop in the stem that normally
A professional, regardless of whether Tup is interested in
For access variable values, if necessary, e.g.
Enable notification of server warning status, etc.
It is also necessary to provide the means. message
Central control that must be transmitted to a specific address
This is extremely difficult to achieve in a system
It is. Other important attributes of distributed process control systems
This simplifies communication, i.e., eliminates complicated wiring or
There is a point where multiple conductors are not required. system
Use a single conductor to connect all units in the
and without any changes to your existing system
Preferably, additional units can be added. Connecting parts of a distributed data processing system
Cables of various designs are known. Typical
Cables carry multiple signals simultaneously in parallel
It is a flat multi-wire cable. single
Use shielded cables, which
A system such as a coaxial cable that transmits signals sequentially.
Single wire terminations are also used. It's easy
It also protects the system from noise.
It can also be expected to have a shielding effect, which is an important means of
The latter is preferred. However, this kind of cable
square wave data bits due to the effective capacitance of
“curls” during transmission. Therefore, this “round”
"Natsuta" to reliably detect data transmission signals
A more complex error checking device is preferably used.
Reduce error rates to extremely low levels where they are no longer necessary
It is desirable to provide a means to lower the Typical conventional interconnected process control system
In most cases, as mentioned above, the center or
A host computer is used. like this
One of the functions performed by a computer is
providing a synchronization or clock signal.
As mentioned above, even if the host computer is removed, the system remains
Stem timing control is necessary. if you can
No separate timing signal line or special timing
It also uses timing signal decoding equipment and timing signal processing equipment.
It is desirable to perform the above timing control without using
Yes. In a distributed data processing system, the system
for information to connect the various subunits of the
It is known to provide redundant paths for this purpose. typical
As an example, one wire is used as the first pass, and the other wire is used as the first pass.
By setting it as the second path, if the first path
If a failure is discovered in the path, the second path is operated.
This method has several drawbacks. One of them is
Many of the events that cause failures in the first path occur in the second path.
This method often causes failures in the
The formula does not provide any guarantees.
It is. The second drawback is that the first pulse may fail.
Before this occurs, the device has already malfunctioned.
Also, the second pass is not tested. In addition, the switching structure
Depending on the configuration, the message will disappear during the switching period.
It is possible. Naturally, something like this
If a redundant transmission path scheme can be improved, it should be implemented.
It is desirable that the Also, while avoiding the use of repeaters and amplifiers,
Moreover, it is possible to avoid the accompanying deterioration in reliability and economic efficiency.
It is desirable to communicate using a single-wire cable so that
Delicious. (Problem to be Solved by the Invention) The present invention solves the problem in that one data highway bus
Multiple drops that are more data receiving/transmitting locations
In a process control system connected to
data highway bus.
data highway processor that sends and receives data
and stations in multiple system elements for each drop.
Functional processes that perform partial data collection and control operations
Data Highway Processor and Functions
connected between the processor and the data between them.
data transmission and reception while maintaining the independence of each processor.
Configured with dual port memory
and each data message
An identifier part that identifies the system element to which the page is associated.
information about the status of the minutes and associated system elements.
Include a status part with information, and
Other data received by the data highway processor
Data messages from drop system elements
This data message is analyzed by analyzing the identifier part of the message.
of the local control operations of the relevant functional processor.
Determine whether or not the received data is necessary.
Analyze the status part of the message and check the related system
Determine whether an alarm condition exists on a system element
and a status indicating that an alarm condition exists.
data message with a
Information from system elements in related functional processes
regardless of whether it is necessary for the local control operation of the
so that the functional processor can selectively access it.
by sending it to dual port memory.
The functional processor is the data highway processor.
The status of all data messages received by the
Eliminates the need to analyze task and alarm information
This is intended to ease memory requirements. In general, the present invention
single coaxial cable or equivalent optical cable
The fiber is a means of controlling processes,
process-related variable values or parameters during the process.
a means of measuring data, an operator or substitute;
interface with computer systems
Connect individual drops consisting of means to provide
Related to subsequent distributed process control systems. de
Multiple processors are provided for each
Ru. Generally one processor is used for data high
the remaining processors locally
Performs essential control functions. These processors are
communicate with each other through dual port memory for
do. The data highway is used in mixed mode.
time-division multiplexing over some time.
(TDM) method and continuous monitoring during this time.
Data about variable values that require data in each drawer.
Data that can be accessed from a drop to other drops.
It can be output sequentially to the highway.
Ru. For the rest of the time the highway is called
Used in democratic mode and at this time
Every drop leads to the data highway
Additional data or messages can be output. stomach
Even in different modes, all messages are sent via the bus.
transmitted via. That is, all drops are
access to all messages on the data highway.
can be accessed. Individual messages are
other drops often contain information about
Analyze this data by analyzing the information.
Because each drop has dedicated processor memory
Decide whether to copy or not. Any one
output to the data highway with two drops
Each message sent is sent to the next device that accesses the bus.
Contains a “token” that represents a drop. The distributed process control system of the present invention
used in the code. In the first mode, the drop is connected.
If the connecting cable is used in time division multiplexing (TDM)
used. on each drop every 100 milliseconds.
given time “slot”(s).
In this time slot, each drop is
Information can be output to the bus. child
When any other drop is needed, this
Information can be retrieved. As a matter of course,
In addition to the time-division multiplexing operation, the entire bus itself
Even physical functions can be synchronized extremely reliably.
The provision of a timing device is a prerequisite.
At least one of the drops is time division multiplexed on the bus.
In the slot of the system operating part,
to the data highway.
This is a “time keeper” drop that is output. Ta
Each drop, including the im-keeper, is equipped with this system.
Copy time and synchronize the behavior of each drop itself
and to communicate with other drops.
Use this system time for this purpose. of the present invention
In a particularly preferred embodiment, the timekeeper drop
There are three drops, which are detected by these drops.
The average of the two closest times is the system data
This is the value used as the time. This fixed
By setting the system time reference, the clock signal line
Perform time division multiplexing without separately installing
I can do it. Because time is treated as data,
In this sense, data transmission itself is self-locking.
It becomes gu. The system uses the same bus and the same manner as regular data.
system timing information.
interface for receiving timing data.
It is necessary to separately install an ace means in the local controller.
Because there is no system, it is easier to control the system. Also,
No separate control lines or separate timing unit required.
be. Therefore, the system timing information
By treating the host computer in the same way,
The timing functions provided by
Incorporated into the part drop function. three time keys
The super drop also works if the bus has an operating sequence.
restarts the bus when a bus error occurs. In TDM mode, the drop is continuously monitored
for a given data on a process variable value that requires
Output data and enter democratic mode.
As such, the drops are not data that is transmitted non-repetitively.
You can make inquiries regarding data items.
Therefore, all databases of the system are
Drops are available. That is, which drop
also access and copy all data items
be able to. For distributed databases
instant transparent access to the distributed program of the present invention.
process control system occurs elsewhere in the system.
A control loop that utilizes process values can be
It can be executed in a loop. Also, this
Transparent databases are typically hosted on a single host.
A large number of independent functions that are performed by computers.
Allows for distribution in vertical drops. Each doro
Tups operate in parallel and allocate without interruption
Because you can concentrate on the function that is being
Even if this occurs, system performance will not deteriorate.
stomach. Data hacking in democratic mode
CRT graphic display update and control module using iway
loop processing, alarm notification, progress data collection and operation.
All functions such as printing of work logs are
When the field is in a chaotic state, it is as fast as under steady state.
Respond quickly. In a preferred embodiment, each drop has at least
accessing the highway every 100 milliseconds,
In addition to the message's unit identifier, this drop's
Broadcasting process values stored in memory
I can do it. On the other hand, each drop
Broadcasts from other drops about Seth Points
If necessary, remove each vehicle from the highway.
Store in the memory belonging to the drop. all
Process variable values are broadcast at least once every second
However, each drop only hits once every 100 milliseconds.
Drops can be accessed if
Keep Pro once every 100 milliseconds if conditions permit.
process variable values can be broadcast and updated. good
In a preferred embodiment, the highway speed is 2 megabaud.
Therefore, a system of at least 10000 points per second is required.
Stem broadcast speed is obtained. With this broadcasting technology,
Transmission and confirmation methods often used in the known art.
There is also no high overhead associated with authentication messages.
Master or Traffic Director
Not necessary. Rather, each drop is temporarily mastered.
functions as a token-passing technology and uses token-passing technology to
The next drop on the
give access. Finally, at the end of each broadcast cycle
for the remainder of each 100 millisecond cycle.
Other communications as necessary, e.g. program downloads.
downloading, transfer of English description of each point.
It can be used for any purpose. There are two types of data transmitted on the data highway.
Biphase coding is used,
In the preferred embodiment, each drop's phase lock
The received two-phase pulse is transferred to a small lower unit using a loop circuit.
subunits and weight these subunits.
on the data highway by analyzing
Detect pulses correctly. Each local drop and data highway
A communication interface device that establishes a connection between
Some have redundant interfaces as well as data highways.
It may also be provided as a turf ace. communication interface
Both face messages on the highway
Explore and fix errors built into each message.
After analyzing the correct code, the message was received correctly.
When it is determined that the information was received, the communication processor
In the past, there was a sign that indicated “correct message reception”.
send the issue. As a result, the processor first
Communication equipment that provides a “correct message reception” signal
Retrieve the message from the device. Therefore, communication equipment also
The data highway is also always online.
Switching between main and subordinate communication devices, etc.
At least you get redundancy. (Example) The present invention will be described in detail below with reference to the attached drawings.
do. Table of Contents 1 System Overview 2 Communication Format 3 Drop Overview 4 Message Format 5 Data Encoding and Decoding 6 Clock Control - Overview 7 Data Highway Controller A Data Highway Processor (MBD) B Data Highway Communication Card (MBC) C Shared Memory (MBS) 8 Data Highway Processor Operation A TDM Mode Message Generation B Democratic Mode Message Generation C Organizing Received Messages 9 Clock Control - Detailed Discussion 10 Bus Allocation 11 Control Fields 12 Alarm Handling 13 Shared Memory Configuration 1 System Overview As mentioned above, the main objective of the present invention is to
Data highways provide various input/output terminal devices, data
Acquisition unit, control device, record keeping device, error and
alarm indicators, and other data processing systems.
A distributed process control system that connects all communication means.
The purpose is to provide a stem. Figure 1 shows the present invention.
We present an overview of such a system based on single de
For example, the data highway 10 may be a process control device.
12, input/output terminal device 14, sensor 16, control
Connect various input/output devices such as display device 18, etc.
It continues. In detail, the present invention will be described later.
is the various input/output for data highway 10.
is called a “drop”. all drops are
Not all of them are the same on the data highway
Although it does not use properties, it is almost exactly the same mode.
interact with the data highway. Therefore,
The system of the present invention is a modular system.
I can think. In other words, regardless of type or number
This is because drops can be added arbitrarily. preferred
In some embodiments, up to 254 different drops can be used.
Can be used. Both of these drops are system
access all databases of
The base is copied or copied to memory belonging to each drop.
are memorized and each drop can be exchanged with each other as needed.
You can also believe. This allows maximum flexibility
is obtained, avoiding the use of a single host computer
can be done. As mentioned above, this can vary
This is desirable for reasons of
If a computer fails, the entire system will stop working.
For example, one or more drops
Can the system continue its operation even if the system fails?
is also one of the reasons. All drops are mutual
Because each part of the system can communicate with
It can provide input and output to groups such as
Additionally, the mixed mode usage of highways described below
Conventionally, this function is a function of the host computer.
Ivy program download, status signal
A drone configured as an operator terminal device for forming etc.
run without interrupting system functionality.
can be administered. Complete “data transparency”
achieved. That is, each processor
central memory by “searching” the memory of
can be configured according to the operator's wishes.
It provides an extremely fast cathode ray tube display with
Allows flexibility in the choice of Ram language. Figure 2 shows the distributed process control system of the present invention.
FIG. perform various functions
Multiple drops configured as
They are connected by way 10. each drop
contains a processor to perform these functions.
nothing. However, the processor mentioned here is the drop location.
refers to the hardware and software that
connected to the highway through appropriate means. P
The Rosetsusa performs data acquisition and control functions, e.g.
various processes within the factory under control 22 and inputs.
Turf Ace Distributed Processing Units
20. batch processing
A processing unit 24 can also be used. for operator
Alarm console 26 is for the operator
Cathode ray tube control display/alarm console
Work as. Operator alarm console
system functions as needed.
Engineer console 2 to program
8 can be used. Information that occurs during production
An automatic data recorder 30 for recording information may also be installed.
I can do it. How long did it take to record this data?
A storage/retrieval means 32 can be used. de
For example, one of the ropes is to optimize factory work conditions.
It also includes a computer function 34 for special calculations needed to
be able to. Transfer one drop to another computer
A “gateway” that interfaces with
remote location via telephone line.
Another interface that interfaces to
A face unit 38 may also be provided. Prog
The RAM capable controller master 46 is also a drop.
It is shown as one. This is used by various programs.
on a separate bus to which a programmable controller 46 can be connected.
A programmable controller highway 4
Provides an interface with 4. Said prog
The ram-enabled controller 46 is a process input/output bar.
Other programmable controllers via
Can be connected to 50. Therefore, a large number of different
All controllers in one drop and interface
data highway 1 by phasing
Eliminates the need for access spots on the
Allows complete flexibility in configuration. Each
Simply adapt the drop to the overall configuration of your system.
but also to suit the purpose of each individual drop.
Can be configured. Figure 3 shows the components of the system of the present invention.
FIG. 3 is a detailed diagram of the hardware of the set; data high
Way 10 has data highway control
A (DHC) subsystem 52 is connected.
This subsystem is common to all drops.
, shared memory, serial-parallel and parallel-serial data conversion.
Modulator/Demodulator (Modem) for and preferred
For the example, a custom bit slice mask
A database system that is a microprocessor
Consists of A. Processusa. Shared memory is dual
port memory and data highway
I processor and functional processor 54 (described later)
form an interface between function pro
Setsa performs specific drops and coordination tasks.
cormorant. A functional processor uses one or more chips.
It consists of a commercially available microprocessor. here
A microprocessor is a single chip or
refers to interconnected chips and associated memory.
Therefore, a microprocessor in a known manner
Including system. The functional processor 54 performs the processing of the present invention via the DHC.
The rest of the distributed process control system and the transmission type
communicate. Everything transferred to and from shared memory
All data is processed by the functional processor regardless of its origin.
is considered part of its internal database.
It will be done. Other Drops via the Data Highway
In the preferred embodiment, data is supplied to the
The data highway controller
Comparing the message with a stored table
The federation's functional processor requires this data.
Determine whether or not. If you don't need it
, this message is stored in Drop's shared memory.
be stored or copied. Therefore, the functional process
The service provider is exempted from such communication duties, and the data
Note the memory shared with the highway processor.
It can be used as a control function to concentrate on the original control function.
Using two processors together with shared memory
Written by Data Highway Interface
is simplified and local to the functional processor.
Adds processing power. Function processor 54 is an operator input/output terminal.
a human/machine interface via device 56;
Any form of process input/output device 58
Drops such as data acquisition and control processing, etc.
and perform specific functions of cooperation. The functional processor is
Get data from memory for storage, store it, and use it as needed.
Other hardware, e.g. mass memory
Process input/output and communication with peripheral devices, etc.
By data highway microprocessor
The function processor handles the communication work.
Exempted. Input/output interface 58 is under control
Enables communication with various processes within the factory.
In this configuration, operator console display 56
as well as all forms of process controllers.
Various input/output devices such as devices can be used. 2 Communication Format In order to facilitate understanding of the following means,
The communication format used will be briefly explained. De
communication that takes place over a data highway bus
is the data highway controller at each drop.
controlled by a troller. Communication is a process
This is not only done through regular broadcasting of data.
For requests made by any one drop,
It is done in concert. In a preferred embodiment, the system
The system is a mixed mode consisting of repetitive and non-repetitive transmission modes.
It operates according to the code communication method. 100 milliseconds each
During the first iteration of the command communication cycle, the system
Used in time division multiplexing (TDM) method, this method
Then each drop has at least one time “slot”.
” in this time slot.
Loop outputs a message on the data highway
do. All other drops are required from the message.
You can select the data you need. 100mm each
The second half of the second interval, i.e. the non-repetitive part
In “Democratic” mode, which is
iway sends other messages, e.g.
Used for specific data requests etc. from
be able to. Specifically, (in the preferred embodiment)
(can be installed up to 254) each drop is 100mm
Access the highway every second and
along with message identifier and status information.
broadcast process values stored in memory for
be able to. Each drop that is not on air is connected to other drops.
Listen to Lop's broadcasts and highlight points of interest.
Select, retrieve this from the highway and share notes
Let me remember it. At the end of each regular broadcast, 100 Meriseconds each.
The remaining time in the time slice can be changed as needed.
Communication, e.g. downloading programs, points
It is used for transferring English descriptions of documents. Drop
can also handle specific data requests as needed.
send as well as specific data from other drops.
respond to data requests. In reality, all processes run at least once every second.
The variable value is broadcast, but each drop is 100 mm.
Because you access the highway every second,
If conditions permit, each drop should be 100 milliseconds.
data on key process points once every
It is possible to broadcast data and communicate. data ha
iway is at least 10000 process points per second
transfer speeds that allow for client system broadcast speeds.
have The broadcasting technology used to implement the present invention is
Eliminates the need for a star or traffic director
At the same time, a confirmation is sent back to the origin in the system.
The high overhead inherent in traditional transmission/acknowledgment methods
It also eliminates head problems. In the system of the present invention,
confirmation that the message was received.
I won't send it. That is, other drops can be removed as needed.
Just output the information to the highway so that it can be released.
be. Each drop temporarily acts as a master.
and during that transmission signal, the next time the highway is accessed.
Contains a token that indicates which drop to drop. this
so that two or more drops can be sent at the same time
to avoid accessing data highways.
Coordination of transmission operations is being attempted. When forming a drop database,
English description of data points, alarm limits
Determine database information such as
The same dots from which the process value is obtained or calculated.
stored in the memory of the program. In this way the system
The system database is similar to the process system.
distributed in many drops. mixed mode broadcast
Any drone connected to the highway by means of communication
I wonder if Tsupu exists anywhere in the system?
The process data that is
access as if it were part of the data base.
can be done. Therefore, the data highway is
Qualitatively, all drops belonging to the system are available.
Acts as a distributed global database that can be used
However, due to the speed and configuration of the communication system, this overall
The database is always new and becomes older by more than a second
That can't happen. Each drive against a distributed global database
This type of transparent access of the lop is a control loop.
is formed or calculated by other drops.
Can work with one drop using process values
It means that. Also, the overall database
Transparent access to
Functions that are restricted to those performed in Tsusa
Enables distribution anywhere on the highway
However, this is a physically large and complex system.
is a very advantageous requirement and requires changes to existing systems.
or degrade its performance.
Adding drops to existing systems to improve their performance
This is a requirement that makes it possible to increase for example
Added calculator, elapsed memory, and data acquisition drop
can do. Receive broadcasts from additional drops
each feature processor to include or ignore.
can be programmed to adapt to the behavior of existing drops.
Drop as needed without impact
Can be added. Similarly, mix up the behavior of the remaining drops.
Drops can be removed without disturbing them. The key features of any process system
functions, e.g. optimization of the entire factory, storage of progress data
and searches, and progress records for all factories.
access to a physical database is required.
Ru. Traditionally, such functions were periodically installed from the highway.
factory data and these factory-wide
internally for use by programs.
host computers that form the computer base.
This was done by using Apps like this
The major disadvantage of Roach is that it requires a large number of host computers.
Because many functions must be provided at the same time,
As this computer's capacity reaches saturation,
be. For example, traditional operator terminal equipment
system-wide database
Yes, and therefore the entire database is stored.
The host controller that accesses the main memory
configured as a peripheral device attached to the computer.
It was. In the present invention, any drop can be used to
transparent access to the data base
Many functions that previously required a host computer
Can be distributed to the host computer
computer functions on a distributed computer system.
can be carried out. Passed the first drop
Configured for data storage and retrieval, with a second drop
Configured as a factory optimization computer, the third
A host computer is now required.
Configure as a logger to provide other features of
be able to. System utilization increases and host
performance deterioration associated with remote computers will be eliminated.
That is clearly an advantage. Also, the hierarchy system
Due to interface configuration such as control method, host controller
If you need a computer, check out the “Gateway” Drop
You can easily make do with it.
Finally, the communication transparency provided by the present invention
In view of this, it is recommended to connect additional drops to the system.
is easy. In the preferred embodiment, the long
Coaxial lines forming a 6 km long data highway
Up to 254 drops can be connected to the cable.
Other embodiments can support up to 64 drops
Adopts a highway consisting of optic fibers
do. As readily understood by those skilled in the art, the
Chick fiber cable is a regular coaxial cable
It has much better low noise characteristics than the
This is significant for use in certain types of factories.
It can be a characteristic. This kind of system is
capacity determined by size and time delay factors.
Although the system and method of the present invention
Also constrained by engineering constraints.
Ru. Additionally, data acquisition and local control functions can be integrated into a single drive.
By integrating into the rope, either one of the
Systems that perform only functions often require
Duplication of sensors is avoided. single drop
Functions can also be used, for example, to start with data acquisition and then
This makes it easy to integrate systems that control
Ru. Additionally, this configuration can be used for process modulation, sequence
An integrated approach to control and data acquisition
enable. 3 Overview of Drops In Figure 4, the system of the present invention
process monitoring, process control, operator input
Level of drop for features such as Turf Ace
While the first functional processor 60 is used for
Get the data required by the function processor from the way
and the function processor to communicate with the highway.
The second data highway processor 64 is
use. With this configuration, the feature
Rosetsusa focuses on data acquisition and control tasks.
and are exempt from complex communication interface requirements.
Ru. Functional processor 60 communicates via shared memory 62.
and connects to the data highway processor 64.
Ru. Directly from one processor to another
two processes without simultaneously transferring data to
automatically provide an interface between
In this respect, it is extremely desirable to employ the shared memory 62.
In other words, in this configuration, one of the processors
Just access the shared memory 62 as needed
It is. Functional processor 60 is a process/output unit.
Various known input/output units can be connected via the unit 68.
Connect with 66. As detailed below, the function
The processor connects to a known industry standard bus,
In that case, any form that can be connected to such a bus
Designed to allow use with publicly known input/output devices
do. Therefore, the user of the system of the present invention
process input/output units of the processor must be used.
Virtually voluntary, without the restriction that
Devices can be connected. Data highway processor 64 is redundant
Although the diagram is doubled in order to give
Data High (corresponding to Highway 10 in Figure 3)
Connect to way 70. dual highways are physical
Configure separate transmission lines, or paths. Here
The highway means coaxial cable, optical cable, etc.
Fiber cable or equivalent
means. Two-way communication module 72 and tracker
Greater redundancy is provided by receiver 76.
Ru. I will explain these in detail later.
Ru. Data Highway Processor 64, Communications
The module 72 and shared memory 62 are the same as those shown in FIG.
data highway controller 52.
Ru. Figure 5 shows details of the data highway drop.
configuration and some components that may be necessary
indicates redundancy. Illustrated data highway 70
is redundant and is transmitted via transceiver (MBT) 76.
data highway communication controller
(MBC)72 and connect this controller.
(MBC) 76 is data highway controller
It is connected to the LA (DHC) bus 82. That is, de
The data highway communication card (MBC) 72 is a redundant
Provided in long form. data highway control
The roller bus 82 includes a functional processor 60 and a
perform communication functions with the data highway 70.
Data Highway Processor (MBD)64
is connected. data highway control
The LA bus 82 provides functional processing via a second bus 84.
via shared memory (MBS) 62 connected to Tsusa 60.
and connect it to the functional processor. Preferred embodiment
Now, this second bus 84 is an industrial standard "multibus"
(Intel Corporation product name).
This industrial standard bus (specified in IEEE standard No. 796)
User selection of functional processor
is not limited to products from a specific manufacturer, and can be applied to industrial scale markets.
Extensive multibus data communication interface
You can choose from a wide range of market peripherals. This results in
This provides a great deal of flexibility in drop configuration. de
depending on user needs and system equipment.
can be configured. to multibus interface
There are literally countless peripheral devices that can be adapted.
The possible orders of the inventive system are almost infinite.
Ru. Particularly flexible functional processor unit
The model number is SBC86/05 and is manufactured by Intel Corp.
- Sold by Shion. This unit has 16
It is a bit microcomputer and a person skilled in the art
human/machine interface, including the generation of video displays.
Ace, process interface and control
Pro to perform a wide range of useful functions such as
It is easy to gram. inter manu
Please refer to Al Oda No. 143153-001. A third bus 86, referred to as a distributed input/output bus
interface multibus 84 to
interface unit (MBU)
94 can be used. From bus 86, respectively.
interface specifications may differ.
A connection can be made to the output device.
Functional processor 60 also includes a process monitor.
-, process control, operator interface
To obtain various functions such as
It is connected via bus 84 to input/output devices 88 .
Other drop functions such as record keeping are also possible.
Ru. FIG. 6 shows the components described above in connection with FIG.
physical location in the drop. data·
The highway 70 is connected to a transceiver 76 and
From this transceiver 76, the cable is
data card inserted into the storage card cage 90.
This leads to the Wi-Fi communication (MBC) card 72. Tiger
A receiver 76 is provided in the cage 90, and the highway 7
It may be placed in close proximity to 0. Also, Malteva
components that are compatible with the system, such as shared memory systems.
system (MBS) 62 and function processor 60
It is installed in the cage and inserted into the multi-bath. drawing
Now connect the multibus connector to the back of the card cage.
It is shown by a dashed line 92 across the surface. That is, if the car is in the cage.
Connect to multibus by simply inserting the card.
Established automatically. data highway control
Roller (DHC) bus 82 is also a data highway
processor 64, shared memory (MBS) 62
and data highway communication card MBC72.
Indicated by connecting dashed lines. Multibus 92 connects functional processor 60.
It is also called Q-line card cage 96.
Distributed input/output buffers in the second card cage called
It also connects to the MBU unit 94 via the bus 82.
Connecting. Cage 96 may be used for other inputs/outputs, e.g.
equipment, such as those manufactured by Westingham, the applicant of the present invention.
From Us Electric Corporation
Sold under the product name “Q-Line Point Card”
It may also include input/output devices such as those sold on the market.
can. These are as shown in Figure 6.
Actual contact with position sensors, position actuators, etc.
Continue. Therefore, such as operator terminal equipment, etc.
According to Direct Multibus Compatible Peripherals
If you want the drop to work, use this in multibar.
Just connect it to the bus 92. Also, certain professional
If process control is required, use the MBU unit 94.
to interface the multibus with the distributed input/output bus 86.
After interface, as shown in Figure 6.
Plant sensor Q-line card cage 9
6 (or any other bus system)
That's fine. As is clear from Figure 6, the data
MBC7, a highway communication (Modem) card
2. With data highway processor card
There is an MBD64, and a shared memory card.
MBS62 is connected to DHC or Data Highway Co.
controller 98 is configured. MBT or Tran
Seaba can also be placed here. These 4
The card has a function processor 60 and a data high
form an interface between the way bus 70
including the means to accomplish this. Data Highway Controller (DHC)
For details of the 98 constituents, please refer to the data
After explaining the format of messages used in stingrays
Explain. 4 Message format Message format used in accordance with the present invention
The mat is shown schematically in FIGS. 7 and 8. Figure 7a is a book
1 shows an overview of the inventive mixed mode transmission system; Already
As stated in
It is performed in a tarbal. 100mm each
The first part of the barrel time slice is TDM mode
102, and in this part the time is
divided into slices. at least one tie
Each drop is assigned to a slice of 100
Ru. That is, for example, the drop 81 is the first slice 1.
00, drop 82 will drop to the next slice.
83 is transmitted to the next slice, and so on.
Do the following. When TDM mode 102 ends, demo
Enter the check mode 104. At this time, e.g.
For example, additional data, program downloads,
Special requests such as requests for system maintenance, etc.
The message is transmitted. The drop should be transmitted.
If you don't have a democratic message,
Transmit a blank message and take the bus to the next drop.
“Hand off”. The mixed mode approach has several advantages. Time
By using split multiplexing, all
Tsupu accesses the bus at the specified time. this child
is the frequent transmission of given data throughout the system.
enable communication. In TDM method, data high
You can make the most of your time for way communication.
Also, by providing a democratic mode
This gives the system significant flexibility. That is, de
functions that are not possible when data transmission is TDM only.
can be done. Figure 7b from drop to data highway
One data block or “frame” to be transmitted
individual fields are subject to change.
However, the same format is also demonstrated in TDM mode.
It is also used in Krachitsuk mode. be hired
The protocol is basically IBM Corporation
The well-known
This is an improved version of the “HDLC” frame. the
The basic configuration is shown in Figure 7b. consecutive frames
Leave a space in between, and after this space add a length of approx.
2.4 microsecond mark pulse 106
This pulse is used to activate the data transmitter.
let This pulse has 8 two-phase encoded 0 strings 10
8 is followed, and this is the recovery of the next transmitted two-phase data.
The data highway used for
Synchronize the phase lock loop circuit of the communication card.
Ru. Then one 0, six 1s and another 0?
A flag byte 110 follows. hdlc pro
This binary value sequence is unique in the protocol.
Can be used as a flag. This is explained below.
Ru. Using HDLC protocol or zero insertion method
may cause inadvertent access to the data highway bus.
Prevent the flag from appearing. In the zero insertion method
If the data to be sent has 5 consecutive ones
Insert extra zeros into the outgoing data stream if the data
is output to the data highway processor.
Before receiving HDLC controller, input flow sequentially
, the above-mentioned remainder along with the periodic redundant character described below.
The zero of the minute is removed. That is, the known HDLC controller
The rollers only flip at the beginning and end of the transmission block.
Exiting to the data highway so that the lag appears
Control power. Flag 110, associated with Figure 7c
address, control and data files as described below.
Rudo 112 continues. Next, cyclic redundancy of length 2 bytes
Check field 114 follows, but this field
Yield to data highway controller
and error checking according to known techniques.
inserted into the outgoing transmission signal for checking and modification. No.
2 flag 110 completes the transmission. Figure 7c shows the drop from the drop shown in Figure 7b.
data blocks or “frames” to be
It is a development diagram of the description thus given. flag·
Byte 110 is as described above. Add to this
Les Field 116 follows. This address
The field or “A-byte” 116 is the data
Find the next drop accessing the highway.
Acts as a “token” that determines the A-byte
116 is every time the drop sends a message.
With an 8-bit address index that grows to
be. This index is
an access to the drop table that indicates the next drop to be
used for access. address byte 116
A control byte 118 follows. This is a control flag.
This is a byte consisting of 8 bits. This control flag
This will be explained in detail later in connection with Figure 8a.
Ru. Then 0 to 63 data words 120
Subsequently, the details of this data word are also shown in sections 8b and 8.
This will be described later in relation to figure c. Messenger shown in Figure 7c
specific program to be monitored within the page frame.
Typical points or subdivisions related to process values
minute is a “system” that identifies a specific data point.
is a “system identification” tag that specifies a specific data message.
is important to the functional processor of the collaboration.
Data highway controller to determine
Contains one word used by. Each poi
Also includes status words. Other works
For example, a card can be used to transmit analog values.
I can do it. After all words have been transmitted, 16 bits
periodic redundancy check 114 and flag 1
10 is transmitted and any one droplet of the present invention
Frames sent from the
Complete. Figure 8, consisting of Figures 8a to 8d, shows the above frame.
It shows the detailed format of each part of the system. 8th
Figure a shows the bits used in C field 118.
limit. As already mentioned, it consists of 8 bits.
Ru. Bit P, which takes the seventh position, is combined
Parity bits for A and B fields
It is. Parity is limited to odd numbers. this
The bits are between the processor and the HDLC controller.
Bit errors that may occur during transmission
Catch. The M bit occupying position 6 is mesuse.
Indicates the mode of the page. It's set
, the mode is TDM, i.e. same message format.
-Matsuto goes into democratic mode for TDM as well
is also used, and the M bit indicates which
Specify which mode it belongs to. occupy position 5
The T bit indicates the mode of subsequent messages.
Ru. If set, the mode is TDM, in other words
Then, this bit indicates which mode the current drop is in.
handoff to the host. occupying position 4
The H bit set by DHC is
Frame-first handoff goes unanswered
Recovery handoff due to heat
represents. R bits are transmitted via the data highway.
Time to synchronize frame transmissions that take place
Used by the Keeper. It's set
Then, the R bit is set by the timekeeper DHC as the data hacker.
Detected that Iway's downtime was abnormally long,
Restart the data highway from this frame.
Instruct what is happening. Therefore, the symbol path behavior
The time key indicates that some error has occurred.
The R bit is set when the pass is detected. 100mi
After the resecond time has passed, U occupies position 2.
bit is the final democratic mode frame
set during a frame and the next frame is TDM.
Instruct the person to do the following. In this case, the re-democracy
The A field is used to recover the cycle.
Leave it unused. Therefore, the U bit is set
If there is, enter the value for the first description item in the TDM list.
means ``end off''. Finally, set positions 1 and 0 to
The two S bits each occupy also act as timekeepers.
It is often used. If this S bit is 0
The word following the C field may contain the clock value.
means. The S bit value is (to provide redundancy)
Me) Three time keys used in the system
Which timekeeper is sending the message?
Indicates whether Value 01 is time keeper A
, 10 is time key B, 11 is time key
Each means P.C. Data portion 120 of the transmission block (Figure 7c)
can be blank or contain up to 63 words.
can. In the data portion 120 of the transmission block
The format of the message is that the transmission is in TDM mode.
De frame or democratic mode frame
It depends on the mood. each with a period of 100 milliseconds
In the TDM part, the DHC of each drop is one frame.
The periodic information is sent, and each frame is
Stem ID, status word, and ifana
If it's a log point, it's a set of messages consisting of that value.
Consists of pages. Digital TDM message format
The mat is as shown in Figure 8b, and the analog
The format of the TDM message is shown in Figure 8c.
As shown. In either case, the system
Starts with a system ID word and a status word. System ID is located in the first word of the message
Contains a combined 14-bit system element identifier.
nothing. System ID identifies the nature and origin of the data
to determine whether this message is important or not.
Each drop is tested accordingly. Adopts 14 bits
Over 16000 individual data points,
i.e., process variable values, system status, etc.
This makes it possible to identify each separately. 14 bit
If you specify a number between 1 and 254,
For example, rather than specifying a single data point,
to drop while sending a message
It's nothing more than that. For example, when the printer runs out of paper,
If a drop configured as this printer is
is in the alarm state, and therefore this
The 14-bit number provides convenient communication functions. 2ba
The two extra bits in the host's system ID are:
Utilized by sea urchins. Bit 15 has an analog message.
whether it is a digital point or a digital point.
Ru. If it is set, the points are digital,
If it is cleared, the point is analog.
Ru. Bit 14 is always 1 in TDM messages.
is set to This allows the function processor to
TDM description items can be written in democratic mode.
It can be distinguished from the mentioned items. Status/
The word contains attributes of the message's status.
If the system elements are digital, the status
The least significant bit of the word contains the digital value. 8th
The two-word analog value field shown in Figure c is
Used only for analog messages. This fee
field contains a 32-bit floating point analog value.
nothing. Figure 8d is available in the preferred embodiment
It is a democratic mode message.
In the DEM part with a period of 100 milliseconds,
Some DHCs will respond to requested non-regular requests.
whether the message is executed by a coordinating functional processor or
is sent in response to a request from another drop.
I can believe it. 100 milliseconds given
The number of DHCs actually transmitted in a TDM cycle depends on the number of DHCs actually transmitted in a TDM cycle.
limited by the time remaining until the period begins.
In some cases, all drops are
messages can be sent. DEM period
Messages sent to are one-shot broadcasts.
and messages to the origin drop.
be done. One-shot broadcasting is based on system elements.
Send all attributes to all drops
used for. This kind of broadcast is a drop
receives a one-shot broadcast request from another drop.
Sent when a message is received. The system ID part of one-shot broadcasting is number 8.
As described in connection with figures b and 8c. W.C.
The field is one word and is included in the message.
Indicates the number of additional words of information to be added. starting point dorotsu
For request/change messages to
This field can be 0. If 0, then this
The message is identified by the system ID field.
information about all attributes of system elements
be interpreted as a request for a shot broadcast.
Ru. If WC field is 0, DISP and AD field
There are no rules. Relationship with One Shot Broadcasting
The AA field used in the series is 1 to 61 words.
This word is stored sequentially in shared memory.
It will be done. To send data to the drop, use request/
A modified message is used. System ID and
The WC field is as described above. DISP fee
A field is a record of transmitted data within a data record.
Used to indicate storage location. AD file
The code can be applied to one or more attributes of the specified element.
1 to 60 words representing information. most
Later, the general message to the origin drop will also be the same.
Contains the same system ID and WC fields, but is shared
8 first-in/first-out memory
Which buffer of buffers (FIFO) is used?
Indicate what is used to memorize the tsage
Also includes FI field. To summarize, to the starting point
Request/change message is one shot
Specific data to be transmitted using broadcast format
used to request data. General to origin
Messages such as confirmation or similar
It becomes a signal. 5 Data Encoding and Decoding Figure 9 shows what is used in connection with the present invention.
1 is a comparison diagram of various data encoding methods including: FIG. 9th
The first row of the diagram contains data in the form of a series of 0's and 1's.
Illustrated. The next line NRZ is a “non-return-to-zero” sign
This is a coding method in which the signal is at a high level at the time corresponding to 1.
It is at the bell and at other times it is at a lower level. Next
The line NRZI is used in some data recording systems.
It is widely used to convert and reduce the number of data.
This is a “non-zero inversion return” method. 4th row
RZ is a simple half-bit cell high pulse for 1
otherwise used to provide low pulses.
This is the return-to-zero encoding method used. This method
It is said that automatic clock control of the data is not possible.
not. Finally, the data highway
Two-phase encoding method employed in the present invention for data transfer
is shown in the fifth row. This data conversion method
In the end, there is a 0 in the center of every bit cell.
If it is 1, an upward conversion occurs, and if it is 1, a downward conversion occurs.
The result is the waveform shown. That is, two-phase encoding
, half of each bit cell is low and half is high.
and the higher half appears first or second.
coded 1 or 0 depending on
It is determined whether the The NRZ encoding method is utilized within the controller of the present invention.
However, the two-phase encoding method is
It will be used via i. Therefore, a means of translation will be provided.
There is a need. This is shown in Figure 11.
Figure 19 shows the relevant waveforms. should be coded
The result of exclusive OR operation on NRZ data
The 4MHz clock frizzes along with the 2MHz clock and the 2MHz clock.
122. Flip F
The output of the lop is the two-phase data shown in the lower part of Figure 10.
It is. The message program shown in Figures 10 and 11
The rotor is as already mentioned. That is, in
The mark formed by the barter 126 allows
The transmitter activates as soon as the message starts. in
The spacing is maintained by converter 128, and the result
As shown and as described above in connection with Figure 7b.
The format will look like this. The two-phase data encoding method used in the present invention includes
There are several advantages. One of them is all
Since the conversion occurs in the data bits of
Sufficient frequency information to allow dynamic clock control
Therefore, a single coaxial cable is sufficient.
Ru. For two-phase encoding, the net DC voltage is 0.
is also convenient, generally between the conductor and the shield.
No DC voltage is generated. Another advantage of two-phase encoded communication is that two-phase encoded
Now, each bit coded in a bit cell is
half are high or “positive” and half are low or “negative”
becomes. For example, 1 is the first in one bit cell.
first coded as “high” and then as “low”.
, and 0 is the opposite. Other features of the invention
When decoding, the first and second bit cells of each bit cell are
By comparing the relative amplitudes of the parts with each other,
Achieve relatively noise-free decoding of phase data
be able to. In other words, the first half of the bit cell is
1 is detected if it is higher on average than the amplitude of the second half
and vice versa if it is 0. Shown in Figure 10.
The square wave two-phase data is processed by a flip-flop.
This is almost ideal data created by just
However, in the process of being transmitted on the coaxial highway,
signal deterioration occurs, and the rectangular edges become slightly rounded.
Ru. In order to receive data correctly, transmission verification is required.
It is necessary to provide means to improve the accuracy of knowledge. present invention
Another feature of is that the two-phase data can be
sample each half of the bit cell.
Weight the center sample against both ends, weight
This bit set is determined by summing the values
Another modification is made by forming the total value of each half of the
Get good results. The total value of the first half is the second half
If it is larger than the total value of , 1 is decoded, and then
If the half is larger, 0 is decoded. Therefore,
For example, stray electricity that appears on the line for some reason
A considerable part of the high half of the bit cell under the action of pressure
It is extremely effective in that the noise is small even when the minute is negative.
and under the action of said stray voltage.
Since the weighting method was adopted, it was decoded correctly.
There is a high possibility that Figure 13 shows how this correct decoding is performed.
FIG. Figure 13a is ideal
This shows two-phase data. One bit cell is
The first half is high, the second half is low, coded as 1
indicates that it has been done. Figure 13b shows the data to be detected.
An extreme example is shown in which data is accompanied by distortion and noise. 1st
The waveform shown in Figure 3a is distorted and is shown by the dashed line in Figure 13b.
The waveform becomes almost a sine wave, but the line noise is
The shape is significantly deviated from the shape shown by the broken line. As mentioned above, the key to decrypt the two-phase data is
Detect whether either half of the sample has a higher average value
It is to be. When noise is correlated with signal amplitude
is unthinkable, so a signal with an almost sinusoidal waveform is compared.
It is in the center of each cell that it has a significant meaning.
Ru. That is, the maximum at the center of the bit cell amplitude
If the signal is 0.3 volts, −0.2 volts of noise is reliable.
The sign is not detected as negative with respect to 0, but for example
The signal value is slightly 0.1 volts near both ends of the bit cell.
If default, the signal is sensed as negative with respect to zero. subordinate
Figure 13c shows how each part of the bit cell is divided.
Indicates the weighting value given to the lower-level unit.
vinegar. In the preferred embodiment, each half of the bit cell is
Divided into 8 subunits. end unit
is given a value of 0, and the weighting of the intermediate unit is
Increase gradually until the central unit takes a relative value of 3. child
These are all as shown in Figure 13c. other
It goes without saying that a weighting method may be used.
do not have. For a given subunit, the waveform values are
If positive for any value, this subunit
The weighting value of the associated bit cell is
value. The whole bit cell like this
After analyzing the results, compare the total value of each half.
The total value of the first half is the total value of the second half.
If the first half is also high, 1 is decoded, and if the first half is low
The bit is 0. Figure 13c shows that if the waveform is positive,
If the “1” bit string is negative or 0, it becomes a “0” bit.
The mechanism by which columns are formed is shown. This bit string
is added to the weighted values and the results are summed.
Ru. This ignores all negative parts of the waveform.
is obtained using the weighting values shown in Fig. 13c.
This means that the amount of units that will be added is added. the
The results are shown in Figure 13e. First half of bit cell
The minutes have a total value of 8, and the second half has a total value of 6.
Since it is taken, it means that 1 has been decoded. Of course
Well, theoretically in this example the first half of the bit cell
The first part will take the value 12, and the second half will take the value 0.
Ru. The information listed here is easily understood by those skilled in the art.
The examples given above are grossly exaggerated. Not much noise
It is usually not noticeable. In fact, the advantages of the present invention
In the preferred embodiment, the bit error rate is 10 ^-7 than
Much lower. Another feature of the present invention is that the two-phase data can be
The phase lock is used to set the clock to be divided into
weight the divided subparts relative to each other using
and can be summed to provide statistically superior data detection.
make it possible. Perform this operation and perform the above decryption.
A circuit for carrying out this process is shown in FIG. Nominal frequency 2M
Hz two-phase data is provided at 130 and the bit
so that 16 samples are formed per cell.
32MHz sampling generated from oscillator 132
Sampled at speed. The circuit is basically a bit
Detect leading edge changes to find cells. inspection
When an edge is detected by the detection device 156, the edge is detected by the detection device 156.
A digital phase lock loop counts up to the next edge.
To up. The count is reconciled each time.
and bit the counter interval if necessary.
Adjust by 1 to match the cell.
The phase lock loop is configured from the flag shown in Figure 7b.
Synchronization based on eight zeros separating the gate bits.
It will be done. In this way, the phase lock loop is
Find the period field. Check this initial field.
By knowing the possibility of 180° phase shift synchronization,
It disappears. Two consecutive by OR gate 134
After the phase OK signal is output, the lock state is
exist. The input data has two periods, i.e. two component two-phase data.
sampled in the first and second half of the data. day
The data decoding process converts two-phase samples into single-component NRZ
Two PROM13 to convert to data bit
6 and 138 are used. “1” PROM136
The first time it operates, the input shift register 1 is already
40 and temporarily register 1.
42. two phases each
16 samples per bit cell are divided into two 8-bit
It is extracted in the form of a group of tutos. This 8-bit group is the standard
Figure 13d shows the input waveforms compared to the values shown in Figure 13d.
It is a 1 or 0 bit string like this. 140 smell
After being shifted in, the first bit group is 8 bits.
The data is transferred to the parallel register 142. of the register
The output is “1” and the address for PROM136.
It works. The contents of each PROM location are
Logic provided by an address that is 8 bits
Contains a number representing a weighted algebraic value of 1. PROM
The output of is a weighted sum provided as nibbles,
That is, it is stored in the 4-bit parallel register 144.
It is 1/2 byte of data. In this process, 8 bits
The second half of the two-phase data cell consisting of
The first 8 bits are processed in the same way as the first 8 bits. child
The junction points are extracted from 16 samples of raw data.
There are two data nibbles. These nibbles are
1PROM 136 and 4-bit register 144
For PROM138 supplied and zero-aligned together
Acts as an address. This PROM has two
If the upper 4 bits, that is, the first
If the value of the bull is greater than the lower 4 bit value, the signal is
Outputs 1. Otherwise, signal 0 will be output.
Ru. When clock control is performed, this becomes 146.
Non-zero feedback data output occurs at If all 0
PROM138 address is set to 0 or set to 1
Then, there is no DHB activity and therefore the “activity” belief
Even if ACTVTY is set, it is still a false signal.
become. That is, the address for PROM138
An address of 1s or 0s is presented as
If the signal is active, no activity signal will be generated. As mentioned above, Figure 13 shows the ideal bit cell.
square wave part (Fig. 13a) and typical, but
Graph the relationship between the exaggerated real waveforms (Figure 13a)
to show. The weight assigned to each of the samples
The estimated values are shown below the individual samples in Figure 13c.
did. As is clear from the figure, at least
data storage that is easily disturbed by noise, jitter, etc.
The center part of the screen is designed to increase the accuracy of the output NRZ data.
is specially emphasized by the stored value of PROM136.
ing. As mentioned above, highway activities are PROM13.
Detection based on the presence or absence of changes detected by 8.
be done. “No activity” means three consecutive two-phase codes.
Defined as the absence of a Microen described later
microengine, data highway
The controller and timekeeper use this activity signal.
to ensure detection of incoming message frames.
otherwise the noise will be confused with real data.
Prevent from being exposed. 6. Clock Control - Overview As can be readily understood by those skilled in the art,
Accurate timing is important in fabric control systems.
This is an essential condition, and the present invention is no exception. There
, the drops all operate on the same time value.
Special measures have been taken to ensure that time division multiple
Synchronize all drops when transitioning to heavy mode
This timing is done by
Ru. Any drop contains control bytes for that frame.
Time division by setting the “U” bit in
When a command to switch to multiplex mode is broadcast, all
All drops receive this. So each dorotsu
the local time snap shot.
Ru. That is, the internal clock included in each drop is
Record the value when the U bit was sent. Mo
Mode switching is received almost simultaneously by each drop
In theory, all drops are exactly the same.
The time will be recorded at some point. Next most
The first three drops to be broadcast, i.e. the time key.
between the C field and the first SID word.
Snapshots recorded by each timekeeper
Insert another word containing the content. time key
Each drop, including the pa, receives this broadcast.
Because we believe that the first three emissions in TDM mode
After transmission, each drop has three time snapshots.
This means that the message has been received. inside each drop
data highway including local clock
I processor has three snap shot ties
Check the system and take the average of the two approximate values.
Ru. The data highway processor then
The average value of “Switching to TDM” of the processor itself
Compare with the command time snap shot and see the comparison.
Adjust its clock according to the comparison result. That is,
Each processor has this function as required by the processor.
The clock data can be accessed so that the clock value can be accessed.
time is stored contiguously in its shared memory. child
The process will be described in more detail later. One feature of the invention is that three separate tie
Mie by using Mukipa Drop
Provide redundancy to timekeepers. time keeper's
The basic function is to search and detect lost tokens.
It's about doing. In other words, the highway is one drop.
Hand off correctly from one drop to the next
The goal is to provide the signals necessary to general
, send that frame to the highway and
After passing the drop, each drop will be sent to the other within the given time.
Check to see if there are any broadcasts coming in. Preconditions
As a matter of fact, if the broadcast comes in, the next drop
verified the token and executed the broadcast.
If the broadcast is not detected, the token is missing.
It means that The drop that passes the token comes first.
Wait 30 microseconds, then 80 microseconds
Set the window of your computer to check for new broadcasts.
Gasu. If not found, increment address again
and retransmit frames without data fields.
This will pass the token to the next drop.
Therefore, this drop means that the next drop will
Recognizes response signals and sends own message
Incremental operations can continue until example
For example, approximately 100 drops are arranged in numerical order and
Systems where lops 30-39 are offline
is possible. In this case, drop 29 is
A token addressed to drop 40 is sent by drop 40.
in 11 increments until confirmed in the form of a trust.
do. However, in reality, “confirmation” messages are not used.
Not used. Each message is just data
, but also the next token, which means that the previous token
Confirm that the delivery of the package was carried out correctly.
means. Three timekeeper drops on the highway
It also performs separate monitoring functions for received
Following each broadcast, three timekeepers
time out. That is, the first time
Keeper is 240 microseconds, second time key
Pa 440 mic seconds, 3rd timekeeper 640
Each timeout is done in microseconds.
Ru. One of the timekeepers receives the token
If this timekeeper is not detected,
new broadcasts must be detected within the given time frame.
For example, restart communication from the starting point in time division multiplexing mode.
Start. For some reason the first timekeeper
If no broadcast is detected within 240 microseconds, the
1 timekeeper spans 440 microseconds
and monitor it. Often a second timekeeper
Back up the first timekeeper and do the same for the third timekeeper.
The timekeeper beats the first and second timekeepers.
Cup up. The timekeeper has three modes of operation. Immediately
1 Normal mode 2 Timekeeper mode 3 Reset mode In normal mode, MBC sends messages.
The timekeeper is activated after receiving the signal. highway
Active for 110 microseconds in
If not detected, the timekeeper times out.
Then, MBC interrupts MBD. Timekeeper mode is data highway
Used to detect system failures. activity
If not detected, the timekeeper is activated. C
Time clock before activity in Iway is detected.
If the driver times out, the highway system
It is assumed that there is a failure in the MBC, and the MBC interrupts the MBD.
nothing. MBC timer is a programmable array logic
chip (PAL) control sequencer, program
counter, 100-division counter, and input synchronization
Consists of period registers. These logic elements interact
to perform timing functions. FIG. 14 is a state change diagram of this timer. 4
The signals are shown and set as shown below.
It has a meaning. The TIMOT signal is activated when the cooperation timer times out.
ACTV signal (signal in Figure 12)
(equivalent to ACTVTY) indicates that there is no activity on the highway.
It means that the TWCZ signal has been detected and the transmission is complete.
The IR signal indicates that the interrupt to the MBD is accepted.
It means that it was received. The timer has the following main operating modes:
Ru. 1 Reset mode 2 Normal mode timer 110 microseconds
Condo 3 Timekeeper A, B, or C mode tie
M mode is set by command from MBD according to SS bit.
selected. The timer always runs once with the following exceptions:
It operates in one mode. i.e. time key
In PA mode, the control sequencer is set to 152.
When a TWCZ signal is received, it will automatically jump to no
Runs in macro mode and uses MBC macro engine
to confirm that the message has just been sent.
The exception to this is when giving instructions. Timer reset mode 150 under three conditions
to move to. The first is “off” at 151
, the next step is normal mode.
If there is, but before the message is sent, what is the last message?
This is the case when a mode conversion occurs. Normal mode (NEST node No. 153)
The timing interval is set by the micro engine.
30 microseconds and timer self-timed
80 microseconds timed by the body.
Ru. In other words, this mode is used at the end of the sent message.
In other words, 30 microseconds after
Microengine is reset and signal TWCZ is set.
It opens when you press the button to start normal mode.
Begins. After starting, the timer indicates that there is no activity on the highway.
Wait for it to appear (ACTV = 1) and press the “receive” address.
The robot actually receives the message and “owns” the message.
"Notify that you are about to start sending"
Ru. The activities are based on the two already explained in connection with Figure 12.
is detected by the phase detection circuit, and this circuit
Output ACTVTY signal. If ACTV is 80 miles
If it doesn't happen within cross seconds (it won't be true)
If the counter times out (TIMOT=
1) As a result, the PAL sequencer becomes a node NTO
and set the interrupt. Here, the recovery hand
Off is sent. This state is interrupted by MBD.
set (IR=1) is received and the message is sent.
It continues until instructed to do what is believed. Then Thailand
The machine jumps to reset mode 150. Nodes MSETA, MSETB and
In timekeeper mode starting with and MSETC,
Each timer monitors highway inactivity.
Ru. 3 given to timekeepers A, B, and C
The three intervals are 240, 440, and 640 respectively.
It is a microsecond. This mode is
now detects when there is no message transmission on the
It is configured. For example, if the highway is completely
If it is in the “dead” state, timekeeper A first
(TIMOT = 1) and outputs a timer interrupt.
(enter node MTO). (not shown) stay
The status bit is set and the normal mode is activated.
Timekeeper mode instead of detimeout
timeout. This percentage
This is a signal to restart the MBD. time
The drop programmed as Keeper A is
If it fails, that is, if the IR does not become high, the
Timekeeper B, which acts as a backup,
Timeout at 440 microseconds and do the same
Perform a restart. Timekeeper C is the final
This is a tsuku-up timer. On the other hand, the time key
If ACTV goes high while in PA mode, the reset
After passing through the
mode. Shown below in Figure 14
As in, the node MTO entrance is
Indicates that a restart is required and no
The NTO indicates that a recovery handoff is required.
Instruct. MBD uses the above status bits.
You can distinguish between the two by using
Ru. When the MBD responds with proper operation, the IR signal is
Detected by time keeper and reset motor
150 is accessed. 7 Data Highway Controller A Data Highway Processor (MBD) As will be readily understood by those skilled in the art, the present invention
One of the main hardware components in the system is
A variety of multi-bus compatible peripherals.
a very specific and
The data highway that determines the characteristics of the system
Data Highway Pro that communicates with
It's Setsa. So below is the data highway
I will explain the details of the Microprocessor (MBD) card.
Ru. Figure 15 is the block diagram for this card.
Figures 16 and 17 correspond to the blocks in Figure 15.
The advanced machine shown in the diagram
Micro Devices (AMD) model 2901 bits
Slice microprocessor and 2901 Mac
This is a block diagram of the ROS sequencer. Data Highway Processor (MBD)
It is a high speed bit slice processor. the
The design is general purpose and capable of processing parallel data.
Ru. Below is a single MBD module.
Explain the function. Figure 15 shows the logic block of this device.
Show the Tsuku diagram. MBD is a data encoding/decoding function and serial
MBC communication controller that performs parallelization/parallelization functions
and the MBS shared memory module.
One-board data processor to control
It is. Operates at high speed (200nsec/cycle) and
Decision making via sliced architecture
and data manipulation capabilities. Figure 15
As shown in the block diagram, this device
operates under microcode control of all elements.
Ru. MBD is a microprocessor that gives a 16-bit word length.
Has a programmed structure. pipeline·
mode, instruction execution is performed by the microprogram.
Selecting the next microinstruction from program PROM160
This means that it is done in parallel. 3K×48
Included in bit PROM160 (can be expanded to 4K)
The microcoded instructions are 2910 microsequences.
accessed by the server 162; Each clock
When the current instruction enters the pipeline/branch
clocked into the address register 164 and the “next
“2910 Mic” is executed at clock time.
The sequencer 162 executes instructions sequentially and subroutines.
Chin linkage, internal loop ability, and external
Pass through a branch address formed by
Contains the logic to do this. Details are shown in Figure 17.
Ta. bit test multiplexer 166,
itas code register 168 and reverse read flag
The test tree consisting of registers 170 is
Sequence control based on logic level of desired bits
enable. Each of the eight reverse reading flags
Test and conditionally set or reset
Bye. Other sequence controls are 4 different
Address multiplex from any one source
The “next address” can be selected via the handle 172.
This is achieved by making it possible. address multiple
Lexa 172 selects “branch address”
By controlling the 2910 Micro Sequencer 1
62 controls the next instruction to be executed. multiple
Lexer 172 is one of four multiplexer inputs.
2910 micro for blanching through
Provides external direct input to sequencer 162.
The above four inputs are conditional branch ability, multi
via way branch register 174.
multi-way branching and hand
Interrupt branching to ring subroutines
Provides two inputs for Priority interrupt structure 178 has eight interrupt lines 176
can accept. This structure is micro
Form the lower 4 bits from the code address.
These 4 bits are branch address register 1.
Address multiplex with upper 8 bits of 74
This is the interrupt address to provide to the
Ru. An interrupt is pending and the current microinstruction
If possible, the 2910 micro sequencer 162
Call the appropriate routine used for a specific interrupt
vinegar. The detailed structure of the heart of MBD is shown in Figure 16.
16-bit 2901 ALU/register 180. 16
Word x 16 bit direct address file memory
Equipped with memory, logic, arithmetic and shift operations
under full microcode control.
Ru. ALU input/output ports are source and destination
- Two main buses for sion data, namely Y-
forming the basis of bus 182 and D-bus 184.
Ru. This 16-bit bus also has the following components:
is connected. That is, RAM/ROM micro
Memory 186, byte swap register 18
8. Parity generation/check device 190,
indicator register 192, program
Possible time 194, and W-bus 198 (DHC
bus) and the rest of the DHC.
A connected input/output port 196. RAM/ROM micro memory 186 is 2910
Same as supplied to micro sequencer 162
Addressed using an address. microme
Memory 186 is 512 words of read-only memory (ROM).
memory and random access memory (RAM)
It has 1024 words and requires 2 cycles to access.
is necessary. The address is presented in the first cycle.
and the data is given to the next cycle. 8253 programmable timer 194 is D-Bus 1
The lower 8 bits of 84 are accessed. micro
One piece of data is sent from the memory 186 to the timer 194.
Bytes are loaded and sent via this same bus 184.
, one data is sent from timer 194 to ALU 180.
ta bytes are read. Timer 194 is a microphone
via six control flags 195 from the code
controlled. MBD is a component of two other major system modules.
MBC and MBS are connected via W-Bus 198.
can be accessed. two decoders 2
00 is source and/or under microcode control.
allows selection of the destination register. Figures 21 to 24 below are the sequence of MED operation.
The details of the process are illustrated in detail. MBD is programmed to perform
The functions are outlined below. MBD is data high
Along with accessing the ray communication card (MBC),
Parallel data described below in connection with Figures 18 and 19
Also access the message buffer for. Ba
Tsuhua is a dual port type, W-Bus 1
98 and MBD input/output logic or
Under the control of MBC micro engine (Fig. 19)
be. Received data is an interrupt sent from MBC
accessed by MBD in response to . MBD
checks each system ID (SID). then
MBD is a shared memory (MBS) data-aware array
Extract the control information from the (DRA) part and use this information as
is used by the function processor to process the received word message.
any of the information contained in each of the pages.
Determine if you will be involved. If you don't get involved
The MBS section is called the Data Definition Table (DDT).
Other information contained in the minutes determines where the data is stored.
Instruct. MBS data blocks and conditional storage data
MBD is busy while processing data words.
In round mode (from MBS shown)
The information is retrieved from the system
element (i.e. part of the transmitted word).
Ru. From this system element to MBC
The transmit block for output is
Can be assembled. During transmission, the MBD assigns data blocks to
Receive to determine which MBD to send next
Handoff control information used by MBD
Add a prefix that represents This data is stored by MBD.
Loading length (word count) to MBC
is sent on the W-bus (by MBC) after
Ru. Next, we collaborate with MBC, MBS and functional processors.
A typical example of an MBD that sends and receives data is explained below.
Ru. The message buffer is a 128 word circular receive buffer.
buffer and two 64-word transmission buffers (TDM
Batsufua and Democratic Mode Batsufu
a). MBD is a receiving buffer
Add zero to the DHCP register to indicate the beginning of the
Start receiving messages by loading
Ru. Instructions are then sent to the HDLC controller,
As a result, the received data of the HDLC communication controller
data path is enabled. Receive two-phase decoder
Serial NRZ data from
Performs lag stripping and CRC accumulation
Shifted to HDLC controller. HDLC controller
Signetics or Motolo as a controller
You can use the 2652 model commercially available from La.
It can be physically placed on the MBC board. The rest of the message is memorized by Batsuhua,
After FLAG detection is completed, the HDLC controller detects CRC
Check and send results to HDLC control logic
report. HDLC control logic has two “methods”
“page complete” interrupt, i.e. the message is not correct.
An interrupt indicating that a CRC or
or other frame conditions were incorrect.
Instruct interrupt and either one to MBD
Interrupt. If correct, next message
MBC's RCVA register to indicate the starting point of
The microprocessor memorizes the contents of the data and then
The DHCP register is the starting point address of the current message.
is loaded. This allows the microprogram
is a routine that checks the first word of a message.
Directed. As mentioned above, this first word is
ADDRESS field and CONTROL field
Including de. That drop will be handed off
The above file is used to determine whether
field is examined. If for this drop
If handoff takes place, MBD is the main drawer.
Waiting to send handoff information.
stored during the page and start sending. Here MBD is (if the function processor of cooperation
(if the data is meaningful for FP)
Started the task of storing information on the dual port MBS.
do. In this case, MBD sets the RCVA counter to
At the same time, HDLC control logic is used to receive messages.
Create a message buffer so that you can also use
Use the DHCP register to access the If CRC or other frame conditions are normal
If it detects that the MBC is not
In response to receiving an erroneous message interrupt,
MBD sets the RCVA counter again for the preceding message.
Set to the end and false messages will be ignored. While data is being entered from DHB, MBD is
in background mode between receive interrupts.
and send messages at the appropriate time.
Load the message to be output to the point. the spot
If the flag byte in the data definition table is
Check what data is output by
and then get the output data. For this reason, MBD
Messages to be sent using DHCP register
remember. Message Batsuhua
Sage assembled and hand off to drop
Once the message instructing the user has received the message, the message will be sent.
It is done. MBD sent to XMTA register
Set the message start address to the WDCT counter,
Length of transmit block that commands MBC to start transmitting
Load each. Data is word count
The data is sent one byte at a time until the data is decremented to zero.
, and even if it is decremented to 0, it will receive its own transmission in reverse.
The HDLC control logic used is MBD interrupt logic.
Appropriate message interrupt (GMI) or
or cause a post-message interrupt (BMI). Figure 16 shows details of the 2901 microprocessor 180.
Shows a detailed block diagram. This thing is
Basically, it will be obvious to those skilled in the art. The figure is
Pipeline register 164 and microinstruction register
In addition to showing the connection with the coder 202, FIG.
The connections of the various bits supplied to the ALU are also shown.
The output of the microprocessor 180 is as shown in the figure.
Connected to Y-bus Y198. Similarly, the 2910 microsequence shown in Figure 15
No. 17 showing the block diagram of the
The figures will also be obvious to those skilled in the art. address multi
Input connections from plexer 172 and micropro
Has an output connection to the gram ROM160, which
is also illustrated in FIG. Illustrated in Figure 15, details in Figures 16 and 17.
The components shown work together to form the data highway.
A person skilled in the art can easily determine the manner in which the controller is provided.
It would be easy to understand. Basically, the microphone
The processor 180 performs the actual calculations and
Cross sequencer 162 is a pipeline register
MicroProgram from PROM160 via 164
Select data and instructions to be supplied to setter 180
do. The flowchart of MBD operation is 21st to 24th.
As shown in the figure. B. Data Highway Communication Card (MBC) As mentioned above, data highway communication card (MBC)
The card MBD is a data highway communication car.
Data highway and interface via HDMBC
face. Both are shared memory modules.
Data Highway Controller with Le MS
Configure. data highway communication card
MBC will be explained below. MBC card is
Physicalize MBD, Drops and Data Highways
Electrical interface between flat cables connected to
- Work as a face. Also, MBCB is Dorotsu
between the adapter and the data highway transceiver.
It is a logical link. MBC is listed below 5
It has two main functions. 1 MBD input/output interface 2 Protocol generation and error detection 3 Two-phase data encoding and decoding 4 Flat cable interface 5 Timekeeper/timer Input/output interface to the MBD
and will be explained below. MBC is MBD processor
enables parallel data transfer between 256 16
8 contained in bit word buffer memory
The W-bus interface registers are
Connect to This is shown in Figure 18. In the same figure
Connect to W-bus at 198 in Figure 15
At WD-bus 206 and point “Data I/O”
The buffer memory is shown at 204 when connected.
There is. The first two registers, i.e. buffer data
data register read (BDRR) 206 and
Tsuhua Data Register Write (BDRW)
208 is a buffer read and write buffer.
is a data register. Each is 16 bits wide
(1 word), buffer memory 204?
The word you just read or the buffer
Holds the next word to be written in memory 204
Ru. The next three registers are DHC address points
(DHCP) register 210, sending address counter
Counter register (XMTA) 212 and reception
Address counter register (RCVD) 21
It is 4. DHCP register 210 is set according to the routine.
Access to buffer 204 made during
is controlled only by MBD. By reading
read or write (or read or write)
(mixed), the address is automatically set for each access.
is incremented to Finally, DHCP is controlled by MBD.
It can be read backwards. Two more registers, namely XMATA212
and RCVA214 bytes the address value from MBD.
can be loaded. After loading,
These registers are used when sending and receiving messages.
Used by MBC to access Batsuhua 204
I am in a position to do so. XMATA212 is based on MBD.
RCVA cannot be read backwards with the following constraints.
214 can be read backwards. i.e. RCVA214
The content of is immediately after a proper message interrupt (GMI).
Valid only for reading. Read about this
When picking up, RCVA214 always picks up the newest one.
Contains the end address of the sent message.
Must be. Word counter or WDCT register 21
6 is also loaded from the W-bus. Its value is MBC
Then, in the next message, some words
Tell us what will be sent. Decrement of WDCT216
is sent to MBC as the message is sent.
It is done by twisting. WDCT is read by MBD
I can't do it. The last two registers 218 on the W-bus and
220 are status and instruction registers, respectively.
It is. CMSTAT218 and CMCMD
It is called 220. Each is 8 bits wide,
In general, MBD is MBC as if it were a peripheral device.
allows you to control. extremely noteworthy
In particular, MBC uses
MBC (all records on this interface
Enabling/disabling the register
I can do it. However, the status register 218
can be read by the MBD at any time. Micro engine sequencer shown on the left side of Figure 18
For details about sensor 230, refer to Fig. 19.
This will be explained later. Some of them have already been explained on the right.
This shows the element. For example, as mentioned above in connection with FIG.
digital phase lock loop 222 and the eleventh
This is the two-phase encoder 224 shown in the figure. 18th
Also shown in the diagram is a drop transceiver 72 and
Flat cable 22 connecting to data highway
Optoisolator used for connection with 6 and
Showed the driver. The internal mechanism of MBC is the job of transmitting and receiving data.
applied to. This includes 256 words but 2
Parallel data processing one word at a time from 04
Take out the page and send it sequentially using the flat cable 226.
There must be. MBC can be input in series at the same time.
Detect and receive message frames and extract data
And I have to memorize this in Batsuhua 204.
stomach. Therefore, MBC is a single-chip HDLC processor.
The protocol communication controller 228 is used. Already
As mentioned in this controller, sign
Chitx or Motorola controller
(Part number 2652) can be adopted. this
One of the main purposes of the chip is byte synchronization.
Ru. The chip detects special transitions in the received data stream.
The above can be achieved by recognizing the lag character.
Perform byte synchronization. HDLC also
Each device performs a “modem” function. i.e. byte width
Transform the data into bit-serial NRZ format data
This NRZ format data is then processed by the circuit shown in Figure 11.
The data is then transformed into output two-phase data. Iriki Nisho Day
data is converted to NRZ data by the circuit shown in Figure 12.
Then, byte is processed by HDL Tsuchip 228.
Converted to width data. All of this chip and its associated data registers
All are the “micro engine” shown in Figure 19 or
is controlled by the microsequencer 230.
Ru. Micro engine has 36 timing/controls
Control signals, test 16 status input lines,
and 8 stays, also called micro interrupts.
Enable priority interrupt structure for task request flags
make it possible. Figure 19 is a 24-bit microword
Details of the microengine are shown, including details of the microengine. The micro engine in Figure 19 is an MBD machine.
Exactly the same
It works on time. Adopted battle memo
In view of the re-access method, this
It is important for measurement. MBD is also microengineered
The buffer 204 is also accessed randomly.
However, the microengine then has two consecutive
access (2 reads or 2 writes)
Let's do it. Also, MBD is a combination of two or more consecutive crosses.
logically prohibited from doing so.
Ru. If concurrent access occurs, MBD is high
given priority. This ensures that if MBD
simultaneously (asynchronously) activates the buffer 204.
If the processor is accessed, two micro-engines
At least one of the accesses is valid. The microengine operates on seven bases, one at a time.
Perform the main sequence operation. That is, 1. Start of transmission 2. Setting of message start flag 3. Transmission buffer empty service 4. Transmission buffer full service 5. Check reception status 6. Termination of transmission service 7. Reset sequence The first six sequences are all micro-enabled.
When a specific micro-interrupt acts on the
will be activated. When the routine (sequence) is finished
Microengine “checks” pending vectors
do. If a pending vector exists, the micro
The engine is in service routine (furmware).
vector directly to the correct address (at
jump over If there are no micro interrupts,
Enter a “play” state. During this idle state, the next
A continuous check for micro interrupts is performed.
It will be done. One of the main components of the micro engine (Figure 19)
2911 micro program sequencer 230
It is. This is also an advanced micro device.
It is a part made by Ishizu. 2911 230 is micro
Microwave included in program ROM232
Address controller that operates in sequence according to instructions
It's a troller. Cascade control of two 2911s
to form an 8-bit address. The 2911 sequencer uses the following to obtain the output address.
You can choose from one of four sources:
Ru. 1 1 set of external direct inputs 231(D) 2 Stored in internal register (not shown)
External data from D input 3 4 word deep push/pop stack
234 4 Processed by microprocessor 235
The output of the preceding instruction 2911 is stored in the microprogram ROM 232.
supply the address of The output of ROM232 is the current microinstruction word.
Pipeline register 23 holding each part of
6-238. The following table shows the microphone
shows the definition of the program word field.
vinegar.

TABLE The remainder of FIG. 19 will be obvious to those skilled in the art. C Shared Memory (MBS) Data Highway Controller (DHC)
The third major component of the is the data highway shared memory (MBS) card. This card interfaces the feature processor with the highway processor MBD. It is the input/output buffer for the data highway controller DHC and provides expanded memory for the functional processor. Shared memory card is a dual port device configuration
It has 32K to 128K of RAM, with an additional 12K available for functional processor memory. Due to the dual port configuration, the DHC and functional processor can access shared memory simultaneously without interference. Shared memory is the only part of the data highway controller that its functional processors are concerned with. In other words, it is nothing but another card on which the functional processor relies for data. In the multibus card cage 90 (FIG. 6), the MBC, MBD, and MBS each consume one slot, even though only the MBC connects to the multibus. In other words, the data highway shared memory is used by the functional processors connected to the multibus, MBC, MBS, and
Make a connection between the MBC and the DHC bus. Shared memory has several important functions.
Its main function is to provide a storage location for the data that the functional processor should output to the highway. This data is read by the highway processor and transmitted to the data highway via the communications card. Similarly, shared memory stores data retrieved from the highway by the highway processor for use by the functional processors as needed. Therefore, the functional processor does not have to pay attention to the mechanics of communication, but only reads data from or inputs data into the shared memory as needed. The highway processor's job, on the other hand, is to translate the needs and instructions of the functional processor and execute them over the data highway. MBS cards are configured on extended multibus lines. RAM memory・
Arrays can be 16K or 64K on the same printed circuit board
Use dynamic RAM memory. Dynamics required on the same circuit board to expand the dual port portion of MBS from 32K bytes to 128 bytes
Additional RAM memory is required, and 128K of separate single-port RAM can be used for the functional processor. MBS receive memory is requested from both interface ports and
Interact with the port. Memory request is MBD
and from the functional processor simultaneously,
MBD takes precedence over functional processor. If MBD
is communicating with memory, and when a functional processor attempts to access memory, part of the memory logic tests the MBD's "hold memory" flag and locks the functional processor from starting until the MBD is completed. However, this lock will not occur if the bus busy signal is active. FIG. 20 is a block diagram of a dual port shared memory. The DHC bus, which contains both data and addresses, is MBD port 2 on the left side of the drawing.
The address and data lines of the multibus provided at 40 and including the functional processor port 250 are shown on the right side of the drawing. Addresses are generally processed by the elements shown at the top of the drawing, and data flow passes through the bottom of the drawing. Therefore, MBD port 240
The address received from is latched into latch 242 and used to access RAM 244, and the incoming data is latched into latch 246 and then used to access RAM 244.
Transferred to RAM244. On the other hand, data passing outward through MBD port 240 is latched by latch 248. Similarly, the functional processor
The address received from port 250 is receiver 2
52 and is sent to the RAM 24 via the MBD function/refresh address control 254.
Data received from the FP port 250 is latched into the functional data receiver 256 and then provided to the RAM. Data output to functional processor port 250 goes via byte output control 258 to functional data driver 260 for driving multibus lines. Control of MBD port 240 is
This is done by the following commands transmitted via the MBS command bus. 1 Increment address and read 2 Increment address and write 3 Read at current address 4 Write at current address 5 Increment address and write byte to lower half of word 6 Upper half of word at current address Write byte in half 7 Increment address, read, break lock 8 Increment address, write, break lock 9 Read at current address, break lock 10 Write at current address, break lock 11 Increment address Read, lock12 Increment address, write, lock13 Read, lock at current address14 Write, lock at current address All accesses are word accesses except for the two write byte instructions 5 and 6. be. The address used is contained in the MBS address latch 22, which is loaded by the MBD. In the second cycle after the read command, the MBD can output a command to enable the data read onto the DHC bus. Address latch 242 receives address signals from the MBD via the DHC address and data bus and latches the address if the MBS is addressed to the MBD. Address latch 242 is used for both reading and writing. For memory write operations, data information from the MBD is received via the DHC address and data bus and latched into latch 246 if the MBS is addressed to the MBD. For memory read operations, MBS
as the address and data source,
Data is transferred to the DHC address and data bus through MBS data out latch 248. FP port 250 interfaces with the functional processor via a multibus. Multival
Address lines are received using buffer 252. As is well known, multibus data lines connect receivers 252 and drives 260 for reception and transmission.
Each is buffered by The following signals are received from the multibus. 1 Write Memory Instruction 2 Read Memory Instruction 3 Bus Busy 4 Byte High Enable 5 Address Bit 0 Transfer Confirmation is a signal sent to the functional processor on this bus. The two ports of MBS have various 3 statuses.
Multiplexed using logic receiver enable. If the Multibus controls the memory bus, the Multibus' interface logic can communicate with the internal RAM memory. MBD
controls this memory bus.
The board's MBD logic can communicate with internal RAM memory. 8 Operation of Data Highway Processor FIG. 21 is a flowchart schematically illustrating the operation of the data highway processor (MBD). It consists of blocks 337, 337A and 338, shown in detail in FIGS. 22, 23 and 24, respectively. The logical starting point of the flowchart is MBD 3
1 of 2 communication cards MBC721 in 30
This is the point in time when a "proper message interrupt" is received from someone. This signal is as shown in 280-283
Formed by MBC 72. 280 and 2
Once the start and end flags (FIG. 7c) are detected at 82, the process is performed at 283 in a known manner.
A CRC check is performed. MBD first retrieves the message at 330 from MBC 72 pointing to GOOD MSG. Therefore, both highways and both MBCs are always on-line, providing redundancy without the need for complex switching such as designating one as first or second. In particular, in the present invention, the data highway 2
The physical location of the main cable can be changed, so even if there is a localized noise source, for example,
Only one cable is affected. Since receipt of a valid message interrupt at 330 means that the final message has been received, there is no need for the drop to increment the address field and send a recovery handoff message. Drop then checks at 331 whether the message just sent is its own message. If not, check 332 to see if the last message received was a handoff for this drop. That is, it checks whether the token of the own drop is in the A field of the last received message. If not, the data highway processor returns at 342 to the operating state it was in when it detected the "good message interrupt" at 330 above. With the token recognized, at 333
The first action performed by the DHC is to recognize whether a TDM or Democratic mode transmission is occurring by checking the M bit of the C field.
In either case, it is only formed in the next A field 334. That is, the A field, which is an index to the lotus allocation table, is incremented to provide the correct token for the next drop in the transmission sequence. If the mode is changed to TDM mode, the next TDM message to be assembled in the output buffer, which will be described later, is supplied from 335. If there is no message in the buffer, an empty handoff is sent at 336, ie, a message containing only the token and start and end bytes. The next step in TDM mode is the creation of the next TDM message. This will be described in detail later with reference to FIG. 22. The previously received data is then processed at 338, as described with reference to FIG. Finally, with all output buffers loaded and all received data processed, preparation operations can be performed at 339. These operations include maintaining the system clock signal and reconciling the bus assignment table in the event of any conflicts between timekeepers. 340
The processor returns to block 337 to create the next TDM message, as shown in FIG. This is because TDM messages require the functional processor to
This is because it is updated every time there is a notification of any change in the data to be reported in the TDM message. In contrast, the next democratic message does not require such an update. A substantially similar process unfolds if the message to be sent is in democratic mode. That is, the A field is updated at 334, the message is provided at 335A, there is no message in the buffer 336, an empty handoff, and the next message is sent at 337.
Created at A. If it is determined at 331 that a valid message interrupt is associated with the drop's own message, the drop sets the timer to 110 at 341.
Set to microseconds and see if any subsequent activity appears on the bus. If it appears, we can assume that the next drop received the token correctly. If not, the drop again increments the token to the next drop by incrementing the A field and sends a recovery handoff message at 341A. This operation can be repeated until the indicator cycles through the bus assignment table and indicates that the drop being transmitted is likely an error generator. In this case, the drop in question can be taken offline. If timer activity is correctly detected, the drop returns from the interrupt state, for example at 342, to its previous state. As already mentioned, parts of the inventive system can be implemented in a redundant manner. Typically, redundant data highway coaxial cables, redundant communication interfaces and transceivers are provided, all of which feed the data highway controller bus for access by the data highway processor. The communication interface (MBC) checks the CRC field of each message received as described above and removes it if the message is correctly decoded. The communication interface thus forms the "good message interrupt" mentioned above. Therefore, this is a useful feature since the transceiver that provides the correct message interrupt first will be accessed by the data highway processor.
Both transceivers are always on-line, and both data highways can be designated as one primary highway, one secondary highway, or one primary highway, as is often the case in the prior art.
Rather than designating the other as a secondary highway, they are used interchangeably. Therefore, both can be used sequentially, without an explicit switch from one to the other, which would cause synchronization problems, message loss, etc. This scheme also increases the bit error rate of the system since random errors on one coax highway do not typically occur at the same time as random errors on the other coax highway. A. TDM Mode Message Formation As already mentioned, FIG. 22 shows the following TDM message formation. First, in 343, 1/
Consider the loading parameters that indicate the points you want to send in 10 second intervals. Some points are transferred from the 1/10 second starting point of the data definition table (DDT) in shared memory (29th
(Fig.), similarly at 344, "1 second data", ie, data transmitted every second, is transferred from the 1 second starting portion of the DDT to the communication buffer. Therefore,
For example, any message transmitted from the output buffer upon detection of the above-mentioned symbol may include data transmitted at 1/10 second intervals, such as the value of a process control variable used in a feedback loop;
and typically a relatively small number of variable values that do not change rapidly or are transmitted at one second intervals, such as values that are only needed for CRT graphics updates. B Formation of Democratic Mode Message FIG. 23 shows the following process of forming a democratic mode message. One shot
If a message is requested, request/
The zero bit in the DDT flag field is checked at 345 to determine if a modified or regular message is being sent. If this bit is set, a one-shot message should be sent at 346, and the required one-shot data is simply sent at 347 from the shared memory to the MBC output buffer. If this buffer is full at 348, processing stops. If it is not full and some messages have to be sent as shown in 349, the origin flag
Block 345 is accessed again. If the flag field 0 bit is not set, the receive point in the DDT is manipulated for the R bit 350. If set, it means that the request/change message is sent at 351, and the data requested by the drop that sent the request is sent to the output buffer at 352. If the buffer is full, processing stops at 353, and if the buffer is not full, block 345 is accessed again. Finally, if the R bit is not set at 350, a normal message has been requested. If the functional processor sends the normal message to be sent at 354 to the output FIFO, the processor checks the output FIFO.
In this case, the message is transferred to the output buffer at 355. Again, if the buffer is full, processing stops; otherwise, block 345 is accessed again. C. Processing of received messages The priority order of MBD operations is to first make sure that all TDM messages have been created;
Next, it makes sure that all democratic messages have been created, and finally processes all received messages. Therefore, the operation of the data highway cannot be interrupted for reasons such as decoding of received messages. This is also an advantage of the distributed processing system of the present invention. There is no need to interrupt the operation of the entire system; the highway continues to operate regardless of any errors that may occur in the drop. Hereinafter, a method for decoding a received word by the system of the present invention will be explained with reference to FIG. The first operation performed at 300 is an examination of the word's control or C field. If the M bit is set at 301, it means that we are in time division multiplex mode. The processor then retrieves the system identifier (SID) from the data recognition array (DRA) at 302.
Explore. If the identifier is present, it means that the content of the message is of interest to this particular drop, ie, this information is needed by the particular drop's functional processor in performing its local control operations. If the SID is not found,
For example, an alarm check can be accessed at 303. This will be described later (FIG. 28). If SID exists in DRA,
A search of the DDT table at 304 confirms the correct location of the data. The data is then stored in the appropriate location on the MBS at 305 and the running timer is reset at 306. This timer is used to measure the time between updates of a particular data point, and also indicates to the functional processor (via a bit in the status word) that a particular value is no longer valid. then 30
This is done by sending a change in status word at 7. At 309, the next element of the message is accessed. Check bit 15 of the SID to see if the data word is analog or digital. If digital, only the status word is relevant, as already mentioned in connection with Figure 8b; if analog, the status word is relevant as well as the analog value (Figure 8c), which is two words. have sex. Therefore, to determine the number of bytes to skip before searching for the next SID, the bits of the SID are used.
Use 15. The final SID of each transmission is detected at 310 by checking each SID to see if it is a "match." To give the processor a way to verify that the final SID was present,
This word is inserted by MBC after CRC check. 300,3 if M bit is not set
11, the democratic mode is processed. 312 again to check if the data word is relevant to the local processor.
, the SID is searched during DRA. The next two most significant bits of the SID are examined at 313 to determine what type of democratic message was received. If bit 15 is 1, this means it is a one-shot message in 314;
The data in the AA field (Figure 8) is determined by the search for DDT at 315.
Stored in location in MBS. The next entry is then processed at 316. If bit 15 is 0, democratic mode
This means that the message is a regular message or a request/change message to the origin 317. At 318, the processor searches the DDT to determine if it is the origin specified in the message. If not, the message has no relevance at all and the next entry is processed at 319. If so, check bit 14 to determine whether the message is a request/change message or a normal message at 320.
If bit 14 is set, the message is a normal message and is sent to the input FIFO at 321-322. If bit 14 is not set, the message is sent in 323 as a request/change message or as a one-shot message.
It is a message. If the word count is 0,
The request is for one shot at 324, and one shot bit 0 in the flag DDT field is set at 325. As described in cutlet 326, upon detecting a zero in the flag field DDT, the MBD creates a message for transmission as described in connection with FIG. If the word count is not zero, it means that the message is a request/change message, as shown at 327. The displacement field is then used to find the position of the data to be changed,
AD field data indicates new data at 328. At 329 the next element is processed. 9 CLOCK CONTROL - DETAILS In distributed data processing systems, it is necessary to provide a means for clocking the system so that events that later prove to be significant can be analyzed historically. That is, assume that the circuit breaker is tripped. In order to determine the cause of this trip, the events leading to the trip of the circuit breaker must be reconstructed. Therefore, it goes without saying that the data in each drop must be synchronized to establish accurate correlations between the various events. For example, if a simple crystal oscillator is used in each drop, changes over time, such as changes in temperature, will affect the individual clocks differently. Therefore, one feature of the present invention is to synchronize the clocks of each drop in the entire system at the end of each 100 millisecond time frame. Each local drop copies the master clock signal and reflects its value by adjusting each drop's internal clock. The system is thus repeatedly synchronized. FIG. 25 shows an aspect of this synchronization. Near the end of the democratic mode, the final message to be sent in this mode is detected. This detection is accomplished by expiring a 100 millisecond internal timer placed in each drop. (The internal timer has some degree of accuracy, with a worst case deviation of 250 microseconds from the exact time within each 100 millisecond period). “U” in the control field if the final message is to be sent.
A bit is set at 316 and a message is sent at 362. Upon detection of the U bit in the drops 363, the drops detect that time division multiplexing mode is about to begin, and each drop takes a "snapshot" of the internal clock at 364.
To this end, each drop causes the current value of the internal clock to be stored in a register. The time keeper
The first three drops to send in TDM mode, send the own clock value, ie the result of the snapshot, at 365. This value is inserted after the control field of the message frame transmitted by each timekeeper. In addition to the "normal" data that the timekeeper drops transmit when performing their assigned local processing functions, the S bits appearing in the control word are sent to timekeepers A, B, and C, respectively, by 01 and 10. and 11 to indicate that you are about to send a snapshot. Every drop containing a timekeeper averages the snapshot values of two adjacent timekeepers at 366 and adjusts their respective internal clocks at 367 to match this average value. At 368, TDM mode continues. That is, the next drop following the timekeeper transmits its data. In the preferred embodiment, the internal clock includes 1 millisecond and 125 microsecond clocks for increased accuracy. 10 bus allocation Naturally, not necessarily 1/10 of each drop
The amount of data to be sent every second is not necessarily the same. It is also obvious that some data must be sent more frequently than others, such as data about process variable values that change rapidly and are used in feedback loops, which of course requires frequent transmission. Need to send. Other data that does not change frequently may need to be sent less frequently. In a preferred embodiment of the invention, some data is transmitted at 1 second intervals and other data is transmitted at 1/10 second intervals. Additionally, each drop can be provided with multiple time slots for data transmission in TDM mode. That is, in many cases, drops access the data highway as often as once every 100 milliseconds, and each time a given drop can be found in a bus assignment table that determines the sequence in which it transmits different data. Figures 26a and 26b illustrate this. Chapter 26b
The figure shows one of the bus assignment tables that is almost the same in democratic and TDM modes.
In either mode, a simple pointer, the A field of each word, points to a slot in the bus assignment table, so that any drop located in this slot in the assignment table is the next drop to transmit.
As is clear from the figure, some drops appear multiple times. These drops are therefore drops that transmit different data at different times within each 100 millisecond period. Figure 26a shows an example of data transmitted sequentially by a single drop. For example, in the first slot of the first 100 millisecond time frame, data items A, B, C, and D are transmitted;
Items X, Y, Z and W are transmitted in the slots of the TDM part. During the next 100 millisecond interval, items A, B, and C are repeated in the first slot and X, Y are repeated in the second slot. However, item E replaces item D, and both items U and V replace Z and W. In the third slot, F replaces E, P and Q replace U and V.
replaces. Ten such transmissions are made, and after one second has elapsed, the values transmitted in the first interval, ie A, B, C, D followed by X, Y, Z, W, are repeated. Therefore, the bus assignment table of FIG. 26b is an extremely important piece of information. Both tables are stored with each drop and are constantly updated by the timekeeper. Each drop is 1/8 of two bus allocation tables
is sent every second in one of the democratic mode messages. Therefore, the bus allocation table is fully updated in each drop's memory every 8 seconds. If there is any objection to the received bus assignment table, the drop will "vote" on it. That is, normally two of the timekeepers agree and the third timekeeper is ignored. In democratic mode, the bus assignment table is cycled repeatedly until the remainder of the 100 millisecond period is filled, but in time division multiplex mode, the bus assignment table ends when the bus assignment table has been cycled through. 11 Control Fields The use of control fields in each message frame has already been mentioned in several places.
We consider this problem below with respect to one particular location. FIG. 27 shows an example of how the control field bits change over one 100 millisecond period. The time division multiplex mode is shown in the left half of the diagram, and the democratic mode is shown in the right half. The control field begins with a "D" in the address field at the beginning of time-sharing mode. This is a pointer to the position in the bus assignment table of the last democratic mode message to be transmitted. At this time, the control field becomes X1100001. The second, M, bit is set since TDM mode has already begun. The third, or T, bit indicates the mode of the next message. The next set of messages are all TDM, so this bit remains set. The S bit is 01. This is the first
1 Since it is a TDM message, time keeper A
It is now its turn to send the snapshot. In the next two messages, when timekeepers B and C send, the S bit becomes 10 and then 11. For each transmission, the address field is incremented and the pointer moves according to the bus assignment table until the value "TDM" is reached. In addition, the above value "TDM"
is the value of the pointer corresponding to the highest numbered drop in the bus allocation table. When this value is reached, the T bit is unset because the next message will be in democratic mode. Since the value D now becomes an address field, the end position of the democratic message can be picked up and the democratic mode begins. As is clear from the right half of the diagram, the message mode is
Since it is not TDM, the M field will be 0. Again the transmission continues, proceeding according to the bus assignment table by incrementing the address field. As can be seen, the T and U bits are set in the control byte of the final democratic frame with address field 2 in the illustrated example. A brief explanation of the other bits in the control field is as follows. P is A and C combined
This is a parity bit that indicates the parity of the field. Although the value is illustrated as X, the address and control fields are not limited here. That is, "D", "TDM", or "N" appears. H
The bit is set by the data highway controller to indicate that this particular message is a recovery handoff because the previous handoff was not answered. That is, each data highway controller searches for messages following its own message transmission and, if not detected, increments the address field and retransmits the message, and this retransmission is determined by setting the H bit. Instruct what to do. Although this was discussed above in connection with the timekeeper, the timekeeper also sends a bus from a given point in the bus allocation, along with transmissions by the first timekeeper, to a number of restart at the starting point in TDM mode. Setting the R bit indicates that the timekeeper detects an abnormally long period of inactivity as described above and restarts the bus with this message. 12 Alarm Handling As previously mentioned, in the present invention, some data is sent repeatedly, while other data is sent on request, such as by a one-shot request. It may also be desirable to call the attention of other drops regarding the data. for example,
This is the case with drops configured as man/machine interfaces. A typical example is a video display data terminal device, which can be used to display the values of various variables along with the measurement locations during the process under control. Typically, when an operator selects a specific part of the process to monitor,
The local software creates a corresponding data recognition array, and from then on the DHC selects only those points from the highway that are recognized by comparing the system ID to the stored value in the data recognition array. however,
The operator must also be provided with an indication that an alarm limit has been exceeded at some point during the process, for example. Each message then also includes a status field indicating whether an alarm limit has been exceeded [compare with typical known systems in which the operator terminal is configured as a peripheral to a host computer with direct access to central memory. Although there are many reasons to avoid a host computer in a distributed processor control system, there is easy access to the entire database. According to the invention, such access is provided by a mixed mode communication format. ].
The SID of the above status message is DRA
Each drop, whether present or not, is inspected and appropriate action is taken to keep the operator aware of the alarm condition. FIG. 28 shows the alarm processing stage. At 370, the system ID SID is retrieved from the data highway message. Once the SID is found, the message's status word will be set at 374 to match the stored status mask.
It is compared with the preceding status word using an AND operation. Note that this status word was previously received for the data point in question. If any changes are observed at 378, the system ID is placed in the MBD's new state change FIFO for access by the functional processor at 380. If there is no change,
After normal message processing as described above, the next system ID is simply accessed at 381. If the system ID is not present in the DRA and bit 7 of the status word is set, indicating at 382 that a point is in alarm, then
At 384, the system ID is copied to the alarm FIFO, which is checked periodically by the feature processor. Otherwise only the next SID is accessed. When a point is found to be in an alarm condition, the function processor typically performs the following sequence of actions. The alarm FIFO is first accessed and a one shot request is sent to the highway at 386 for access by the origin drop, which then sends at 388 any additional information about the point or system element in alarm. The drop is then provided with any attributes associated with the point at 390. This attribute is displayed on the operator terminal monitor screen and indicates which points are in alarm. In addition to the actual value and the limits to which it is compared, for example, an English-language designation identifier of the point can also be displayed. Regardless of how many drops send one-shot messages, all drops are provided with all information about the point of error at the same time. This is in contrast to systems where each message must be seen and responded to separately. 13 Configuration of shared memory Figure 29 shows the shared memory system 39 of the present invention.
The structure of 1 is shown. The purpose of the configuration is, for example, to
The object of the present invention is to provide a means by which records 392 can be easily inspected to see if they contain data portions that should be utilized by a functional processor. The message can then be broken down into its component parts to determine its exact meaning. For example, each message 392
A system ID is provided as part of the data recognition array (DRA) 394 and is used to access the data recognition array (DRA) 394. If there is a non-zero field, it means that the federation's functional processor is concerned with this data portion. The value “Local ID” placed in the DRA 394 is then used to create a Data Definition Table (DDT) containing flags and data field size information.
Index 396. Data definition table 396 also stores points indicating locations in shared memory where data records 398 themselves are stored. Record 398 is the status of each point
Contains ID, other information, limit values, English description, and related attributes. The system ID of the point in alarm condition can be stored separately in alarm buffer 399. Conclusion We have described a distributed process control system that employs a number of new technologies. New techniques include employing a mixed-mode data transmission scheme, in which a portion of each cycle is used for time-division multiplexing operations, in which each data acquisition or control drop is repeated over a connecting line. Given the opportunity to send data, the remainder of each cycle, i.e.
In the “democracy” operating mode, other commands,
You can send data requests, etc. Each data acquisition unit includes a first processor that selects and supplies data important to the local processor to the data highway, the highway cooperating with a second functional processor or other functional processors such as a third, fourth, etc. and perform any functions such as process control input/output required for that location. The two interface with each other via dual port shared memory, which has many advantages as described above. This distribution of processing functionality provides a completely transparent data base throughout the system, eliminating the requirement found in known systems employing a central or host computer. It has many advantages such as reliability, modularity, and ease of understanding and use.
Perhaps the most important advantage is that the system can operate even if some of the distributed processing functions are not active. The system is synchronized by three timekeepers configured as data acquisition units, eliminating the need for separate signal lines such as clock control lines.
A single, simple and easily configured redundant coaxial cable is required to serpentinely connect the separate data acquisition points. The accuracy of information reception is improved by utilizing a two-phase encoding method for data transmission in the system of the present invention, and by dividing this two-phase code into subparts by a phase lock loop circuit and weighting these subparts. It was also explained that .

[Brief explanation of the drawing]

FIG. 1 is an imaginary notch slope diagram of a factory employing the distributed process control system of the present invention, FIG. 2 is a more detailed notch slope diagram of the process control system of the present invention, and FIG. 3 is a diagram of the present invention. A diagram of the blocks that make up the system; Figure 4 is a block diagram showing the components that make up a typical drop; Figure 5 is a detailed diagram of a typical drop showing the use of redundant highway components; Figure 6 is a typical drop diagram. Physical block diagram of target drop diagram, Figure 7 consisting of Figures 7a, 7b and 7c.
FIG. 8 shows a block diagram of a typical data highway transmission block and message; FIG. 8, consisting of FIGS. 8a-8d, shows a block diagram of a transmitted data message; and FIG. 9 shows various data encoding methods. Figure 10 is a diagram containing a series of curves illustrating the data encoding technique and message protocol utilized in the present invention; Figure 11 is a two-phase encoding scheme employed in the present invention. FIG. 12 is a circuit diagram of a digital phase lock loop circuit used to correctly decode two-phase encoded data. FIG. 13, consisting of FIGS. Figure 14 is a waveform diagram illustrating the weighting scheme; Figure 14 is an illustration of the clock control logic to keep the various drops properly synchronized with each other; Figure 15 is a block diagram of the data highway processor (MBD); 1
Figure 6 is a block diagram of the microprocessor used in the data highway processor (MBD), Figure 17 is a block diagram of the companion microsequencer unit used in the data highway processor (MBD), and Figure 18. is a block diagram of the data highway communication circuit (MBC), and Figure 19 is a block diagram of the microengine in the data highway communication (MBC) card.
Figure 20 is a block diagram of the dual port shared memory used for communication between the functional processor and the data highway processor unit; Figure 21 is the overall flow sheet of the MBC operating sequence; Figure 22; is a block diagram related to TDM message creation that supplements the block shown in FIG. 21, and FIG. 23 is a second block diagram showing how to create a democratic message.
A block diagram supplementing the block diagram in Figure 1. Figure 24 shows how a received message is decoded. A block diagram supplementing the block diagram in Figure 21. Figure 25 shows how the system clock is fully updated. FIG. 26 is a diagram showing the transmission sequence of the timekeeper when
Figure 6a shows the sequence of sending several messages at intervals of 100 milliseconds for a given drop and the possible changes in the actual messages sent, and Figure 26b shows an example of the bus assignment table. Figure 27 is a diagram showing how control fields change in time division multiplexing mode and democratic mode, Figure 28 is a flow sheet showing how status words, alarm bits are used, and Figure 29 is a shared memory FIG.

Claims (1)

[Scope of Claims] 1. A distributed process control system comprising a plurality of drops and a data highway bus connecting the drops in parallel, wherein each drop sends a data message on the data highway bus. a data highway processor connected to said bus via transmitting/receiving means for transmitting and receiving data messages from said bus; and a functional processor connected to a plurality of system elements for performing local data collection and control operations. and a dual port memory connected between the data highway processor and the functional processor to enable them to communicate and to enable each processor to operate independently; transmitting a token signal over the bus that coordinates the transmission operations of each data highway processor so that more than one data highway processor does not access the data highway bus for transmission; has an identifier portion identifying the system element to which the data message relates and a status portion containing information regarding the status of the associated system element; a first analysis means for analyzing the identifier portion of the message to determine whether information from these system elements is necessary for local control operations of the associated functional processor; and a status portion of the received data message. a second analysis means for analyzing the data message to determine whether an alarm condition exists in the system element; and means for transmitting to a dual port memory for selective access by the associated functional processor regardless of whether it is necessary for local control operations of the system. 2. The system of claim 1, wherein the data highway processor includes means for sending a request requesting additional information regarding the system element in which the alarm condition exists. 3. third analysis means for determining whether a change in status has occurred by analyzing the status portion of data messages that the data highway processor successively receives from system elements of other drops; 2. The system of claim 1, further comprising means for transmitting data messages with changed status to a dual port memory for selective access by an associated functional processor.