JPH048030A - Harmless bit error rate test method and device - Google Patents

Abstract

PURPOSE: To measure the bit error rate(BER) of a digital communication circuit by using a second channel having a less number of bands by providing a method and device by which the BER of the data flow of the communication circuit can be decided accurately without replacing the data flow. CONSTITUTION: A microprocessor 2 transmits three CRCs 3, 4, and 6 to a downstream testing device from an upstream testing device through a second communication channel at every 1/10 second and the downstream testing device calculates and compares the received CRCs similarly to the upstream testing device, counts uncoincidence as block errors, and separately stores the block errors. The block error rate of the three block lengths are obtained by dividing the count value of the errors by the total number of 1/10-sec blocks. Since only a bit rate of 240 bits/sec is required for transmitting the CRC information through the second channel, the bit rate of 960 bits/sec has time to synchronize the two testing devices to each other and to confirm the synchronization between the devices and, in addition, to detect the error of the CRC information.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for non-disturbing measurement of bit error rate (BER) in a data stream in a digital communication circuit.

[Prior Art] A commonly used method for measuring errors in digital communication circuits is described in US Pat. No. 3,315,228.
3596245.3725860.3760354.3
B24548.3914740 and 4428076.

This method uses a code or pattern generator to inject known test patterns into the digital communication circuit. The pattern received at the other end of the circuit is compared to a synchronized known test pattern generated at the other end. This comparison gives a count of bit errors. BE
R is determined by dividing the number of bit errors by the total number of bits observed.

US Pat. No. 4,234,954 describes a method in which signal level impairments are detected, integrated, and used to estimate the BER of a communication circuit.

US Pat. No. 4,397,020 describes a method in which cyclic redundancy codes (CRCs) are used to detect errors in communication circuits. The CRC is calculated at the end of the transmission for 4632-bit blocks and is embedded in the data. At the end of reception, the CRC is recalculated on the same data block and compared with the embedded CRC, and any discrepancies indicate the presence of an error.

[Problem to be Solved by the Invention 1 The prior art has two main drawbacks: either the communication circuit is put out of use (referred to as an unused state test), or it requires data to replace it (referred to as a fault test). I was suffering from one or the other.

U.S. Pat. Nos. 4,710,924 and 4,713,810 disclose BE
We are proposing a technology to store R results at a remote measurement point. This technique includes means for isolating faulty sections of the communication circuit. However, this technique does not show how to measure BER.

US Pat. No. 3,916,379 and US Pat. No. 47,363
No. 77 proposes a non-disturbing test method using a second digital communication circuit. Synchronization information and an error code or cyclic redundancy code (CRC8) are transmitted from one end of the digital communication circuit to the other end via the second channel. In the prior art, these codes, computed remotely and uniformly partitioned into block lengths of contiguous bits of data, are compared with codes computed independently by the received digital information, and each discrepancy is It is accumulated as an error. In US Pat. No. 3,916,379, the BER is estimated from the number of block errors. However, this estimate rapidly loses accuracy as the block error rate (BLER) approaches 1 (ie, at high BER and/or long block lengths). Furthermore, if the block length is reduced to accommodate a high BER, the bandwidth of the second channel is required to carry a proportionately increasing number of error codes.

This is a disadvantage since the bandwidth of the second channel is usually limited by price and reliability.

SUMMARY OF THE INVENTION The present invention provides a method and apparatus for accurately determining the BER of a data stream in a digital communications circuit without discontinuing circuitry or replacing the data stream. Overcoming the shortcomings of the prior art.

[Operation] The method involves comparing block check codes computed on blocks of data sampled at two points in a digital communication circuit and using this comparison to determine the bit error rate.

(A block check code is a data word derived by operating a specific function on a data block when the data word length is generally much smaller than the block length. If the data block is replaced for some reason (e.g. due to an error) (Block check code calculations almost always lead to different results when must be installed to ensure that the index check code is computed for the bits of the index. A second communication channel is used to transmit block check codes generated at one or both locations to a common location for comparison. This second channel is also used to transmit synchronization signals.

At the point where the block check codes are compared, a count of the number of mismatches and the number of codes to be compared is kept. The number of mismatches divided by the total number of block check codes in a given time interval gives an accurate estimate of the block error rate.

Assuming that bit errors have a Gaussian distribution (that is, all bits have the same error probability), the block error rate is expressed by the following equation using a given BER.

BLER=1−(1−BER)”2E (1) Here, 5IZE is the number of bits included in each block.

Solving this equation for BER, BER=1- (1-BLER)""' (2) BER
It is clear that an accurate estimate of the block error rate is required to provide a good measure of the block error rate. From equation (1), as BER and block length increase, BLER approaches 1 (
(saturation). As the BLER saturates, it is necessary to wait a long time until a sufficient amount of error-free blocks are accumulated to obtain an accurate representation of the long-term block error rate.

In order to avoid saturating the BLER when the BER increases, the block length needs to be reduced. The present invention allows the block length to be reduced without increasing the rate at which block check codes are transmitted, thus minimizing the bandwidth required for the aforementioned second channel. This is accomplished by computing a block check code for a block consisting of samples of data bits rather than all data bits. More specifically, each of these blocks consists of data sampled within a certain time period. The sampled data consists of non-contiguous sections of the data stream and/or isolated bits taken at periodic or random intervals according to a sampling algorithm. These block lengths determined by the sampling algorithm and time interval are determined so that the block error rate does not saturate. FIG. 1 shows a generalized algorithm for sampling the data bits of a communication circuit and dividing the sampled data into blocks from which a block check code is calculated.

The fact that the block check code is computed and compared to samples of the channel data rather than to all data means that, assuming a Gaussian distribution of errors, each bit in the sample is as erroneous as every other bit in the channel data. has a probability of occurring, so it does not affect the bit error rate determined using equation (2).

This method uses non-Gaussian distributed errors (i.e., burst errors), assuming that the error distribution is uncorrelated with sampling.
It is also suitable for determining the BER in the case of It is useful to reduce the block length and recalculate the BER to ensure that the calculated BER is accurate. If the recalculated BER is substantially different from the original BER, this indicates the presence of a burst error.

The block length can be reduced sufficiently as long as the calculated BER remains unchanged.

Embodiment An apparatus for unimpeded bit error rate testing according to a preferred embodiment is shown diagrammatically in FIG. Each test device shown in FIG. 3 includes the block elements shown in FIG. In addition, synchronization circuitry (as described in the aforementioned US Pat. No. 4,736,77, referenced in this application) is provided to the two test devices to identify common points in the digital data stream and initiate observations. This ensures that the block check code is calculated on a block of data bits representing the same location in the data stream transmitted on the digital communication circuit at each of the observation points in FIG.

FIG. 4 shows a block diagram of a preferred embodiment of the invention. A timing circuit 1 generates sample pulses synchronized with the digital data to be monitored. One output of the timing circuit generates one pulse for each data bit, and the other output generates 15 pulses to be monitored.
It outputs one pulse for every bit, and the third output outputs one pulse for every 223 bits to be monitored. The timing circuit also outputs a block signal every 1/10 seconds, which is used to latch the outputs of the three CRC generators and clear the generators for the next data block. Following the block signal, microprocessor 2 receives the latched CR from the three CRC generators.
Load C information.

The first CRC generator 3 calculates a 12-bit CRC word over all bits of the data to be monitored (sampling is not working). The second CRC generator 4 receives every 15th bit of the data to be monitored from the corresponding sampler 5 and calculates a 6-bit CRC word for these bits.

The third CRC generator 6 receives every 223rd bit of the data to be monitored from the corresponding sampler 7 and calculates a 6-bit CRC word for these bits.

The effect of the sampling used for the second and third CRC generators is that the second CRC is calculated only 1/15th the amount of the CRC generated by the first CRC generator, and the third
CRC is calculated by an amount 1/223 of the first CRC. The CRCs generated by the first, second and third CRC generators are
These will be referred to as "medium block" and "small block" CRC.

Every 1/10 seconds, three CRCs are transmitted by the microprocessor 2 from the upstream test device to the downstream test device via the second communication channel (see FIG. 3). The downstream test device calculates the CRC similarly to the upstream test device and compares the generated CRC with the CRC received from the upstream test device. Mismatches are counted as block errors, and CRC errors for each small, medium, and large block are accumulated separately. Block error rates for each of the three block lengths are obtained by counting these errors by the total number of 1/10 second blocks. The microprocessor converts the block data error rate to a bit error rate using the second equation.

If the number of blocks with errors is not too large or the number of blocks without errors is insufficient for a given block length, the BE derived from their block error rates is
It is important to note that R measurements are statistically unreliable. For example, it may be advantageous to define a reliability or selection criterion that requires at least 10 erroneous blocks and at least 10 non-erroneous blocks to be accumulated before calculating the BER. be.

If the accumulated block error statistics for two or more block lengths satisfy reliability criteria, BER measurements derived from different block lengths are compared. If the measurements are essentially the same, the errors in the digital communication circuit will be predominantly Gaussian and the BER results will agree to a high degree. If the BER result derived from one block length is significantly different from the BER derived from other block lengths, the microprocessor determines that there was a burst error in the communications circuit during the test. do. In either case, the smallest block length that satisfies the reliability criteria described above is selected by the microprocessor as giving the best estimate of the actual BER.

Unless it is necessary to determine whether the error distribution in the digital communication circuit under test is Gaussian or non-Gaussian, always calculate the BER based on the smallest CRC block length that satisfies the reliability criteria. It is sufficient. At low bit error rates, this means that the large block CRC information is first used to calculate the BER, and as soon as enough block errors have accumulated for each block length, it is switched to the medium block and finally This means that you can switch to small blocks.

The calculation method used allows the microprocessor to perform the first (
2) It may be difficult to accurately calculate the BER using Eq. For low block error rates, B
A highly accurate approximation of ER is given by:

BER=BLER/5IZE (3) This is 10-
Although the result differs by 5% from that given by equation (2) at the block error rate of ', this is still a good enough approximation at a low block error rate.

The 1/10 second block period and various CRC block lengths used in the preferred embodiment of the invention allow digital communication circuits transmitting data at 1.544 megabits per second (standard American Tl rate) to transmit data at 1200 bits per second. It should be mentioned that this was selected by analysis using two communication channels. To transmit the CRC information over the second channel, simply 24
Since only 0 bits are required, the 960 bits per second can be used to synchronize and verify the two test instruments, as well as to detect (and, if necessary, correct) errors in the CRC information. be. It is essential to detect at least a CRC word error in order to prevent an error in the second channel from turning into an error in the digital communication circuit under test.

The selection of the CRC polynomial is based on its ability to discriminate between erroneous and non-erroneous blocks.

A CRC polynomial of order n produces an n-bit CRC word that has the ability to detect a combination of (2''-1)/(2'') of all possible errors in the block being computed. A 12th order CRC polynomial is used for large blocks (calculated for each bit) in order to have a high degree of agreement so that errors occurring in the digital communication circuit under test will not go undetected. be done. This allows to accurately determine the seconds in which the error occurred, an important measurement in the telecommunications industry. Medium and small blocks use a 6-bit CRC to save bandwidth on the second channel. At such small block lengths, high precision is important because they represent samples of statistical data and are used to calculate the BER, and it is usually necessary to know the precision with a high degree of agreement. isn't it.

Advantages of the Invention The main advantage of the invention is that it makes it possible to measure the BER of a digital communication circuit using a second channel that has essentially less bandwidth than the prior art.

Moreover, this measurement method is achieved without disturbance and without replacing the data transmitted by the circuit. This method minimizes "downtime" during repairs and allows routine servicing of digital communication circuits.

Those skilled in the art will recognize various modifications that may be made in connection with the present invention as described below.

1. Using different intervals between sampled bits.

2. Using different sample algorithms.

3. Use different block lengths.

4. Adjusting the sampling algorithm and/or pronk length according to the actual or predicted block error rate.

5. Using different numbers for CRC blocks.

6. Random sampling of data.

7. Use fans to dissipate heat generated by circuits.

8. Using different CRC polynomials.

9. Using a block check code in a format other than CRC; 10. Incorporating a second communication channel into the digital communication circuit under test.

11. Using the block check code mismatch information to derive other performance measures representative of BER.

12. Divide the sampled data bits in the block based on the number of sampled data bits rather than time interval when using a randomized sampling algorithm.

In any case, the scope of the present invention is not limited to the preferred embodiments described above, but includes the spirit and concept of the claims.

[Brief explanation of the drawing]

1 is a diagram showing a generalized sampling algorithm and block formation according to the present invention; FIG. 2 is a diagram showing a typical ER test method according to the prior art; FIG. 3 is a diagram showing a non-fault testing method; FIG. 4 is a block diagram of a preferred embodiment of the present invention.

Claims (1)

1. Repeatedly and intermittently sampling data bits in a data stream according to a sampling algorithm at upstream and downstream monitoring points to generate pairs of upstream and downstream sampled data bits; dividing the set of sampled data bits upstream into upstream blocks of a predetermined block length; and dividing the set of sampled data bits downstream into downstream blocks of a predetermined block length. and calculating a downstream block check code in a downstream block; sampling data bits at upstream and downstream monitoring points and dividing the set of upstream and downstream sampled data bits into upstream and downstream blocks to ensure that a block check code is calculated; synchronizing the computation of upstream and downstream block check codes and in upstream blocks formed from data bits indicating the same location in the data stream as data bits forming the downstream block for which the downstream block check code is computed; Comparing the calculated upstream block check code and downstream block check code to determine the number of mismatches, and determining a bit error rate or a representative quantity based on the number of mismatches. A method for measuring the bit error rate of data flow in digital communication circuits. 2. The method of claim 1, wherein the repeated and intermittent sampling of data bits is periodic sampling. 3. Claim 1, wherein the step of calculating block check codes for upstream and downstream blocks is cyclic redundancy codes (CRCs).
Or the method described in 2. 4. The step of determining the bit error rate is a step of calculating the block error rate based on the number of discrepancies between upstream and downstream block check codes, and determining a representative amount from the bit error rate or block error rate. 4. The method according to any one of claims 1 to 3. 5. The method of claim 4, further comprising the step of selecting block lengths for upstream and downstream blocks based on reliability criteria. 6. means for repeatedly and intermittently sampling data bits in the data stream according to a sampling algorithm at upstream and downstream monitoring points to generate a pair of upstream and downstream sampled data bits; means for dividing the set of data bits into upstream blocks of a predetermined block length; means for dividing the set of downstream sampled data bits into downstream blocks of a predetermined block length; means for calculating a block check code; and an upstream block check code is calculated in an upstream block consisting of data bits representing the same position in the data stream as the data bits forming the downstream block for which the downstream block check code is calculated. Sampling of data bits at upstream and downstream monitoring points, partitioning of the set of upstream and downstream sampled data bits into upstream and downstream blocks, and upstream and downstream block checking to ensure that means for synchronizing the computation of a downstream block check code with an upstream block check computed on an upstream block formed from data bits representing the same location in the data stream and data bits forming the downstream block for which the downstream block check code is computed; A data flow in a digital communication circuit comprising: means for comparing a code and a downstream block check code to determine the number of mismatches; and means for determining a bit error rate or a representative quantity based on the number of mismatches. A device that measures the bit error rate of 7. The apparatus according to claim 6, wherein the repeated and intermittently sampled data bit sampling means is periodic sampling means. 8. The apparatus according to claim 6 or 7, wherein the means for calculating block check codes in upstream and downstream blocks is cyclic redundancy code (CRCs) calculation means. 9. The means for determining the bit error rate includes means for calculating the block error rate based on the number of discrepancies between upstream and downstream block check codes, and determining a representative quantity from the bit error rate or block error rate. 9. Apparatus according to any of claims 6 to 8, comprising means. 10. The apparatus of claim 9, further comprising means for selecting block lengths of upstream and downstream blocks based on reliability criteria. 11. The plurality of upstream sampled data bits and the downstream sampled data bits such that the plurality of upstream sets of sampled data bits correspond to the plurality of downstream sets of sampled data bits. repeatedly and intermittently sampling data bits in the data stream according to a plurality of sampling algorithms at upstream and downstream monitoring points to generate a plurality of sets; and any of the upstream sets of sampled data bits. or an upstream block having a predetermined block length such that the predetermined block length for one is different from the predetermined block length for the other upstream sets of sampled data bits. splitting each of the plurality of upstream sets of sampled data bits; and calculating an upstream block check code at an upstream block for each of the plurality of upstream sets of sampled data bits. , the predetermined block length for any one of the downstream sets of sampled data bits is different from the predetermined block length for the other downstream sets of sampled data bits; dividing each of the plurality of downstream sets of sampled data bits into a downstream block having a predetermined block length such that: calculating a downstream block check code at the downstream block; and downstream block checking for each of the plurality of upstream sets of sampled data bits and the corresponding downstream set of sampled data bits. To ensure that the upstream block check code is computed in an upstream block consisting of data bits representing the same position in the data stream as the data bits forming the downstream block in which the code is computed, the upstream and downstream sampling data bits at monitoring points of and dividing the set of upstream and downstream sampled data bits into upstream and downstream blocks;
synchronizing the computation of upstream and downstream block check codes; comparing each upstream block check code of the upstream set of sampled data bits with its corresponding downstream block check code of the downstream set of sampled data bits to determine the number of data bits; , determining a selected criterion; and selecting one of the plurality of upstream sets of sampled data bits and a corresponding downstream one of the sampled data bits based on the selected criterion. and determining a mismatch between a selected upstream set of sampled data bits and a corresponding downstream set of sampled data bits. How to measure bit error rate.