JPH0480130U - - Google Patents

Info

Publication number
JPH0480130U
JPH0480130U JP12441490U JP12441490U JPH0480130U JP H0480130 U JPH0480130 U JP H0480130U JP 12441490 U JP12441490 U JP 12441490U JP 12441490 U JP12441490 U JP 12441490U JP H0480130 U JPH0480130 U JP H0480130U
Authority
JP
Japan
Prior art keywords
power supply
constant current
control transistor
current control
sawtooth wave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12441490U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12441490U priority Critical patent/JPH0480130U/ja
Publication of JPH0480130U publication Critical patent/JPH0480130U/ja
Pending legal-status Critical Current

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  • Control Of Electrical Variables (AREA)
  • Dc-Dc Converters (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例による鋸歯状波発
生回路を示すブロツク図、第2図は定電流制御用
トランジスタにPNP形トランジスタを使用した
他の実施例を示すブロツク図、第3図は鋸歯状波
を発生しない休止期間中は定電流回路の動作を停
止するようにした本考案のさらに他の実施例を説
明する回路図、第4図は従来回路を示すブロツク
図である。 図において、1は直流電源、2はコンデンサ、
3はトランジスタ、4,5は抵抗、6は定電圧ダ
イオード、7は放電用スイツチ、8はフローテイ
ング電源を示す。なお、図中、同一符号は同一、
または相当部分を示す。
Fig. 1 is a block diagram showing a sawtooth wave generating circuit according to one embodiment of this invention, Fig. 2 is a block diagram showing another embodiment in which a PNP type transistor is used as the constant current control transistor, and Fig. 3 is a block diagram showing another embodiment in which a PNP type transistor is used as the constant current control transistor. FIG. 4 is a circuit diagram illustrating still another embodiment of the present invention in which the operation of the constant current circuit is stopped during a rest period in which a sawtooth wave is not generated. FIG. 4 is a block diagram showing a conventional circuit. In the figure, 1 is a DC power supply, 2 is a capacitor,
3 is a transistor, 4 and 5 are resistors, 6 is a constant voltage diode, 7 is a discharge switch, and 8 is a floating power supply. In addition, in the figure, the same reference numerals are the same,
or a significant portion.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電源電圧に近似する鋸歯状波形のピーク電圧を
得るための回路構成で、定電流制御用トランジス
タのベース電流をフローテイングした電源より得
たことを特徴とする鋸歯状波発生回路。
A sawtooth wave generation circuit has a circuit configuration for obtaining a peak voltage of a sawtooth waveform approximating the power supply voltage, and is characterized in that the base current of a constant current control transistor is obtained from a floating power supply.
JP12441490U 1990-11-26 1990-11-26 Pending JPH0480130U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12441490U JPH0480130U (en) 1990-11-26 1990-11-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12441490U JPH0480130U (en) 1990-11-26 1990-11-26

Publications (1)

Publication Number Publication Date
JPH0480130U true JPH0480130U (en) 1992-07-13

Family

ID=31872066

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12441490U Pending JPH0480130U (en) 1990-11-26 1990-11-26

Country Status (1)

Country Link
JP (1) JPH0480130U (en)

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