JPH0479008A - High aspect groove embedding method - Google Patents

High aspect groove embedding method

Info

Publication number
JPH0479008A
JPH0479008A JP19369090A JP19369090A JPH0479008A JP H0479008 A JPH0479008 A JP H0479008A JP 19369090 A JP19369090 A JP 19369090A JP 19369090 A JP19369090 A JP 19369090A JP H0479008 A JPH0479008 A JP H0479008A
Authority
JP
Japan
Prior art keywords
insulating material
high aspect
conductor
groove
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19369090A
Other languages
Japanese (ja)
Other versions
JP2807065B2 (en
Inventor
Ichiro Kudo
一郎 工藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP19369090A priority Critical patent/JP2807065B2/en
Publication of JPH0479008A publication Critical patent/JPH0479008A/en
Application granted granted Critical
Publication of JP2807065B2 publication Critical patent/JP2807065B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Magnetic Heads (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Physical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To embed an insulating material into a high aspect groove without any void by applying a negative bias voltage only to this conductor when embedding the insulating material into the high aspect groove formed on a substrate by a bias sputtering method. CONSTITUTION:A negative bias voltage -V is applied to a conductor 10 on a substrate 1 and by executing sputtering to an insulating material molecules 12 while setting the substrate 1 at 0 potential the insulating material molecules 12 is accumulated on the exposing faces of the conductor 10 and an insulation pattern 2. Then, Ar<+> collides a simultaneously accumulated insulating material 4 so as to cut off one part of the surface of the insulating material 4. In such a case, the insulating material 4 accumulated on the upper or side surface of the conductor 10 is cut off by the collision of Ar<+> and the Ar<+> is not almost collided to an insulating material 4b accumulated on the bottom of a high aspect ratio 11. Therefore, speed for accumulating the insulating material 4 onto the bottom of the high aspect groove 11 is much higher than the other, and the high aspect groove 11 starts embedding the insulating material 4b from the bottom. Thus, the insulating material can be easily embedded into the high aspect groove while reducing the void.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、薄膜磁気ヘッドなどの基板上に絶縁されて小
ピンチで渦状や綿状などに形成された導体の間のハイア
スペクト溝に、導体間を絶縁する絶縁材をバイアススパ
ッタ法で埋め込むハイアスペクト溝埋め込み方法に関す
る。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a high aspect groove between conductors that are insulated on a substrate such as a thin film magnetic head and formed in a spiral shape or a cotton shape with a small pinch. This invention relates to a high aspect groove filling method in which an insulating material for insulating between conductors is filled using a bias sputtering method.

〔従来の技術〕[Conventional technology]

磁気テープなどの磁気記録媒体の高密度記録化に伴い、
磁気記録媒体に情報を記録し、再生する磁気ヘッドは益
々高性能なものが要求されている。この磁気ヘッドの性
能は、磁気ギャップに磁界を発生させるコイルの巻数や
、磁気ギャップにおける磁路の長さなどで大きく左右さ
れることから、コイル巻数をより多くし、磁路長をより
短くするなどして、磁気ヘッドの高性能化を図る様々な
工夫がなされている。
With the increasing recording density of magnetic recording media such as magnetic tape,
Magnetic heads for recording and reproducing information on magnetic recording media are required to have increasingly high performance. The performance of this magnetic head is greatly affected by the number of turns of the coil that generates the magnetic field in the magnetic gap, the length of the magnetic path in the magnetic gap, etc., so the number of turns of the coil is increased and the length of the magnetic path is made shorter. Various efforts have been made to improve the performance of magnetic heads.

例えば、強磁性体の基板上にWi11jiコイルやat
膜ココアの薄膜パターンを積層したi!膜磁気ヘッドの
構造例と、その製造例を第7図乃至第18図を参照しな
がら説明する。第7図及び第8図に示す薄膜磁気ヘッド
はフェライトの強磁性体の基板(1)上に、酸化アルミ
ニウム等の第1の絶縁パターン(2)、銅等の薄膜コイ
ルパターン(3)、酸化アルミニウム等の第2の絶縁パ
ターン(4°)、センダスト等の薄膜コアパターン(5
)、及び薄膜コイル引き出しパターン(6)、(7)を
部分的に重ねて積層し、その上に低融点ガラス(8)で
非磁性体の保護板(9)を固定したものである。薄膜コ
イルパターン(3)は第1の絶縁パターン(2)上に銅
等の導体(lO)をドライエンチングやメツキで渦巻状
に被着して形成され、この上に第2の絶縁パターン(4
°)が形成される。薄膜コアパターン(5)は薄膜コイ
ルパターン(3)のコイル中心部から基板(1)の先端
まで延びるパターンで形成され、その内側端部(5a)
は基板(1)に接続され、外側端部(5b)は第1の絶
縁パターン(2)上に形成されて、この外側端に第1の
絶縁パターン(2)の厚みにて磁気ギャップGが形成さ
れる。
For example, Wi11ji coil or at
i! is a laminated film pattern of membrane cocoa. An example of the structure of a film magnetic head and an example of its manufacture will be described with reference to FIGS. 7 to 18. The thin-film magnetic head shown in FIGS. 7 and 8 has a first insulating pattern (2) made of aluminum oxide, etc., a thin-film coil pattern (3) made of copper, etc. on a ferrite ferromagnetic substrate (1), A second insulation pattern (4 degrees) such as aluminum, a thin film core pattern (5 degrees) such as Sendust
), and thin film coil extraction patterns (6) and (7) are partially overlapped and laminated, and a non-magnetic protection plate (9) is fixed thereon with low melting point glass (8). The thin film coil pattern (3) is formed by depositing a conductor (lO) such as copper in a spiral shape on the first insulating pattern (2) by dry etching or plating, and on top of this is formed a second insulating pattern (2). 4
°) is formed. The thin film core pattern (5) is formed in a pattern extending from the center of the coil of the thin film coil pattern (3) to the tip of the substrate (1), and its inner end (5a)
is connected to the substrate (1), the outer end (5b) is formed on the first insulating pattern (2), and a magnetic gap G is formed at this outer end by the thickness of the first insulating pattern (2). It is formed.

上記磁気ヘッドの性能を高くするには、薄膜コイルパタ
ーン(3)の巻数を多くして発生する磁界強度を高める
ことや、薄膜コアパターン(5)と基板(1)と磁気ギ
ャップGで形成される磁路の長さを短くすることなどが
知られている。第8図に示す′Vr#膜コイルパターン
(3)は単層で、これの導体(10)の電流容量で決ま
る断面積を変えること無く、m層のままで薄膜コイルパ
ターン(3)の巻数を多くすると、薄膜コイルパターン
(3)の半径部分での長さしが大きくなり、その分だけ
磁路が長くなって、磁気ヘッドの高性能化が難しくなる
。また、磁路を長くすること無く、薄膜コイルパターン
(3)の巻数を多くする手段として、例えば第9図に示
すように、薄膜コイルパターン(3)を複層に形成する
ことが知られている。しかし、このように薄膜コイルパ
ターン(3)を複層に形成すると、薄膜コイルパターン
(3)を1層毎に形成する製造工程が必要で、磁気ヘッ
ドの製造工程数が倍増し、製造コストが高くなる不具合
がある。
In order to improve the performance of the magnetic head, it is possible to increase the number of turns of the thin film coil pattern (3) to increase the strength of the generated magnetic field, or to increase the strength of the magnetic field formed by the thin film core pattern (5), the substrate (1), and the magnetic gap G. It is known to shorten the length of the magnetic path. The 'Vr# film coil pattern (3) shown in Figure 8 is a single layer, and the cross-sectional area determined by the current capacity of its conductor (10) remains unchanged, and the number of turns of the thin film coil pattern (3) remains m layers. If the number of magnetic heads is increased, the length of the thin film coil pattern (3) at the radius becomes larger, and the magnetic path becomes longer by that amount, making it difficult to improve the performance of the magnetic head. Furthermore, as a means of increasing the number of turns of the thin film coil pattern (3) without lengthening the magnetic path, it is known to form the thin film coil pattern (3) into a multilayer structure, as shown in FIG. 9, for example. There is. However, forming the thin film coil pattern (3) in multiple layers in this way requires a manufacturing process to form each thin film coil pattern (3) layer by layer, doubling the number of manufacturing steps for the magnetic head and increasing the manufacturing cost. There is a problem with the price increasing.

また、磁路を長くすること無(薄膜コイルパターン(3
)の巻数を増大させる別の手段として、第10図に示す
ように、薄膜コイルパターン(3)の導体(10)の断
面積を変えずに、その幅Wを短く、高さHを大きくし、
幅Wを短くした分だけ導体(10)のピッチPを小さく
して、薄膜コイルパターン(3)の長さLの半径部分に
単層に形成できる導体(10)の本数を多くすることが
知られている。この場合、導体(10)の幅Wに対する
高さHの比であるアスペクト比を高くし、導体(10)
の間に形成された溝(11)の幅Pに対する深さHのア
スペクト比を高くする程、薄膜コイルパターン(3)の
巻数を多くすることができるので、導体(10)と@ 
(11)は益々ハイアスペクト比化される傾向にある。
In addition, there is no need to lengthen the magnetic path (thin film coil pattern (3
) As shown in Fig. 10, another means of increasing the number of turns of the conductor (10) of the thin film coil pattern (3) is to shorten the width W and increase the height H without changing the cross-sectional area of the conductor (10) of the thin film coil pattern (3). ,
It is known that by reducing the pitch P of the conductors (10) by the amount that the width W is shortened, the number of conductors (10) that can be formed in a single layer in the radius portion of the length L of the thin film coil pattern (3) can be increased. It is being In this case, the aspect ratio, which is the ratio of the height H to the width W of the conductor (10), is increased, and the conductor (10)
The higher the aspect ratio of the depth H to the width P of the groove (11) formed between the conductor (10) and the @
(11) tends to have an increasingly high aspect ratio.

ハイアスペクト比化された上記溝(11)をハイアスペ
クトfi (11)と称し、このハイアスペクト溝(1
1)への第2の絶縁パターン(4′)の絶縁材の埋め込
み方法を説明する。
The high aspect ratio groove (11) is referred to as high aspect fi (11).
The method of embedding the insulating material of the second insulating pattern (4') in 1) will be explained.

ハイアスペクト溝(11)への絶縁材の埋め込みはスバ
ンタ法で行われ絶縁用材料を塗布して形成する方法が多
いが、コスト高となるのが通常で、これは第11図乃至
第13図に示すように行われている。第11図に示すよ
うに、基板(1)上の第1の絶縁パターン(2)上にハ
イアスペクト比化された導体(lO)を形成したものを
スパンタリング装置にセットして、基板(1)に向けて
酸化アルミニウム等の絶縁材分子(12)をスパフタリ
ングする。すると絶縁材分子(12)は導体(lO)と
第1の絶縁パターン(2)の露出面に様々な方向から飛
来して堆積されていく。この場合、絶縁材分子(12)
は、導体(10)と第1の絶縁パターン(2)の露出全
面に均等な厚さでは堆積せず、絶縁材分子(12)は導
体(10)の上面の角部C,には略270の最も広い角
度の方向から飛来して、ここに最も多く付着し、導体(
10)と第1の絶縁パターン(2)のコーナ部分Coに
は略90°の狭い角度の方向からしか絶縁材分子(12
)が飛来せず、ここに最も付着し難い、その結果、絶縁
材分子(12)の堆積がある程度進行すると、第12図
に示すように、堆積された絶縁材(4)の内の導体(1
0)の上面角部の絶縁材(4a)がひさし状に膨らみ、
ハイアスペク)a(11)への絶縁材分子(12)の侵
入を妨げるようになる。そして、絶縁材分子(12)の
堆積がさらに進行すると、第12図の鎖線に示すように
、隣接する2つの導体(10)  (10)の上面角部
でひさし状に膨らんだ絶縁材同士が接触して、ハイアス
ベク)i (11)への絶縁材分子(12)の飛来を完
全に妨げる。すると、ハイアスペクト溝(11)を埋め
つつある絶縁材(4b)の中に空洞(13)が形成され
、この空洞(13)は絶縁材分子(12)の堆積進行後
も残されて、第13図に示すように、最終的にハイアス
ペクト溝(11)に埋め込まれた絶縁材(4b)の中に
、大小様々な不定形の空洞(13)が形成されることが
あった。このような空m (13)はハイアスペクトI
l! (11)のノ1イアスペクト比が高くなるほど顕
著に発生して、導体間の絶縁不良の原因や、第2の絶縁
パターン(4′)の上にWi膜ココアパターン5)を形
成するときの熱に対する導体(10)の耐熱性を劣化さ
せて、磁気ヘッド製造の歩留まりを悪くする原因になっ
ている。
The insulating material is often filled into the high aspect groove (11) using the Svanta method, which involves applying an insulating material, but this method is usually expensive, as shown in Figures 11 to 13. This is done as shown in . As shown in FIG. 11, a high aspect ratio conductor (lO) formed on the first insulating pattern (2) on the substrate (1) is set in a sputtering device. ) is sputtered with insulating material molecules (12) such as aluminum oxide. Then, the insulating material molecules (12) fly from various directions and are deposited on the exposed surfaces of the conductor (lO) and the first insulating pattern (2). In this case, the insulation molecule (12)
is not deposited to a uniform thickness over the entire exposed surface of the conductor (10) and the first insulating pattern (2), and approximately 270 insulating material molecules (12) are deposited on the corner C of the upper surface of the conductor (10). The conductor (
10) and the corner portion Co of the first insulating pattern (2), the insulating material molecules (12
) do not fly and are the most difficult to adhere to here.As a result, when the deposition of insulating material molecules (12) progresses to a certain extent, the conductor ( 1
0) The insulating material (4a) at the top corner swells into a canopy,
This prevents the insulating material molecules (12) from entering the high aspect ratio a (11). As the deposition of the insulating material molecules (12) further progresses, the insulating material bulges out like a canopy at the top corners of the two adjacent conductors (10) (10), as shown by the chain lines in FIG. This contact completely prevents the insulating material molecules (12) from flying into the Hyasbek)i (11). Then, a cavity (13) is formed in the insulating material (4b) filling the high aspect groove (11), and this cavity (13) remains even after the deposition of insulating material molecules (12) progresses. As shown in FIG. 13, irregularly shaped cavities (13) of various sizes were sometimes formed in the insulating material (4b) finally embedded in the high aspect groove (11). Such a sky m (13) is high aspect I
l! The higher the aspect ratio of (11), the more conspicuous the occurrence, which may cause poor insulation between conductors or when forming the Wi film cocoa pattern 5) on the second insulation pattern (4'). This deteriorates the heat resistance of the conductor (10) against heat, causing a decrease in the yield of manufacturing magnetic heads.

そこで、最近は上記ハイアスペクトm (11)に絶縁
材(4)を、より空洞少なく埋め込む方法として、絶縁
材分子(12)をスパッタリングするときに、基板(1
)全体に負のバイアス電圧を印加して、基板(1)の導
体(10)に向けて不活性イオン、例えばアルゴンイオ
ン(以下、Ar+と称する)を衝突させるバイアススパ
ッタ法が開発され、実行されている。このバイアススパ
ッタ法で上記ハイアスペクトm (11)に絶縁材(4
)を埋め込む方法を、第14図乃至第16図を参照して
説明する。
Therefore, recently, as a method of embedding the insulating material (4) in the high aspect m (11) with fewer cavities, when sputtering the insulating material molecules (12), the substrate (1
) A bias sputtering method has been developed and implemented in which a negative bias voltage is applied across the substrate (1) and inert ions, such as argon ions (hereinafter referred to as Ar+), are bombarded towards the conductor (10) of the substrate (1). ing. By using this bias sputtering method, the high aspect ratio m (11) is coated with the insulating material (4).
) will be explained with reference to FIGS. 14 to 16.

第14図に示すように、基板(1)上に第1の絶縁パタ
ーン(2)と導体(10)を形成したものをスパッタリ
ング装置にセントするときに、導体(10)を含む基板
(1)全体に一定の負バイアス電圧−■を印加する。こ
の状態で絶縁材分子(12)をスパッタリングし、同時
にスパッタリング装置にAr+を供給すると、Ar+は
基板(1)と導体(10)の負バイアス電圧−■で導体
(10)と第1の絶縁パターン(2)の露出面に様々な
方向がら衝突する。Ar+は反応性がほとんど無くて、
導体(lO)や第1の絶縁パターン(2)の露出面に堆
積せず、導体(10)と第1の絶縁パターン(2)の露
出面に堆積するのは絶縁材分子(12)だけで、Ar+
は堆積した絶縁材(4)に衝突する。このAr+の衝突
エネルギーで堆積した絶縁材(4)の一部が飛び出して
、絶縁材(4)の表面が削られる。
As shown in FIG. 14, when a substrate (1) with a first insulating pattern (2) and a conductor (10) formed thereon is placed in a sputtering apparatus, the substrate (1) containing the conductor (10) A constant negative bias voltage -■ is applied throughout. In this state, when insulating material molecules (12) are sputtered and Ar+ is supplied to the sputtering device at the same time, Ar+ is applied to the conductor (10) and the first insulating pattern at a negative bias voltage of −■ between the substrate (1) and the conductor (10). (2) The exposed surface is collided with from various directions. Ar+ has almost no reactivity,
Only the insulating material molecules (12) are deposited on the exposed surfaces of the conductor (10) and the first insulating pattern (2) without being deposited on the exposed surfaces of the conductor (lO) or the first insulating pattern (2). , Ar+
impinges on the deposited insulation (4). A part of the deposited insulating material (4) flies out due to the collision energy of this Ar+, and the surface of the insulating material (4) is scraped.

Ar+は絶縁材分子(12)と同様に導体(1o)の上
面隅部C1に最も飛来し易く、導体(10)の上面隅部
に堆積した絶縁材(4)を最も多く削る。従って、絶縁
材分子(12)が堆積される割合より、これをAr+が
削る割合を小さく設定しておけば、導体(10)と第1
の絶縁パターン(2)の露出面に絶縁材(4)が比較的
平均して堆積されていく。すなわち、絶縁材(4)の堆
積とAr”衝突による絶縁材削りは同時進行するが、仮
に第15図の鎖線に示すように、先に絶縁材(4)が少
し堆積した時点で、A r ” 衝突を行なわせると、
導体(10)の上面隅部C1のひさし状に膨らんだ絶縁
材(4a)が最も多(Ar+衝突で削られて、その厚さ
が他と同程度になり、全体の絶縁材(4)の厚さが均一
化される。これと同しことが絶縁材堆積とAr+衝突の
同時進行が行われ、その結果、ハイアスペクトfi (
11)に絶縁材(4)が比較的良好に埋め込まれていき
、第16図に示すようにハイアスペクト溝(11)に埋
め込まれた絶縁材(4b)から空洞が無くなる。
Like the insulating material molecules (12), Ar+ most easily flies to the top corner C1 of the conductor (1o), and removes the most amount of the insulating material (4) deposited at the top corner of the conductor (10). Therefore, if the rate at which the insulating material molecules (12) are removed by Ar+ is set to be smaller than the rate at which the insulating material molecules (12) are deposited, the conductor (10) and the first
The insulating material (4) is deposited on the exposed surface of the insulating pattern (2) in a relatively average manner. In other words, the deposition of the insulating material (4) and the insulating material scraping due to Ar'' collision proceed simultaneously, but if a small amount of the insulating material (4) is deposited first, as shown by the chain line in FIG. ” If you cause a collision,
The insulating material (4a) that bulges like an eave at the top corner C1 of the conductor (10) is the most heavily shaved off by the Ar+ collision, and its thickness is the same as that of the others, making it the largest part of the entire insulating material (4). The thickness is made uniform.The same thing occurs when insulating material deposition and Ar+ collision proceed simultaneously, resulting in high aspect fi (
The insulating material (4) is embedded relatively well in the high aspect groove (11), and as shown in FIG. 16, no cavity is left in the insulating material (4b) embedded in the high aspect groove (11).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところで、上記バイアススパッタ法でハイアスペクト溝
(11)に絶縁材(4)を埋め込む場合、Ar+は導体
(10)の上面と側面に堆積される絶縁材(4)を削る
と共に、第1の絶縁パターン(2)の露出面でハイアス
ペクトm (11)の底に堆積される絶縁材(4b)も
削る。そのため、導体(10)とハイアスペクト溝(1
1)のハイアスペクト比を高くするほど、後述するよう
にハイアスペクト溝(11)に絶縁材(4)を空洞無く
埋め込むことが難しくなっている。
By the way, when embedding the insulating material (4) in the high aspect groove (11) using the bias sputtering method described above, Ar+ scrapes the insulating material (4) deposited on the top and side surfaces of the conductor (10), and also removes the first insulating material (4). The insulating material (4b) deposited on the bottom of the high aspect ratio m (11) is also removed on the exposed surface of the pattern (2). Therefore, the conductor (10) and the high aspect groove (1
The higher the high aspect ratio (1) is, the more difficult it becomes to fill the high aspect groove (11) with the insulating material (4) without any voids, as will be described later.

例えば、第17図に示すように、導体(10)の幅Wと
溝幅Pが数μmで、高さHが5μm程度以上に高くした
ハイアスペクト比化された導体(1o)におけるハイア
スペクト溝(11)に絶縁材(4)をバイアススパッタ
法で埋め込むと、第18図に示すように、埋め込まれた
絶縁材(4)に空洞(13)が形成されることがあった
。つまり、ハイアスペクト溝(11)の底から堆積する
絶縁材(4b)の堆積速度と、導体(10)の上面隅部
C1や側面に堆積する絶縁材(4a)の堆積速度に大差
が無くて、絶縁材堆積がある程度進行すると、!@17
図の鎖線に示すように、ハイアスペクト溝(11)の底
から堆積される絶縁材(4b)が十分成長する前に、隣
接する導体(10)  (10)の上面隅部C五の堆積
絶縁材同士が接触して、その真下に空洞(13)が形成
され、これがそのまま残ることがあった。このような空
洞(13)は、ハイアスペクトfi (11)のハイア
スペクト比が高くなるほど多く、かつ、大きなものが発
生し、これが原因でハイアスペクトjlli (11)
と導体(10)の尚更のハイアスペクト比化が難しくな
っており、薄膜磁気ヘッドの尚更の性能改善を難しくし
ている。
For example, as shown in FIG. 17, a high aspect groove in a high aspect ratio conductor (1o) in which the width W of the conductor (10) and the groove width P are several μm, and the height H is approximately 5 μm or more. When the insulating material (4) was embedded in the insulating material (11) by bias sputtering, a cavity (13) was sometimes formed in the embedded insulating material (4), as shown in FIG. In other words, there is not much difference between the deposition rate of the insulating material (4b) deposited from the bottom of the high aspect groove (11) and the deposition rate of the insulating material (4a) deposited on the top corner C1 and side surfaces of the conductor (10). , once the insulation material deposition has progressed to a certain extent, ! @17
As shown by the chain line in the figure, before the insulation material (4b) deposited from the bottom of the high aspect groove (11) has grown sufficiently, the insulation material deposited on the upper surface corner C5 of the adjacent conductor (10) (10) When the materials came into contact with each other, a cavity (13) was formed directly beneath it, and this sometimes remained as it was. Such cavities (13) are more numerous and larger as the high aspect ratio of high aspect fi (11) increases, and this causes high aspect jlli (11)
This makes it difficult to further increase the aspect ratio of the conductor (10), making it difficult to further improve the performance of the thin film magnetic head.

それ故に、本発明の目的とするところは、ハイアスペク
ト溝のハイアスペクト比が高くなっても、このハイアス
ペクト溝に絶縁材を空洞無く確実に埋め込むことのでき
るバイアススパッタ法によるハイアスペクトa埋め込み
方法を提供することにある。
Therefore, an object of the present invention is to provide a high aspect a filling method using a bias sputtering method that can reliably fill an insulating material into a high aspect groove without voids even if the high aspect ratio of the high aspect groove becomes high. Our goal is to provide the following.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成する本発明の技術的手段は、基板上に絶
縁されて形成された導体の間の小溝幅のハイアスペクト
溝に絶縁材をバイアススパッタ法で埋め込むに際し、前
記導体にのみ負のバイアス電圧を印加することである。
The technical means of the present invention to achieve the above object is that when an insulating material is embedded in a high aspect groove with a small groove width between conductors formed insulated on a substrate by a bias sputtering method, a negative bias is applied only to the conductor. It is to apply a voltage.

〔作用〕[Effect]

基板上に絶縁されて形成された導体にのみ負のバイアス
電圧を印加して、導体間のハイアスペクト溝にバイアス
スパッタ法で絶縁材分子を堆積させ、かつ、堆積させた
絶縁材に不活性イオン例えばAr+を衝突させると、A
r+は負バイアス電圧の印加された導体へと飛来して、
導体に堆積されつつある絶縁材にだけ衝突し、その一部
を削る。従って、ハイアスペクト溝の底に堆積する絶縁
材がAr+の衝突で削られる割合が大幅に少なくなり、
ハイアスペクト溝の底からの絶縁材の堆積速度が増しで
、その分ハイアスペクト溝に絶縁材を埋め込む速度が早
くなり、埋め込まれた絶縁材中に空洞が形成される割合
が少なくなって、ハイアスペクト溝の尚更のハイアスペ
クト比化を可能にする。
A negative bias voltage is applied only to the conductors formed insulated on the substrate, and insulating material molecules are deposited by bias sputtering in the high aspect groove between the conductors, and inert ions are applied to the deposited insulating material. For example, when Ar+ collides, A
r+ flies to the conductor to which negative bias voltage is applied,
It only hits the insulation material that is being deposited on the conductor, shaving off some of it. Therefore, the rate at which the insulating material deposited at the bottom of the high-aspect groove is scraped away by Ar+ collisions is significantly reduced.
The rate of deposition of insulation material from the bottom of the high-aspect trench increases, the speed at which the insulation material is filled into the high-aspect trench becomes faster, and the rate of formation of cavities in the buried insulation material decreases. This enables the aspect groove to have an even higher aspect ratio.

〔実施例〕〔Example〕

以下、本考案の具体的実施例を第1図乃至第6図を参照
しながら説明する。
Hereinafter, specific embodiments of the present invention will be described with reference to FIGS. 1 to 6.

同図は、第17図に示した薄膜磁気ヘッドにおける基板
(1)の第1の絶縁パターン(2)上に、高いハイアス
ペクト比で形成された導体(10)の間のハイアスペク
ト溝(11)に、酸化アルミニウム等の絶縁材(4)を
バイアススパッタ法で埋め込む本発明方法を説明するた
めのものである。
This figure shows high aspect grooves (11) between conductors (10) formed with a high aspect ratio on the first insulating pattern (2) of the substrate (1) in the thin film magnetic head shown in FIG. ) is used to explain the method of the present invention in which an insulating material (4) such as aluminum oxide is embedded in the substrate by bias sputtering.

本発明は第1図に示すように、スパッタリング装置で基
板(1)上の導体(1o)に絶縁材分子(12)をスパ
ッタリングする際に、導体(1o)にだけ負バイアス電
圧−■を印加して、基板(1)に向けて不活性イオン例
えばAr+を衝突させることを特徴とする。このような
導体(1o)への負バイアス電圧−■の印加は、第7図
に示す薄膜コイル引き出しパターン(6)(7)を介し
て行えばよい。
As shown in FIG. 1, the present invention applies a negative bias voltage -■ only to the conductor (1o) when sputtering insulating material molecules (12) onto the conductor (1o) on the substrate (1) using a sputtering device. The method is characterized in that inert ions such as Ar+ are caused to collide with the substrate (1). The negative bias voltage -■ may be applied to the conductor (1o) through the thin film coil lead-out patterns (6) and (7) shown in FIG.

導体(10)に負バイアス電圧−■を印加し、基板(1
)をゼロ電位にして絶縁材分子(12)のスパッタリン
グを行うと、第2図に示すように、導体(10)と第1
の絶縁パターン(2)の露出面に絶縁材分子(12)が
飛来して堆積する。この堆積と同時進行して、堆積する
絶縁材(4)にAr”が飛来して衝突し、絶縁材(4)
の表面一部を削る。ここで、Ar+の飛来方向は負バイ
アス電圧Vが印加された導体(10)の方向にほぼ決ま
り、導体(10)の上面や側面に堆積する絶縁材(4)
がAr+衝突で削られ、ハイアスペクト溝(11)の底
に堆積する絶縁材(4b)へのAr+衝突はほとんど無
くなる。従って、ハイアスペクトa(11)の底の絶縁
材(4b)の堆積速度が他よりも一段と速くなり、ハイ
アスペクト溝(11)に底から絶縁材(4b)が埋め込
まれることになる。
A negative bias voltage -■ is applied to the conductor (10), and the substrate (1
) when the insulating material molecules (12) are sputtered at zero potential, the conductor (10) and the first
Insulating material molecules (12) fly and deposit on the exposed surface of the insulating pattern (2). At the same time as this deposition, Ar'' flies and collides with the deposited insulating material (4), and the insulating material (4)
scrape a part of the surface. Here, the flying direction of Ar+ is almost determined in the direction of the conductor (10) to which the negative bias voltage V is applied, and the insulating material (4) deposited on the top and side surfaces of the conductor (10)
is scraped by Ar+ collisions, and Ar+ collisions on the insulating material (4b) deposited at the bottom of the high aspect groove (11) are almost eliminated. Therefore, the deposition rate of the insulating material (4b) at the bottom of the high aspect groove a (11) becomes much faster than in the other regions, and the insulating material (4b) is embedded in the high aspect groove (11) from the bottom.

以上の絶縁材埋め込みの動作を、仮に第5図及び第6図
に示すように、絶縁材分子(12)のスパッタリングと
Ar”jfl突を別々に行わしめた例でもって説明する
。まず、第5図に示すように、絶縁材分子(12)のス
パッタリングだけを行うと、導体(10)と第1の絶縁
パターン(2)の露出面に絶縁材(4)が堆積する。こ
の堆積は導体(1o)の上面隅部C1で多く行われる。
The above operation of embedding insulating material will be explained using an example in which sputtering of insulating material molecules (12) and Ar''jfl bombardment are performed separately, as shown in FIGS. 5 and 6. As shown in Figure 5, by sputtering only the insulating material molecules (12), the insulating material (4) is deposited on the exposed surfaces of the conductor (10) and the first insulating pattern (2). (1o) This is often performed at the upper surface corner C1.

次に!@6図に示すように、導体(10)に負バイアス
電圧−■を印加してA r ” fi突を行わせると、
Ar+は導体(10)に堆積した絶縁材(4)だけを削
って厚さを平均化し、ハイアスペクト溝(11)の底に
堆積した絶縁材(4b)はそのまま残る。このような分
子のスパッタリングとA r ” 衝突を同時進行的に
行わせると、ハイアスペクト溝(11)の底から絶縁材
(4b)が成長して、第3図及び第4図に示すように、
ハイアスペクトfi (11)に絶縁材(4b)が空洞
無くして埋め込まれる。
next! @6 As shown in Figure 6, when a negative bias voltage -■ is applied to the conductor (10) and A r ” fi thrust is performed,
Ar+ cuts only the insulating material (4) deposited on the conductor (10) to make the thickness average, and the insulating material (4b) deposited at the bottom of the high aspect groove (11) remains as it is. When such molecular sputtering and A r ” collision are performed simultaneously, the insulating material (4b) grows from the bottom of the high aspect groove (11), as shown in FIGS. 3 and 4. ,
The insulating material (4b) is embedded in the high aspect fi (11) without any cavity.

なお、上記実施例では、負バイアス電圧を一部と記した
が、具体的には一つの定電圧−100ボルトなどとして
もよく、あるいは二つの一100ボルト、−150ボル
トなどと複数段階に印加設定して絶縁材(4)の膜状態
制@(表面や厚さの改@)を図ることができる。
In the above embodiment, the negative bias voltage is described as part of the voltage, but it may be applied in multiple stages such as one constant voltage of -100 volts, or two constant voltages of -100 volts, -150 volts, etc. By setting, it is possible to control the film condition of the insulating material (4) (change the surface and thickness).

また、本発明は薄膜磁気ヘッドにおける薄膜コイルハタ
ーンの導体間に形成されたハイアスペクト溝への絶縁材
埋め込み方法に限らず、高密度配線化が要求されている
LSIの配線用導体間のハイアスペクト溝や、プリント
基板などに形成された幅広の薄膜状導体に線状にエツチ
ングなどで形成したハイアスペクト溝への絶縁材埋め込
み方法においても有効に通用できる。
Furthermore, the present invention is not limited to a method of embedding an insulating material into a high aspect groove formed between conductors of a thin film coil pattern in a thin film magnetic head, but is also applicable to a method of embedding an insulating material into a high aspect groove formed between conductors of a thin film coil pattern in a thin film magnetic head, and is also applicable to high aspect ratio between conductors for wiring in LSI, where high density wiring is required. It can also be effectively applied to a method of embedding an insulating material into a groove or a high aspect groove formed by linear etching or the like in a wide thin film conductor formed on a printed circuit board or the like.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、導体間のハイアスペクト溝に絶縁材を
スパッタリングさせて堆積させる際、導体の負バイアス
電圧で導体に堆積された絶縁材だけが不活性イオンの例
えばAr+の衝突で削られる作用を受けて平均した厚さ
で堆積し、ハイアスペクト溝の底に堆積する絶縁材はA
r+衝突をほとんど受けず堆積を続けるので、ハイアス
ペクト溝に絶縁材をより空洞少なくして埋め込むことが
容易にできるようになり、ハイアスペクト溝のより高い
ハイアスペクト比化を可能にする。この発明方法を薄膜
磁気ヘッドの薄膜コイルパターンの導体間に絶縁材を埋
める技術に通用すれば、薄膜コイルの導体の尚更のハイ
アスペクト比化を可能にして、薄膜磁気ヘッドの性能改
善に効果がある。
According to the present invention, when an insulating material is sputtered and deposited in a high aspect groove between conductors, only the insulating material deposited on the conductor is removed by the collision of inert ions such as Ar+ due to the negative bias voltage of the conductor. The insulation material deposited at the bottom of the high-aspect groove is A
Since the deposition continues with almost no r+ collisions, the insulating material can be easily filled into the high aspect groove with fewer cavities, making it possible to increase the aspect ratio of the high aspect groove. If the method of this invention is applied to the technology of filling insulating material between the conductors of the thin-film coil pattern of a thin-film magnetic head, it will be possible to make the conductor of the thin-film coil even higher in aspect ratio, and it will be effective in improving the performance of the thin-film magnetic head. be.

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第6図は本発明方法を説明するためのもので
、第1図乃至第4図はハイアスペクト溝に絶縁材を埋め
込むときの各動作状態での基板の部分断面図、第5図及
び第6図は本発明方法の説明の参考に利用する基板の部
分断面図である。 第7図は薄膜磁気ヘッドの一部省略部分を含む部分平面
図、第8図は第7図のA−A線に沿う拡大断面図、第9
図及び第10図は第8図の薄膜磁気ヘッドの部分変更例
を示す部分断面図、第11図乃至第18図は従来のハイ
アスペクト溝埋め込み方法を説明するための各埋め込み
工程での基板の断面図である。 (1)−−一基板、    (4)  (4b)・−・
絶縁材、(10) −導体、    (11) −ハイ
アスペクト溝。 第1図 第2111 特 許 出 廟 人  関西日本電気株式会社代   
 理    人  江  原  省  吾第3図 4b 第4図 is 11図 第13’l’4’1 一
1 to 6 are for explaining the method of the present invention, and FIGS. 1 to 4 are partial cross-sectional views of the substrate in various operating states when embedding an insulating material in a high aspect groove, and FIG. 6 and 6 are partial cross-sectional views of a substrate used for reference in explaining the method of the present invention. FIG. 7 is a partial plan view of the thin-film magnetic head including a partially omitted part, FIG. 8 is an enlarged cross-sectional view taken along line A-A in FIG. 7, and FIG.
10 and 10 are partial cross-sectional views showing examples of partial modifications of the thin film magnetic head shown in FIG. FIG. (1) ---One board, (4) (4b) ---
Insulating material, (10) - conductor, (11) - high aspect groove. Figure 1 No. 2111 Patent issued by Kansai NEC Co., Ltd.
Rijin Gangwon Province I Figure 3 4b Figure 4 is 11 Figure 13'l'4'1 1

Claims (1)

【特許請求の範囲】[Claims] (1)基板上に絶縁されて形成された導体の間の小溝幅
のハイアスペクト溝に絶縁材をバイアススパッタ法で埋
め込むに際し、前記導体にのみ負バイアス電圧を印加す
ることを特徴とするハイアスペクト溝埋め込み方法。
(1) A high aspect method characterized by applying a negative bias voltage only to the conductor when filling an insulating material into a high aspect groove having a small groove width between conductors formed insulated on a substrate by a bias sputtering method. Groove filling method.
JP19369090A 1990-07-20 1990-07-20 High aspect groove filling method Expired - Lifetime JP2807065B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19369090A JP2807065B2 (en) 1990-07-20 1990-07-20 High aspect groove filling method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19369090A JP2807065B2 (en) 1990-07-20 1990-07-20 High aspect groove filling method

Publications (2)

Publication Number Publication Date
JPH0479008A true JPH0479008A (en) 1992-03-12
JP2807065B2 JP2807065B2 (en) 1998-09-30

Family

ID=16312161

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19369090A Expired - Lifetime JP2807065B2 (en) 1990-07-20 1990-07-20 High aspect groove filling method

Country Status (1)

Country Link
JP (1) JP2807065B2 (en)

Also Published As

Publication number Publication date
JP2807065B2 (en) 1998-09-30

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