JPH0478140B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a trigger timing signal generator used in a digital oscilloscope or the like.

[Conventional technology]

In recent years, demand for digital storage oscilloscopes has increased due to technological improvements and increasingly sophisticated needs. One type of sampling method for digital oscilloscopes is the equivalent sampling method.
One method to achieve this is to use a sawtooth waveform that has a predetermined gradient from the point where it matches the trigger level of the input waveform, and a reference voltage that increases by a predetermined voltage for each period of this sawtooth wave. It is well known to generate a sampling clock when the sawtooth wave and the reference voltage match.

An oscilloscope using this sampling method stores and displays the portion after the trigger, but depending on the application, it is important to observe the rising portion of the signal and the portion before it in detail.
For this reason, conventional methods utilize the repeatability of the input signal to display a signal spanning two or more periods of the input signal on the screen, and enlarge the rising part after the second period and the part before it. There are ways to check the waveform before the trigger by using some operational tricks, such as doing this.

[Problem that the invention seeks to solve]

However, with this kind of operational innovation, the period of the input signal is very long, the transition is rapid,
When high-speed observation is required, there are drawbacks such as the difficulty of conducting observations with sufficiently high time accuracy. In order to solve this drawback, it would be better to equip the oscilloscope with an observation function before the trigger, but in order to do this, the input signal must be faithfully delayed, the delay time must be variable, and a fairly long time must be secured. However, those who perform equivalent sampling do not have a stable and economical method to do this.

[Means for solving problems]

In order to solve these drawbacks, the present invention is designed to find a pulse serving as a trigger timing from an equivalent sampling pulse train.

[Effect]

Of the observed waveform, a portion before the trigger and a portion after the trigger are distinguished.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 1 is a trigger input signal, 2 is a trigger detection circuit, 3 is a trigger pulse generation circuit, and 4 is a trigger input signal.
5 is a gate signal generation circuit, 5 is a gate period detection circuit, 6 is a gate signal delay circuit, 7 is a sawtooth wave generation circuit, 8 is a reference voltage generation circuit, 9 is a comparison circuit,
10 is a sampling pulse generation circuit, and 11 is a trigger timing detection circuit.

The trigger detection circuit 2 compares the trigger input signal 1 with a trigger level separately set within the circuit, and generates an output signal when the levels match. The trigger pulse generation circuit 3 is configured to generate a trigger pulse 12 based on a signal supplied from the trigger detection circuit 2. Based on the trigger pulse 12, the gate signal generation circuit 4 generates a gate pulse 13 with a period defined by the relationship between the frequency of the trigger input signal and the sweep feed rate preset in this measuring device. . The gate period detection circuit 5 detects the period T of continuously emitted gate pulses, calculates a delay time (T-τ) using a signal 14 representing a pre-trigger time τ set on an operation panel (not shown), and calculates a delay time (T-τ). Delay time control is performed for the signal delay circuit 6. The gate signal delay circuit 6 is configured to generate a delayed gate pulse 15 by delaying the gate signal 13 by a delay time (T-τ) determined by the gate period detection circuit 5. The sawtooth wave generation circuit 7 is a circuit that generates a sweep sawtooth waveform corresponding to the sweep speed set on the operation panel, and is designed to generate a sawtooth wave 16 that starts voltage transition in response to the delay gate pulse 15. . The comparison circuit 9 is designed to generate an output signal when the sawtooth wave 16 and the voltage value output from the reference voltage generation circuit 8 match. The sampling pulse generation circuit 10 compares the sawtooth wave 16 with a stepped reference voltage 18, which will be described later, and generates an equivalent sampling pulse 17 when the sawtooth wave 16 exceeds the reference voltage 18. The reference voltage generation circuit 8 is configured to generate a step-like reference voltage 18 whose voltage value increases by a predetermined amount every time a delay gate pulse 15, which is a trigger signal for generating the sawtooth wave 16, is generated. The trigger timing detection circuit 11 detects the first equivalent sampling pulse 17 after the gate pulse 13 is generated.
is detected, and a trigger timing signal 19 is generated.

The operation of the apparatus configured as described above will be explained using the waveform diagram shown in FIG. In FIG. 2, a is the trigger input signal 1, b is the trigger pulse 12, c is the gate pulse 13, d is the delayed gate pulse 15,
FIG. 2 is a waveform diagram in which e is a sawtooth wave 16, f is an equivalent sampling pulse 17, and g is a trigger timing signal 19. Furthermore, the dashed-dotted line in FIG.

The trigger detection circuit 2 receives the trigger input signal 1 shown in a.
When supplied, an output signal is generated every time the trigger input signal 1 exceeds the trigger level shown by the dashed-dotted line, so the trigger pulse 12 shown in b is sent out from the trigger pulse generating circuit 3. trigger pulse 12
The gate signal generating circuit 4 to which is input generates a gate pulse 13 as shown in c.

This gate pulse 13 is supplied to a gate period detection circuit 5, a gate signal delay circuit 6, and a trigger timing detection circuit 11. When the trigger input signal 1 has a repetitive waveform, the gate pulse 13 is generated at a substantially constant period, so that the gate period detection circuit 5 can easily detect the period of the gate pulse 13 using a counter or the like. For this reason, the gate period detection circuit 5 has a gate pulse 1 that is continuously supplied.
3 is detected, and a signal representing a delay time (T-τ) is sent out using a signal 14 corresponding to a pre-trigger time τ set separately on an operation panel or the like. Therefore, the gate signal delay circuit 6 sends out a delayed gate pulse 15, which is the gate pulse 13 delayed by (T-τ), as shown in d.

The sawtooth wave generation circuit 7 generates a delay gate pulse 15
The reference voltage generating circuit 8 generates a sawtooth wave 16 that starts a voltage transition as shown by the solid line e, and the reference voltage generation circuit 8 generates a sawtooth wave 16 when the sawtooth wave 16 is 1.
A step-like reference voltage 18 that increases by a predetermined voltage ΔV every time the cycle ends, as shown by the dashed line e.
occurs. These signals are compared in the comparator circuit 9, and an output signal is generated at the point where the two voltages match, so that the equivalent sampling pulse 17 shown at f is generated from the sampling pulse generation circuit 10 to which this signal is supplied.

For the input signal waveform, each time an equivalent sampling pulse shown at f occurs, the data at that time is taken in and stored in a memory (not shown). However, as it is, it is not possible to identify which pulse of the equivalent sampling pulse train shown in f is at the trigger point. Therefore, in the trigger timing detection circuit 11, the first equivalent sampling pulse 17 after the gate pulse 13 is generated.
The trigger timing signal 19 shown in g is generated by detecting the time point at which the trigger point occurs, and the trigger point is identified using this signal.

The step-like reference voltage 18 shown in e increases by ΔV every cycle of the sawtooth wave, so f
The equivalent sampling pulse 17 shown in is (T + Δt) higher than the equivalent sampling pulse that occurred immediately before.
Occurs with a delay. Figures 2a to 2g show only a certain period of the sweep period, but
Since the actual sweep is performed repeatedly, even if the equivalent sampling pulse 17 occurs every (T+Δt) period, the input waveform is stored in the memory every time the equivalent sampling pulse 17 occurs. Therefore, by repeatedly performing the sweep, as shown in FIG. 3, data equivalent to data sampled by sampling pulses generated every period Δt is stored in the memory. That is, the equivalent sampling pulse 17 generated at a slow period can be equivalently sampled by sampling with a virtual sampling pulse generated at a sufficiently earlier period.

As mentioned above, the time point when the trigger timing signal 19 shown in g is generated is the trigger time point, so the data sampled after this time point is the data after the trigger time point, and the data sampled before that point is the data sampled at the pre-trigger time τ. This is the data. If the number of constituent points of the waveform on one screen is M, the number of sample data m before the trigger point is τ/Δt,
The number of sample data after the trigger point is (M−m). By displaying the waveform using these data, the waveform of the pre-trigger time τ portion is followed by the waveform of the period (T−τ) after the trigger is displayed on the screen. Since the pre-trigger time τ can be set arbitrarily by the observer, even if the period of the input signal waveform is long, the waveform before the trigger can be observed in detail.

FIG. 4 shows an example in which the trigger timing detection circuit 11 is composed of flip-flops 11a and 11b, in which a gate pulse 13 is applied to the T input of the flip-flop 11a, a delayed gate pulse 15 is applied to the reset input, and a T input of the flip-flop 11b is applied. A trigger timing signal 19 is extracted from the Q output of the flip-flop 11b by supplying an equivalent sampling pulse 17 to the flip-flop 11b.

This device detects which point in the equivalent sampling pulse train corresponds to the trigger timing, and the selection of data to be finally stored is based on the data before the trigger timing, and
Since it is replaced by a means for extracting subsequent data, the resolution of the delay time (T-τ) set by the gate signal delay circuit 6 is not strictly required, and it is sufficient that the accuracy of variation in delay time each time is small.

〔Effect of the invention〕

As explained above, this invention detects which sampling pulse of the equivalent sampling pulse train occurs at the trigger time, and therefore has the effect of allowing detailed observation of the waveform before the trigger. have

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram showing the operation of the device shown in FIG.
Figure 3 is a waveform diagram of the virtual sampling pulse, Figure 4 is a waveform diagram of the virtual sampling pulse.
The figure is a circuit diagram of a trigger timing detection circuit. 4... Gate signal generation circuit, 5... Gate period detection circuit, 6... Gate signal delay circuit, 7... Sawtooth wave generation circuit, 8... Reference voltage generation circuit, 9
... Comparison circuit, 10 ... Sampling pulse generation circuit, 11 ... Trigger timing detection circuit.

Claims (1)

[Scope of Claims] 1. A gate pulse generator that generates a gate pulse based on a trigger input signal, and a delay that generates a delayed gate pulse that is delayed by a time equal to the gate pulse period minus the pre-trigger time with respect to the gate pulse. A gate pulse generation section, an equivalent sampling pulse generation section that generates an equivalent sampling pulse based on a sawtooth wave synchronized with the delayed gate pulse, and an equivalent sampling pulse generation section that generates an equivalent sampling pulse based on a sawtooth wave synchronized with the delayed gate pulse; and a trigger timing signal generating section that detects the first equivalent sampling pulse after a gate pulse is generated and generates a trigger timing signal.