JPH0478064A - Recording medium driving device - Google Patents

Abstract

PURPOSE:To dispense with an exclusive terminal for accessing a storage means by making it possible to input and output information stored in the storage means from an interface part to which a control signal is inputted by a protection circuit. CONSTITUTION:The information related to the version setting of control operation, etc., and various information related to a device like the sort and the number of a machine, etc., are stored in the storage means 1. A protecting means is installed between the interface part 3 and the storage means 1, and when a predetermined prescribed signal is inputted to the interface part 3, protection is canceled, and the storage means 1 becomes capable of being accessed from the interface part 3. Thus, the number of the terminals can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a recording medium drive, and more particularly to a recording medium drive that inputs and outputs control signals and data via an interface section.

In the conventional technology FDD (Floppy Disk L Live), the presence or absence of the RE A DY signal and the form of data output (
Whether the signal is high or low level), whether or not there is calibration (whether or not the initial operation of moving the head to the track start position is performed after the power is turned on), lighting conditions for the front LED (light emitting diode), etc. Functions are often changed to suit the needs of the customer delivering the equipment.

The main part of a conventional FDD is a large-scale integrated circuit (LSI).
), the LSI has several functions,
A select terminal is provided on the LSI, and a printed wiring board (
The required function was selected by changing the connection of the select terminal using jumper wires etc. on the PCB (PCB).

Furthermore, since there are many functions to be set, if one LSI were to be used for certification, the number of select terminals would increase, so several LSIs were manufactured according to the functions.

However, in such recording medium drive devices such as FDDs, the control LSI is provided with a select terminal for selecting a function, and the function is selected by switching the connection of this select terminal. It is troublesome to connect the PCB, and it also requires a large number of select terminals, which means that it is necessary to provide a large number of terminals for connecting jumper wires to the PCB on which the control LSI is mounted, resulting in a large PCB. The number of select terminals that can be set on a commercial LSI is limited, and it is necessary to change the LSI design depending on the function, so the types of LSIs and PCBs to be mounted will increase, and different assembly processes will also be required. It had become.

For this reason, it is possible to read and write internally, for example, E 2P
P OM (Electrically Eraser
ble Programmable Read 0nly
Some devices were configured to have storage means such as "Memory", and to perform input settings and the like based on the information stored in these storage means. Therefore, in addition to the control interface, a terminal section has been provided in order to write and read data in the recording means.

However, in conventional recording medium drive devices such as FDDs, a dedicated terminal was provided to read and rewrite data in the storage means for selecting functions, etc.
There are problems such as the need to provide terminals in addition to the interfuniform part for D control, the number of terminals increases, making it impossible to reduce size and cost, and the risk of incorrect connection. Ta.

The present invention has been made in view of the above points, and an object of the present invention is to provide a recording medium drive device that is easy to set functions, etc., and has a small number of terminals.

Means for Solving the Problems The present invention provides a recording medium drive device that performs input/output of a recording head and input/output of control signals for each operation control section via an interface section, in which various information for each device is stored. provided between a storage means, the interface section, and the storage means, and cancels protection only when a signal input to the interface section is a predetermined signal different from the recorded data and the control signal; and protection means for making the storage means accessible from the interface section.

The action storage means stores various information regarding the device, such as information regarding version settings such as control operations, and model number.

The protect means is provided between the interface section and the storage means, and when a predetermined signal is input to the interface section, the protected storage means can be accessed from the interface section.

In this way, the protection means allows access to the storage means through the interface.

Example FIG. 1 shows a block diagram of one embodiment of the invention.

In this embodiment, an FDD (floppy disk drive) will be explained.

1 is an E2PROM (Eelectro
nically Erasable Programa
ble Read Only Memory), and its output data is supplied to the controller 2. The controller 2 mainly includes an R/'W (READ/WRITE) control circuit 2a and a spindle motor control circuit 2b.
These circuits are controlled according to the data from E2FROMI, and the version of their operation is set.

In addition to inputting data from the E2FROMI, the controller 2 also receives control signals from a terminal section connected to a computer device via a logic circuit. controller 2
In response to these input signals, the spindle motor 5 that rotates the floppy disk 4 is turned on and off, and the read/write operation that supplies data to the magnetic head 6 is performed.
The write (R/Vv') circuit 7 is controlled.

The R/W circuit 7 is supplied with data and the like from the controller 2 to the magnetic head 6 . Further, the R/W circuit 7 is connected to the interface section 3 via a logic circuit.

The interface section 3 is )・Live Select (DS)
Signal input terminal T1, step (STEP) signal input terminal T2, direct (DIR) signal input terminal T3, index (INDEX) signal output terminal T4, file protect (FPT) signal input terminal T5, data (RD) output terminal T6, Light gate (WG) signal input terminal T7,
Motor on (J+1ortor On>terminal T8, write data (WD) input terminal T8, site 1. (SIDEI)
) signal input terminal T,. It becomes more.

The protection means is AND key h1.9.20゜26.2
7.28.29.3+, retractable mo/ma/L vibrator (NfNf v,) 2 +, , 2
2, flip-flop 2-pu 30, coat detector 32,
It is composed of a Sorial/Parallel converter 33 and a Parallel/7/Real converter 34.

DS signal input terminal T, AND gate 8,910.11
and one input terminal of the NAND gates 12 and 13. The STEP signal input terminal T2 is connected via the inverter 14 to the other input terminal of the AND-1-8. DIR signal input terminal T3 is connected to A via inverter 15.
, ND is connected to the other input terminal of the gate 9. The outputs of the AND gates 8 and 9 are input to the counter 16 and also to the stepping motor control circuit 17. The stepping motor control circuit 17 is A
Stepping motor 35 in response to a signal from ND circuit 8
control.

The counter 16 ANDs the input signal from the AND gate 8.
The count is added or subtracted depending on the input signal level from the gate 9, and the counted number is sent to the l rank decoder 1.
Supply to 8. Here, the output of the AND gate 9 becomes a signal indicating the track count direction.

The track decoder 18 changes the count value of the counter 16 to (
A corresponding signal is supplied to the R/W circuit 7.

Further, when the count number of the counter 16 reaches 82 tracks, it is detected and the detection signal is supplied to the step pink motor control circuit 17, and when the count number of the counter 16 reaches 257 tracks, the detection signal is outputted. It is supplied to the input terminals of AND gates 19 and 20.

In this embodiment, the detection signal is output from 257 tracks, but the present invention is not limited to this, and the point is that the number of tracks that are not normally used may be specified.

The other input terminal of AND gate 19 is MM V21, .
INDEX signal output signal output terminal number 4 through 22,
Its output terminal is connected to a preset terminal of counter 16. The counter 16 presets the count number to 82 tracks in response to the output signal of the AND gate 19.

INDEX signal output In addition to the 421 input terminals, an output terminal of the NAND gate 12 is connected. NA
The input terminal of the ND gate 12 is supplied with an output detection signal of the index sensor 23 in addition to the DS signal input terminal T1. The index sensor 23 detects the index hole of the floppy disk 4 and outputs a corresponding detection signal.

The output signal of the index sensor 23 is outputted from four INDEX signal output terminals according to the level of the DS signal input terminal T1.

MMV2N7) Output 1tInput to MMV2, MNIV
The output of 2 is input to the AND gate 19.

FPT signal input terminal T5 is NA, NDK-1-1
The DS terminal T1 is connected to one input terminal of the NAND gate 13, and the output of the file protection sensor 24 is supplied to the other input terminal. The file protection sensor 24 is a sensor that detects whether or not writing to the floppy disk 4 is possible.The output of the file protection sensor 24 is sent to the FPT signal input terminal T according to the input signal level of the DS signal input terminal T1 by the NAND gate 13. Output.

Further, the output of the file protection sensor 24 is inputted to the other input terminal of the AND gate 20 via an inverter 25. The output of AND gate 20 is the output of AND gate 26
．． 27; is supplied to the input terminals of 28, 29 and the flip-flops 1.27; is input to the reset terminal of step 30.

The output of AND gate 27 and flip-flop 30 is A
The signal is input to the ND gate 31. The input of the AND gate 28 is connected not only to the output of the AND gate 20 but also to the WD signal input terminal T9 via an inverter 37.

The output of AND gate 28 is sent to serial/parallel converter 3.
It is connected to the data input terminal of No.3.

Further, the other input of the AND gate 29 is connected to the 5IDEI signal input terminal Tto via the inverter 38. 5IDEI signal input terminal T when protection is released.

A clock signal is input to the .

The output of AND gate 29 is serial/parallel converter 3
3 and a clock signal input terminal of a parallel/serial converter 34.

The output data of parallel/sorial converter 34 is provided to the other input of AND gate 26. The output of the AND gate 26 is input to the other input terminal of the NAND gate 36, and the output of the NAND gate 36 is connected to the RD output terminal T6, so that the data of E2PROhil can be read from the RD output terminal T6.

WG signal input terminal T7 is connected to AN via INNO\-Y39.
It is connected to the input terminals of D gates 31 and 11. The motor on terminal T8 is connected to the controller 2 via the inverter 40.
It is also connected to the input terminal of the AND gate 27. The output of the AND gate 27 is connected to the AND gate 31 and to the rotor terminal of the parallel/serial converter 34.

The output of the serial/parallel converter 33 is E2FROMI
is supplied to the address input and data input of , as well as to the coat detector 32 .

The code detector 32 outputs a high level signal when a certain code is input. The signal is also supplied to the WF multiplied signal AND gate 31 of the serial/parallel converter 33 and also to the code detector 32 . AND Kate 3
The output of 1 is input to the terminal that provides write permission of E2FROMI.

Therefore, writing of E''FROMI is permitted when the input of the AND gate 31 becomes high level and its output becomes high level.

Next, its operation will be explained.

Data is written to the E2FROM using an FDD interface (FDDIF) without providing a dedicated terminal. For this reason, a protection means is connected to the FDDIF. In order to release the protection means, conditions that are impossible in normal FDD use are applied to the interface section.

In this embodiment, the conditions for canceling the protection of the protection means are as follows.

A pulse signal is supplied to the 5TEP signal input terminal T2, and the 25
Specify 7 tracks. Then, as shown in FIG. 2(B), the output of the track data 18 becomes high level at the 257th track. This 257 truck is a normal FDC
(Floppy disk controller) This is a fictitious track number that cannot exist in the IC, and by specifying this, part of the protection against access to E2FROMI is canceled.

As shown in FIG. 2(F), a burst signal having a specific frequency is continuously input to the INDEX signal output terminal T4.

A second signal is connected to the INDEX signal output terminal T4, which is originally an output terminal.
As shown in FIGS. (A) and (B), when the DS (drive select) terminal T1 and the DIR signal input terminal T3 are in a low level state where the drive is not selected, a signal of a frequency not normally used by the FDD is input.

Furthermore, in order to pursue signal stability (to distinguish it from some kind of abnormal oscillation), two MMV21°22 are installed. As shown in Figures 3 (A) and (B), abnormal oscillations rarely occur continuously, and pulse omissions occur at regular intervals, so this causes the abnormal oscillation to be connected to the access signal. With distinction (.

Also, insert a writable disc. This turns on the file protection sensor 24. Since it is rare that a writable disc is inserted during normal use, this operation makes it possible to protect the disc.

With the above conditions, access to E2FROMI becomes possible. In other words, as shown in Figure 2 (J), E2
The PROMI EN signal turns on.

To read, the following procedure is also required.

5. A clock signal is input from the IDEI signal input terminal (terminal for switching heads).

From the WD input terminal (terminal for inputting write data) to E
' Specify the address of FROMI data.

As a result of the above operation, the data E"PR,0M4 is output from the RD output terminal (terminal that outputs the readout).

Writing to E2FROMI is as follows.

First, a clock is input from the 5IDEI signal input terminal, and then the WG (write gate) signal input terminal is set to high level.

Furthermore, the motor-on signal input terminal is set to high level.

Here, data matching the data set in the code detector (CODE DET) is input from the WD terminal.

Write data including address data is input from the WD input terminal.

By doing this, it is turned on by the write gate of E2FROMI or an AND circuit with multiple inputs.

In this way, the E' FROM
Since it is only possible to write and read data in I, E
There is no need to provide a dedicated terminal for 2FROMI, and the entire device can therefore be made smaller. By using multiple protection circuits, data will not be destroyed even if a connection is made incorrectly. Even if a wrong signal is input to the interface section 3, the data will not be easily destroyed.

In this embodiment, the storage means is a memory for setting the operation version of the FDD, but the present invention is not limited to this, and may be a storage means for storing ordinary data.

Further, the present invention is not limited to an FDD, and any recording medium drive device having an interface or the like may be used.

Effects of the Invention As described above, according to the present invention, various information regarding the apparatus can be stored in the storage means, and the information stored in the storage means can be used as a control signal for controlling the operation of the apparatus by the protection circuit. Since the data can be input and output from the input interface section, there is no need to provide a dedicated terminal for accessing the storage means, reducing costs and making it possible to downsize. It has the characteristics of preventing damage, malfunction, etc.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG.
The figure is a waveform diagram for explaining the operation of an embodiment of the present invention. 1... E2PROM, 2... Controller, 3...
・Interface section. Patent applicant: TIATSUKU Co., Ltd. Morigo Ayuno

Claims (3)

[Claims] (1) In a recording medium drive device that inputs and outputs data and inputs and outputs control signals for controlling various operations via an interface section, a readable and writable storage means that stores various information for each device; The interface unit is provided between the interface unit and the storage means, and the protection is released from the interface unit only when the signal input to the interface unit is a predetermined signal different from the data and the control signal. A recording medium drive device comprising: protection means for making the storage means accessible. (2) The recording medium drive device according to claim (1), wherein the protection means is constituted by a plurality of protection circuits. (3) The recording medium according to claim (1) or (2), characterized in that the protect means is configured such that the protection is canceled when the interface unit supplies a signal with a condition not to be used during the operation control. Drive device.