JPH0475360A - Life time evaluation of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to simulate the operation of a device and evaluate the life time of a semiconductor device by entering the oscillation voltage of an oscillation circuit which comprises devices used for a semiconductor device to be actually evaluated for simulating the operation of the semiconductor device. CONSTITUTION:A circuit to be measured applies required operation power source voltage to 12 and 13 while 15 and 16 supplies voltage lower than grounding voltage or the operation power source voltage. While maintaining this state, the characteristics of the devices which constitute the measured circuit is subject to aging deterioration. After having held the required voltage application state described above, every pad terminal is opened so that the supply of the power source voltage to an oscillation device and the measured circuit may be brought to a halt. The electric properties are measured by measured devices P1 and N1. The pad terminal is treated in the same way as the initial value is measured. The difference between the measured value and the initial value is calculated and its calculated value is defined as the amount of deter of deterioration which serves as the basis for estimating life time.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a reliability evaluation method for semiconductor devices in general.

[Conventional technology]

Conventionally, the lifetime evaluation method for semiconductor devices is based on I.E.E.
E. Transactions on Electron Devices Volume 35. Number 9° (1988) 1st
pages 476 to 1486 (IEEE, TRANSAC
TIONS ON ELECTRON DEVICES
vo Q35, Na9. (1988) pp, 1476
-1486), a pulse voltage was applied externally to each terminal of the device using a pulse generator.

[Problem to be solved by the invention]

The above-mentioned conventional technology does not take into account the point of simulating the operation of devices forming a circuit in an actual semiconductor device. In other words, the three conditions that characterize this simulated operation are: (1) the voltages of at least two or more terminals of the device fluctuate simultaneously, and (2) the rise and fall of voltage fluctuations.
The fall time is equivalent to that of an actual semiconductor device (In
(3) The number of digits of the voltage fluctuation frequency is equal to the number of digits of the operating frequency of the actual semiconductor device. For this reason, there was a problem that it could not be applied to actual life evaluation of semiconductor devices.

An object of the present invention is to provide a method for evaluating the life of a semiconductor device by simulating the operation of a device constituting a circuit in a semiconductor device, that is, satisfying the above three conditions.

Another object of the present invention is to provide an evaluation circuit technique for achieving the above object.

[Means to solve the problem]

In order to simulate the operation of the semiconductor storage device mentioned above, the oscillation voltage of an oscillation circuit composed only of devices used in the semiconductor device to be actually evaluated is input to a circuit under test composed only of the devices. . These circuit groups are integrated on a chip to reduce the influence of parasitic load capacitance.

Further, the circuit under test is provided with mutually independent pad terminals for each terminal of the device so that the characteristics of the circuit and the devices constituting the circuit can be measured.

[Effect]

The oscillation waveform obtained by the oscillation device configured with the device actually used in the semiconductor device to be evaluated should be one that reproduces the voltage operation waveform in the semiconductor device, that is, the rise and fall of the voltage. It is possible to make the time less than Ins, and at the same time, the oscillation frequency can be made to match that of the semiconductor device.

The circuit under test is a circuit that is used in an actual semiconductor device and is composed of at least two or more devices.

That is, the potentials of at least two or more terminals of the devices constituting the circuit are in a state of fluctuating simultaneously. This is equivalent to the operation of a device within a semiconductor device.

By integrating the above oscillation device and the circuit under test on a chip and inputting the oscillation voltage to the circuit under test, the load capacitance associated with the wiring can be reduced and the characteristics of the oscillation voltage described above will not be impaired. do not have. Therefore, it is possible to reproduce the operation of devices in an actual semiconductor device, and it is possible to evaluate the life of the semiconductor device.

〔Example〕

FIGS. 1(a) and 1(b) show an example of a circuit configuration for implementing the evaluation method of the present invention. The oscillation device is characterized in that it is comprised only of devices actually used within the semiconductor device. The power supply voltage supply to the oscillator is at the terminal v
This will be done through CC. The oscillation frequency is monitored through the terminal OUT, but it is connected through a buffer circuit B so that the measurement system does not affect the oscillation. The circuit under test consists of only the devices actually used in the semiconductor device, and the terminals of the device under test are provided with mutually independent pad terminals that are not connected to any other terminals other than those of each device. It is. In Figure 1(a), the circuit under test is PL (PMO8).
and Nl (NMO5). Pad terminals are numbered 11-16. Pl gate, source, substrate.

The drains are located at 11, 12 and 13° 14 of the pad terminal, respectively.
It corresponds to The gate, source, substrate, and train of N1 correspond to 11.16, 15°14 of the pad terminal. When the circuit under test operates, 12.13 is fixed to the operating power supply voltage, and 15.16 is fixed to ground or a desired voltage. The potential of the pad can be easily fixed by connecting it to an external voltage source. With such a terminal configuration, it is possible to reduce the load capacitance that affects the operation of the circuit.

Only by integrating these circuits on a chip can the operation of devices in an actual semiconductor device be simulated.

A method for evaluating the lifetime of a semiconductor device according to the present invention will be described below using the circuit shown in FIG. 1(a). First, the electrical characteristics of the devices PL and Nl (devices under test) constituting the circuit under test are measured and set as initial values.

At this time, the pad terminals 11 to 16 are handled in correspondence with each terminal of the device as described above. Next, a power supply voltage is applied to VCC to cause the oscillation device to oscillate. The circuit under test is 12,
1. Apply the desired operating power supply voltage to 3, and 15. '16 applies a voltage lower than the ground or the operating power supply voltage. While this state is maintained, the characteristics of the devices constituting the circuit under test deteriorate over time due to hot carrier effects. After maintaining the voltage application state for the desired time, open all pad terminals and start the oscillation device (including buffer circuit B).
and stop supplying power voltage to the circuit under test.

Then, the electrical characteristics of the devices under test PL and Nl are measured. The handling of the pad terminal is the same as when measuring the initial value. The difference from the initial value is then calculated and used as the amount of deterioration, which is used as a standard for life prediction. Furthermore, it is also possible to evaluate the characteristics of the entire circuit under test, rather than the characteristics of the device alone. In that case, 12.13 is the power supply voltage, 15.16 is grounded or set to a voltage lower than the power supply voltage, and the signal human power 1
What is necessary is to measure the variation in the response characteristic of the signal output 14 with respect to 1.

FIG. 1(b) shows a case where a B1CMOS inverter circuit is used as the circuit under test. 111°11 of pad terminal
2.113 and 117 correspond to the gate, source, substrate, and drain of P 111 (PMO5).

111.117, 116, 115 are N111N111 (
Corresponds to the gate, source, and substrate radrain of N. 11
1, 118, 119, and 121 correspond to the gate, source, substrate, and drain of N112. 118, 121, 12
3. ．． 122 corresponds to the gate, source, substrate, and drain of N113. 114, 117, 118 are B111
118, 121, and 120 correspond to the collector, base, and emitter of B112. When operating this circuit, first the NCC is fixed to the power supply voltage and oscillated. The terminals to be measured are 111 to 114 fixed to the operating power supply voltage of the circuit to be measured, and 115, 116, 119, 12
0, 122, and 123 are set to ground or a voltage lower than the operating power supply voltage. After maintaining this state for a desired period of time, use the above-mentioned combination of pad terminals as shown in Figure 1 (
Perform the evaluation as explained in a). Note that the circuit to be measured is not limited to an inverter circuit, but any circuit used in a semiconductor device can be used.

FIG. 2(a) is an embodiment of the evaluation circuit of FIG. 1(a), and FIG. 2(b) is an embodiment of the evaluation circuit of FIG. 1(b). The oscillation devices indicated by broken lines in both cases use a ring oscillator (feedback type oscillator) consisting of an odd number of basic gate circuits G. Figure 1(a) shows how to handle pad terminals when measuring device characteristics for life evaluation.

This is as explained in (b). Figure 12 (a) and (b)
) has the advantage that the characteristics of the circuit under test do not affect the oscillation characteristics of the oscillator.

Therefore, by adding a capacitor to the output of the circuit under test, only the influence on characteristic fluctuations can be evaluated with high accuracy.

FIGS. 2(a) and 2(b) show other embodiments of the evaluation circuit. The feature of this configuration is that the circuit under test itself constitutes a part of the oscillation device, so it can be used as an evaluation circuit with a small area equivalent to the area of the basic gate circuit that makes up the oscillation device. There is an advantage. This is an advantageous condition when the chip area is small. The evaluation method and pad terminal handling are the same as in FIG.

〔Effect of the invention〕

According to the method of the present invention, accelerated testing can be performed based on the operation of a device in an actual semiconductor device. That is, by quantifying the deterioration at several power supply voltages higher than the voltage of the power supply used and at several oscillation frequencies across the operating frequency used, the life in actual use can be predicted. For the first time, it has become possible to set the system's power supply and operating frequency to ensure longevity. That is, it is now possible to determine the maximum operating frequency at a certain power supply voltage or the maximum power supply voltage for operating at a certain operating frequency.

Also, the area saving effect in the configuration shown in Figure 3 is 0.
．． The 8μm rule saves about 600μ for one gate circuit.

[Brief explanation of drawings]

FIG. 1(a) is a circuit configuration diagram when a CMOS inverter is used in the circuit under test among the circuit configurations for implementing the evaluation method of the present invention, and FIG. 1(b) is a circuit configuration diagram when a CMOS inverter is used in the circuit under test.
Circuit configuration diagram when using a MOS inverter, Figure 2 (
a) is a circuit configuration diagram when a ring oscillator is used as the oscillator in FIG. 1(a), and FIG.
Figure 3(b) is a circuit configuration diagram when a ring oscillator is used as the oscillation device; Figure 3(a) is a circuit configuration diagram when the CMOS inverter of the circuit under test functions as a part of the ring oscillator; FIG. 3(b) is a circuit configuration diagram when the BiC OS inverter of the circuit under test is made to function as part of a ring oscillator. ■CC...Oscillation device power supply voltage supply pad, OUT...
Pad terminal for oscillation voltage waveform detection, B F °゛°buffer circuit for oscillation voltage waveform detection, Pl, pHl...PMO
3. Nl, N11l ~ N11N113-N, B111°B
112...Bipolar transistor, 11~16°1
11-123... Pad terminal for device characteristic measurement 7
,' Agent Patent attorney Katsuma Ogawa (,'・th<b)th (α) 0t)T (αsmall(shi)

Claims (1)

[Claims] 1. A method for evaluating the lifespan of a semiconductor device, characterized by simulating the operation of a device within the semiconductor device and evaluating the lifespan of the device and the device. 2. According to claim 1, the device comprises an oscillation device and a circuit under test, each of which is constituted by a device actually used in a semiconductor device, and the oscillation voltage of the oscillation device is input to the circuit under test. A method for evaluating the lifespan of semiconductor devices. 3. The method for evaluating the life of a semiconductor device according to claim 2, wherein a ring oscillator (feedback type oscillator) is used as the oscillator.