JPH0475140A - Information processor performing symbol processing and numeric value processing in parallel - Google Patents

Abstract

PURPOSE:To improve the description capability of a program and to perform fast processing by generating a sequential arithmetic instruction flow from a symbol processing part which performs symbol processing interpretively based on message transmission between objects, and supplying it to a numeric value arithmetic part. CONSTITUTION:This device is comprised of an interface 1 with a host computer, the symbol processing part 2, the numeric value processing part 3, a bus switch 4, object managing memory 5, and memory banks 61 - 6n for numeric value data. The symbol processing part 2 which performs the symbol processing interpretively based on the message transmission between the objects dynamically generates the sequential arithmetic instruction flow to the numeric value arithmetic part 3 which executes a numeric value arithmetic operation according to interpretive symbol processing in parallel with the symbol processing. Thereby, it is possible to easily perform fuzzy set description by the symbol processing oriented for object, and also, since the parallel processing of an instruction flow generated sequentially by the symbol processing can be performed by the numeric value arithmetic part 3, the fast processing can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device that performs symbol processing and numerical processing in parallel, and is particularly suitable for application to fuzzy information processing systems.

[Conventional technology]

Traditionally, computer architectures have been designed with emphasis on numerical processing. 2. Description of the Related Art Computer systems that process information using a combination of a general-purpose CPU and a numerical processor are common. In addition, as a device that performs symbol processing, L I S P (listρrocessor
) machine is known.

[Problem to be solved by the invention]

In recent years, applications to more advanced knowledge information processing such as fuzzy information processing and artificial intelligence require both numerical processing and symbolic processing, so the computer systems described above cannot hope for efficient processing. .

In view of this problem, it is an object of the present invention to provide an information processing device (computer architecture) that can efficiently perform both numerical processing and symbolic processing.

[Means to solve the problem]

An information processing device according to the present invention that performs symbol processing and numerical processing in parallel includes a symbol processing unit that performs symbolic processing in an interpretive manner based on message transmission between objects, and a numerical value accompanying the interpretive symbol processing. A numerical calculation unit that executes calculations in parallel with the symbol processing, and the symbol processing unit dynamically generates a sequential calculation instruction stream for the numerical calculation unit.

[Effect]

When handling fuzzy information containing ambiguity in an expert system equipped with a knowledge base, numerical operations (fuzzy set operations, etc.) for fuzzy information processing are essential along with symbolic processing. According to the above configuration, object-oriented symbolic processing facilitates fuzzy set description, and high-speed processing is possible because the instruction stream sequentially generated by symbolic processing is processed in parallel by a dedicated numerical calculation unit. .

〔Example〕

Hereinafter, the present invention will be explained based on an example in which the present invention is applied to a computer architecture suitable for fuzzy knowledge information processing.

Fuzzy theory is attracting attention as a means of expressing the ambiguity inherent in human language. The effectiveness of fuzzy theory has been demonstrated mainly through application in the control field, but it is originally a fundamental concept that does not depend on the field. In the future, it is expected that a broader range of fuzzy information processing will be developed in conjunction with knowledge engineering methods as a means of expressing ambiguous human knowledge.

There are two conditions required for a system that supports fuzzy information processing:

(1) Fuzzy set processing and symbol processing can be performed in a unified manner.

(2) Expression and calculation of fuzzy sets can be performed easily and quickly.

There have been systems called ``fuzzy computers'' to date, but they did not meet these conditions. Those based on hardware are aimed at high-speed execution of fuzzy inference for control purposes, and do not support processing such as simple numerical calculations and symbolic processing. There are also examples of software-based fuzzy set processing systems, but none that have sufficient versatility and high speed have been found.

In order to satisfy the above two conditions, a language suitable for fuzzy intellectual information processing and hardware for executing this at high speed will be explained.

First, we will start with the object-oriented language MoNo (hereinafter simply rMoN), which is a system description language for fuzzy computers.
o”. ). And Mo
The basic configuration of hardware for high-speed processing of numbers will be shown, and a functional distributed instruction method calculation unit for high-speed numerical calculation will be described.

Object Tongo M. By introducing No.'s object-oriented model, the following features can be obtained.

(1) Representation of fuzzy sets as data types By regarding fuzzy sets as structured data and expressing them as objects, it is possible to simplify fuzzy set descriptions.

(2) Similarity between objects and frames as units of knowledge representation Objects are suitable for representing units of knowledge representation such as frames and semantic networks.

(3) Ease of program development By being based on object-oriented concepts, it is possible to improve the ease of modularization and reusability of software, and improve productivity.

Furthermore, by introducing the concept of meta-objects,
It realizes the following functions required by fuzzy intelligent information processing.

(1) Representation of fuzzy sets depending on the properties of the entire set (2) Realization of infinite calculation methods in fuzzy set calculations In MoNo, objects "have an internal state,
An entity J activated by a message, a metaobject is an "object that describes the behavior of an object"
It is. The relationship between a metaobject and an object is similar to the relationship between a class and an instance, but the metaobject is specified from the object side. Therefore, the independence of objects increases, and it becomes possible for one object to have a variety of functions.

The basic program in MoNo is written by message passing. The object is a receptor (re
ceρtor) and when you receive a message,
The metaobject matches the slam in the receptor with the message sent, and the action of the matched receptor is executed.

The action to be activated by a message changes depending on the state of the receiver object and so on, and cannot be determined until execution time. Therefore, execution is performed interactively using an incremental compilation method.

Since the program on the fuzzy computer of the barware architecture is written in MoN0, high-speed processing of fuzzy information can be expected by converting the following MoNo processing into hardware.

(1) Fuzzy set calculation processing (2) Numerical calculation processing such as fuzzy relationships and fuzzy integrals (3) Message transmission processing (4) Memory management processing associated with object generation and garbage collection (1) (2) are numerical processing , and (3) and (4) are symbolic processing.

In order to meet the above requirements (1) and (2), a fuzzy set processing unit that processes the most characteristic processing in fuzzy set calculations at high speed and a normal numerical calculation process are operated in parallel. can be satisfied.

To operate multiple arithmetic units in parallel, VLI W
(Very Long In5truction Wo
rd) method may be adopted. In the VL IW method, a compiler performs static program analysis to generate a code that is optimal for the arithmetic unit configuration, including bus and memory configurations. However, in MoNo, calculations are performed by message transmission as described below, so static analysis by a compiler is difficult. In other words, dynamic processing is performed by the interpreter.

In a computational model based on message transmission, when an object receives a message, it
Perform actions such as message transmission and computational instructions on data such as numbers and fuzzy sets.

As shown in 2, the following architecture is used as a method to efficiently process each arithmetic unit in parallel and perform fuzzy information processing at high speed, with instructions for each arithmetic unit dynamically generated during execution. Consider.

(1) Object management: Dynamically generates a sequential operation command stream for each arithmetic unit (object generation processing, message communication processing, etc.) to free up MoNo.

(2) Functional distributed instruction dipping method - A dynamically generated instruction stream is distributed into functionally distributed instruction streams for each computing unit, and parallel processing is performed without synchronization between the computing units.

(3) High-performance arithmetic instructions: By using the 3-operand high-performance arithmetic instructions in the memory-memory arithmetic model, there is no need to consider the arithmetic unit configuration when interpreting M o N o, and the generation of arithmetic instructions is reduced. make it easier.

(4) Synchronous processing: Synchronous processing between arithmetic units and bus arbitration are all supported by hardware, so that distributed instruction streams can be processed at high speed.

(5) Memory Architecture A memory that holds binary numerical data is divided into multiple banks, and multiple arithmetic units can access different banks simultaneously to achieve high-speed data transfer.

FIG. 1 shows a block diagram of the overall configuration of a fuzzy computer that performs the above processing.

In the architecture shown in FIG. 1, the main components are an interface 1 with the host computer, a symbol processing section 2, a numerical calculation section 3, a bus switch 4, an object management memory 5, and a memory panchromator 1 for numerical data.
Consists of 6n.

Interface 1 is in this example VMEbus B
The host computer and the symbol processing section 2 are coupled via o. The symbol processing unit 2 is an object management unit OMU
(Object Management Unit), which handles message communication and object generation in the object-oriented language MoNo, and processes high-performance arithmetic instructions.
Generates N5T. Symbol data such as a method for message passing that describes an object is written in an object management memory 5 connected to the symbol processing section 2 via a lotus B1. Note that the symbol processing section 2 (object management section) may be an interpreter whose basic configuration is a list processing mechanism that handles symbol data as a list.

The numerical calculation unit 3 uses different I! It is composed of a plurality of arithmetic units having high performance, and receives the high-performance arithmetic instruction IN5T generated from the symbol processing unit 2, and performs functional distributed parallel processing. Therefore, the numerical calculation unit 3 is a functional distributed instruction method calculation unit F I
P U (Function-Partition-e
d. Instruction-5treaga
Method Processing Unit)
It is called. An example of an arithmetic unit having different functions is a floating point arithmetic unit 3a (FPU: Floati
ng Po-1nt [In1t), integer multiplier 3
b (IM U = IntegerMultipl
ier Unit), fuzzy set operator 3c (FS
U: Fuzzy 5ets Unit). The high-performance arithmetic instruction INST is distributed and processed in these arithmetic units. Moreover, these computing units 3a, 3b,
A plurality of units (for example, two units each) having the same function are prepared for 3C--------, and instructions are processed in parallel.

The fuzzy set calculator 3c is mainly a vector/matrix calculator that can handle vector data whose elements are membership grades.

The arithmetic units 3a, 3b, 3c --------- are connected to buses B-, Bb, B, B, B, B, B, B, B, B, B, B, B, B, B, B, B, A, B, A, B, A, B, A, B, A, B, A, B, A, B, A, B, B, A, B, B, A, B, B, A, B, B, B, B, B, B, B, B, B,
. . . Table-coupled, and these buses are coupled to the memory panchros 1 to 6rl via the bus switch 4.

Memory panchros 1 to 6□ are divided according to the type of data to be stored. In the example shown in FIG. 1, memory panchromatic □ is for integer data, memory panchromatic 2 is for real number data, and memory panchromatic 3 is for fuzzy set data (vector data).

Bus B on the computing unit side, , Bb, B, ---
-, one is assigned to each data type, and the bus arbiter B
Arbitration is made by A to access the memory bank of the corresponding data type. Further, a plurality of different types of arithmetic units can access memory banks of corresponding data types in parallel (simultaneously).

The data type is specified by the symbol processing unit 2.

The designated data type is held in the bank table BT in the bus switch 4, and is stored in the arithmetic units 3a, 3b, 3c --...
・--1--- and memory panchromatic t, 6z ・- It is used as connection information. Usually, arithmetic units and memory banks of the same type are connected. When an arithmetic unit accesses a memory bank of a different data type, it issues a request to the bus switch controller BSC in the bus switch 4. In response to the issued request, the bus switch controller BSC enables the arithmetic unit to access the memory while avoiding memory access conflicts.

FIG. 2 shows the data structure of a high-performance calculation instruction given from the symbol processing section 2 (object management section) to the numerical calculation section 3.

High-performance calculation instructions read two or one data,
Instructs a series of operations to perform arbitrary processing and write the processing results.

As shown in Figure 2, the high-performance operation instructions for l words are:
It consists of five segments (10 to 14) each indicating an instruction tag, an operation code, a first read address, a second read address, and a write address. Segment 10 of the instruction tag is tag 1 that indicates the data type of the read address.
0a and tag I that indicates the data type of the write address
Consists of Q b. The data type of the read address of tag 10a is the first and second data type stored in segment 12.13.
Indicates the data type of the read address. Further, the data type of the write address of the tag fob indicates the data type of the write address stored in the segment 14. The operation segment 11 includes a tag lla indicating the type of arithmetic unit, and a portion 11b indicating an instruction to the arithmetic unit designated by the tag lla. Tag lla indicating the type of computing unit
is the floating point arithmetic unit 3 in the numerical arithmetic unit 3 in FIG.
a, the integer multiplier 3b, the fuzzy set arithmetic unit 30, etc. The arithmetic instruction portion 11b indicates instructions (opcodes) to the arithmetic unit to perform addition, subtraction, multiplication, division, logical operations, and the like.

Segment indicating the first and second read addresses) 12.13
indicates the address of the memory where each data of the first argument and the second argument of the operation is stored. The data types of these arguments match the data types indicated by the tag loa.

The segment 14 indicating the write address indicates the memory address for storing the operation result. The data type of the operation result is indicated by the tag 10b.

In the high-performance arithmetic instruction shown in FIG. 2, there is a restriction that the type of data (first and second arguments) at the read address indicated by tag 10a must match the type of arithmetic unit indicated by tag lla. It is given. For example, data read by an instruction that performs an integer operation is always of integer type. The data written as an argument is not necessarily of the same type as the arithmetic unit. Therefore, when performing calculations between different data types, it is necessary to execute a data type conversion instruction in advance to make the data type suitable for the arithmetic unit.

In this way, by limiting the read data,
Synchronization processing between computing units, which will be described later, can be facilitated.

Tags 10a, 10b, and 11a corresponding to each type of read data, write data, and arithmetic unit are attached for synchronization processing and selection of arithmetic unit.

FIG. 3 shows a block diagram of the main parts of the numerical calculation section.

The high-performance operation instruction lN5T generated from the symbol processing unit 2 (object management unit OMU) is stored in the sequential instruction queue (SIQ).
) 31 in the order of occurrence, and the instruction distributor (ID)
32 in sequence. The instruction distributor 32 distributes the instruction I according to the tag lla attached to the arithmetic instruction indicating the type of arithmetic unit.
NST is calculated by computing units 3a, 3b, 3c ・−・・−・−
to be distributed.

The arithmetic units 3a, 3b-, 3c--------, as one (3a) is shown in FIG. It consists of 36 calculation units (PU). Arithmetic unit instruction queue 34
holds an arithmetic instruction IN5T to be processed by the arithmetic unit 36. A flag bit is added to the retained arithmetic instruction for synchronization processing with other arithmetic units. The synchronization controller 35 sends the arithmetic instruction IN5T of the arithmetic unit instruction queue 34 to the arithmetic unit 36 without referring to the flag bit of the arithmetic unit instruction queue 34, considering synchronization with other arithmetic units. The arithmetic instruction unit 36 processes the sent high-performance arithmetic instructions in parallel.

Arithmetic units 3a, 3b, 3c provided for each type of arithmetic operation such as an integer arithmetic unit, a floating point arithmetic unit, a fuzzy arithmetic unit, etc.
------- is coupled to one arithmetic unit discriminator (FD) 33. The arithmetic unit discriminator 33 is an arithmetic unit 36
It is determined to which synchronization controller 35 the signal for synchronization obtained from the synchronization controller 35 is to be sent.

Placement plate processing Next, referring to the flowchart in FIG. 4 together with FIG.
The synchronization process between a, 3b, 3c---1 will be explained.

The high-performance arithmetic instructions IN5T are sequentially held in the instruction queue 31 in the order in which they are generated by the symbol processing unit 2.

The sequential instruction queue 31 includes, for example, eight instruction buffers, and when a buffer becomes vacant, the signal full is made inactive and the symbol processing unit 2 is notified.

The symbol processing unit 2 sequentially sends new operation instructions to the instruction queue 31 along with the write signal -rite.

In the example of instruction words accumulated in the sequential instruction queue 31 in FIG. 4, I and R of instruction tags 10a and 10b are integers, respectively.
ALU of operation tag 11a, rM
U, FPU, etc. indicate the type of arithmetic unit such as an integer arithmetic unit, an integer multiplier, a floating point arithmetic unit, etc., and +, × in the instruction part 11b
, #, etc. indicate instructions to the arithmetic unit such as addition, multiplication, and data type conversion. The read addresses 12 and 13 and the write addresses 14, 31, SR, Ll, LR, etc., indicate memory addresses that treat integers and real numbers (floating point numbers) as short words or long words.

The instruction distributor 32 sequentially reads instructions from the head of the instruction queue 31 in response to the signal read, and selects the instructions from the arithmetic unit 3 to be executed.
a, 3b--...- to the arithmetic unit instruction queue 34. The synchronization controller 35 determines whether the first instruction of the four instruction buffers IB of the arithmetic unit instruction queue 34 is executable, and if it is executable, sends it to the arithmetic unit 36. Each instruction buffer IB of the arithmetic unit instruction queue 34 is provided with a flag bit FB for synchronization control.

The synchronization controller 35 has an invalid address table 35a for performing synchronization control by determining whether or not an address used when executing an operation is valid. This invalid address table 35a consists of five invalid address buffers IAB and a flag bit FB attached to each buffer. Furthermore, the synchronization controller 35 includes an instruction monitoring section 35b in the arithmetic unit 36 that holds an instruction to be executed next and monitors an invalid state of an address used by the instruction.

When the instruction monitoring unit 35b determines that the invalid address has been resolved, the held instruction is sent to the arithmetic unit 36 and the arithmetic operation is executed.

Note that the 32 arithmetic units 36 shown in FIG. 4 are different types of arithmetic units 3a, 3b.
・It corresponds to, for example, an integer arithmetic unit, an integer multiplier, and a floating point arithmetic unit.

Synchronization between arithmetic units is performed by checking the address of write data of an unexecuted preceding instruction and the address of read data of a succeeding instruction. In FIG. 4, there are instructions No. 1-No. 8 in the sequential instruction queue 31, and after all these instructions are distributed to the arithmetic unit instruction queue 34, the situation when the instruction No. 1 is executed is shown. has been done. Arithmetic unit instruction queue 3
Flag bit f7 of No. 4 flag bit FB indicates that "work" is set when the No. n instruction is sent to the arithmetic unit instruction queue 34.

When distributing an instruction from the instruction distributor 32 to the arithmetic unit instruction queue 34, an instruction-rite signal is output based on the arithmetic unit type tag 11a in the instruction, and the command is sent to the specified arithmetic unit 3a.
, 3b ---, the instruction is transferred to the arithmetic unit instruction queue 34. At this time, the flag next to the last queued instruction in the other arithmetic unit instruction queue 34 is checked, and if it is not set, the flag write
Output the e signal and set a flag. For example, when reading the instruction No. 2 (integer operation instruction ALU in this case) from the sequential instruction queue 31 into the operation unit instruction queue 34 of the ALU, queuing of another operation unit (IMU in this case) (in this case, No.
, 1 (integer multiplication instruction IMU)) is set to fz=1.

At the same time, a write signal is output and the corresponding IM
In the invalid address table 35a of the synchronous controller 35 of U,
Write data address (312 for instruction No. 2)
Write. At this time, the arithmetic unit instruction queue 34 of the IMU
If the flag is set, the invalid address table 35
A flag is also set in the flag bit FB corresponding to a (f2
).

In this way, by using the flag of the arithmetic unit instruction queue 34 and the flag of the invalid address table 35a in the synchronization controller 35, the address to be checked is determined when sending an instruction from the arithmetic unit instruction queue 34 to the arithmetic unit 36. You can know the check range. This instruction distributor 32
In the synchronous processing of It is only necessary to operate (check) the ALU and IMU. Further, in the case of a type conversion instruction, it is only necessary to perform the same operation on the arithmetic unit of the data type to which the conversion data is written.

Next, the process of transferring an instruction from the arithmetic unit instruction queue 34 to the arithmetic unit 36 by the synchronization controller 35 will be described. If the instruction read from the arithmetic unit instruction queue 34 has a flag set, the flag closest to the head of the invalid address table 35a is erased by the flag remove signal. Then, the addresses 12 and 13 of the read data of the read instruction and the addresses from the beginning of the invalid address table 35a to before the flagged address are checked. If the addresses match, the instruction is written into the instruction register IR of the instruction monitoring section 35b, and the matching address is written into the invalid address register JAR.

For example, when reading instruction No. 2 (ALU instruction), the address S1, I1 of the read data of this instruction is
3 and the starting address SII of the invalid address table 35a.
Compare with. Address Sll is instruction No. 1 (I
This is the write address used by instruction No. 1 written in the invalid address table 35a of the ALU when transferring the MU instruction).

Therefore, in this case, the write address Sll of instruction No. 1 and the read address SII of instruction No. 2 match. This means that if the IMU completes the operation of the instruction No. 1 and the operation result does not enter the write address SII, the ALU cannot read the argument data from the address 311 to perform the operation of No. 2. Indicates that this is not the case. Therefore, in this case, the instruction No. 2 is entered into the instruction register IR of the instruction monitoring unit 35b of the ALU, and the matching address Sll is entered into the invalid address register IAR.
enters.

The instruction monitoring unit 35b of the synchronous controller 35 waits for the arithmetic unit to write data to the address of the invalid address register IAR, and then sends the instruction of the instruction register IR to the arithmetic unit 36 using a write signal.

If the addresses do not match, the instruction is immediately sent to the arithmetic unit without waiting.

The arithmetic unit discriminator 33 monitors the address to which the arithmetic unit 36 has written and the tag indicating its data type, and when it learns that a write has occurred due to the end signal from the arithmetic unit 36, it identifies a tag of the same type. The write address is notified to the synchronization controller 35 of the arithmetic unit by a write signal. Therefore, as shown in FIG. 4, the arithmetic unit discriminator 33 performs a transfer process such that, for example, the ALU and IMU mutually transfer the write address at the end of the operation.

The synchronization controller 35, which has been notified of the completion of writing from the arithmetic unit discriminator 33, compares the transferred write address with the invalid address set in the invalid address register JAR of the arithmetic unit monitoring unit 35b, and if they match. To do this, the instruction in the instruction register IR is sent to the arithmetic unit 36. Then, the write address notified from the invalid address register IAR is erased.

FIG. 5 shows the configuration of the arithmetic unit 36. Computing unit 36 receives and executes executable high-function instructions.

The inside of the arithmetic unit is divided into a data load section 36a, an execution section 36b, and a data store section 36C, which simultaneously process thread access and instruction execution. In order to execute this two-stage pipeline processing, an instruction buffer 36d is provided to store two consecutive instructions. Data load section 3
At 6a, the address generator 36e outputs an address to the memory based on the read address 1.2 and write address supplied from the instruction buffer 36d. When data is read from memory for pipeline processing, the address comparator 36f checks whether the read address matches the write address of the previous instruction and synchronizes the arithmetic unit. Data reading from the memory is performed based on a control signal output from the read controller 36g and an address output from the address generator 36e. The read data is supplied to the calculation element 36j of the execution unit 36b via the input register 36h. On the other hand, the operation code from the instruction buffer 36d is given to the arithmetic element 36j via the execution controller 36i. The output of the calculation element 36j is controlled by the write controller 36k and is sent to the output register 3.
6m to memory. The write address is created by the address generator 36e according to the command stored in the command buffer 36d, and output to the pass line connected to the memory.

〔Effect of the invention〕

As described above, the information processing device of the present invention includes a symbol processing unit that performs symbolic processing in an interpretive manner based on message transmission between objects, and a numerical calculation unit that performs numerical calculations associated with symbol processing in parallel with the symbolic processing. This system dynamically generates a sequential operation instruction stream from the symbol processing section and supplies it to the numerical operation section. Therefore, according to the present invention, when performing symbolic processing that involves numerical operations (fuzzy set operations, etc.) such as fuzzy information processing, program description is good, program productivity is increased, and parallel processing of symbols and numerical values is possible. The processing enables high-speed processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of a fuzzy computer to which the present invention is applied, FIG. 2 is a configuration diagram of high-performance arithmetic instructions generated by the symbol processing section of FIG. 1, and FIG. FIG. 4 is a block diagram showing details of the numerical calculation section, FIG. 4 is an instruction flow chart showing synchronization processing between calculation units, and FIG. 5 is a block diagram showing details of the calculation unit. In addition, in the symbols used in the drawings, 1 ・−・−・・・・−・−Interface 2−
...-- Symbol processing section 3 .-------1...- Numerical calculation section 4 ...-
・−・・−・・−・ Bus switch 5−・・・−・
・・−Object management memory 61 to 6n −・−・−
. . . Memory bank 31 . . . Sequential instruction queue 32 . . . Instruction distributor 36 . . . Arithmetic unit discriminator arithmetic unit instruction queue synchronization discriminator arithmetic unit

Claims (8)

[Claims] (1) Equipped with a symbol processing unit that performs interpretive symbol processing based on message transmission between objects, and a numerical calculation unit that performs numerical operations associated with the above-mentioned interpretive symbol processing in parallel with the above-mentioned symbol processing. An information processing device that performs symbol processing and numerical processing in parallel, wherein the symbol processing unit dynamically generates a sequential operation instruction stream for the numerical calculation unit. (2) The information processing device according to claim 1, wherein the numerical calculation unit includes a fuzzy set calculation unit. (3) The information processing device according to claim 2, wherein the numerical calculation unit includes a real number calculation unit. (4) The information processing device according to claim 2 or 3, wherein the numerical calculation unit includes an integer calculation unit. (5) The numerical arithmetic unit includes at least a fuzzy set arithmetic unit, a real number arithmetic unit, and an integer arithmetic unit with different data types, and each instruction of the sequential arithmetic instruction stream generated by the symbol processing unit includes: A tag indicating a type of the arithmetic unit is attached, and the numerical calculation unit further includes an instruction distributor that distributes instructions to specified arithmetic units based on the tag of the instruction. 1. The information processing device according to 1. (6) The arithmetic instruction is comprised of a memory arithmetic type instruction word having a three-operand configuration with three address specifications for storing the first and second arguments and the values of the arithmetic results. The information processing device described. (7) Each of the arithmetic units includes a plurality of arithmetic units of the same data type, and detects a match between the write address and the read address of the three operands among the instructions of the arithmetic instruction stream, and selects a certain arithmetic unit. Claim 6, wherein each arithmetic unit is provided with a synchronization controller that causes another arithmetic unit to execute a subsequent instruction that involves reading data from the write address after completion of writing the arithmetic result by executing the preceding instruction. The information processing device described in . (8) The information processing apparatus according to claim 5, wherein each of the arithmetic units includes a mutually independent bus and a memory coupled to the bus.