JPH047108B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a read-only semiconductor memory device, particularly a mask programable read-only semiconductor memory device in which memory information is written based on a mask of a specific process.
(hereinafter referred to as Mask-ROM).

[Prior art]

Generally, Mask-ROM is as shown in Figure 1.
Memory cell MC ₁₁ consisting of MOS transistor,
MC ₁₂ ,...MCnm are arranged in a matrix in the row and column directions, and correspondingly word lines are provided for each column.
W ₁ , W _{2 .} . . Wn is connected to bit lines B ₁ , B ₂ . . . for each row.
...Bm is installed. Each memory cell has a structure in which when an "H" potential is applied to the gate electrode, an H level or L level appears on the bit line to which the drain is connected, and desired storage information is stored. It is something that exists. For example, a memory cell in which memory information "1" is stored is composed of a MOS transistor that maintains a non-conducting state even if an H voltage is applied to its gate electrode, and a memory cell in which memory information "O" is stored is It is said to consist of a MOS transistor that becomes conductive when an H potential is applied to its gate electrode. A MOS that maintains a non-conducting state even if an “H” potential is applied to such a gate electrode.
The structure of a memory cell consisting of a transistor (hereinafter referred to as a non-conducting memory cell) is shown in Figures 2a and b.
The one shown in FIG. This is what is being done.

As is clear from these FIGS. 2 a, b and 3 a, b, the non-conducting MOS has a thick gate insulating oxide film 10 provided directly under the gate electrode 6a, and the gate electrode 6a has an "H" level. This structure maintains a non-conductive state by preventing the formation of an inversion layer on the surface of the semiconductor substrate 1 between the source region 4a and the drain region 3a even when a potential is applied.
In FIGS. 2 and 3, 1 is a semiconductor substrate made of P-type silicon, 2 is a thick field oxide film formed in an element isolation part on one main surface of this semiconductor substrate 1, 3a, 3b, and 4a. , 4b are drain and source regions formed by diffusing N-type impurities into one main surface of the semiconductor substrate 1 and are spaced apart from each other; 5 is the semiconductor substrate between the source regions 4a, 4b and the drain regions 3a, 3b; Thin gate oxide films 6a and 6b with a thickness of about 500 mm formed on one main surface of 1 are the gate oxide films 5a and 5.
A gate electrode is formed on the word line in substantially the same shape as this gate oxide film, and is formed integrally with the word line. 7 is a CVD oxide film formed on the entire surface of the semiconductor substrate 1; 8a and 8b are contact holes formed by etching this CVD oxide film 7 to reach the drain regions 3a and 3b; 9;
is an aluminum wiring layer formed to fill the contact holes 8a, 8b and connect to the drain regions 3a, 3b, and also serves as a bit line. Reference numeral 10 denotes a thick gate oxide film formed between the gate oxide film 5 and one principal surface of the semiconductor substrate 1 in the non-conductive memory cell.

When a Mask-ROM is configured by the conducting memory cells and non-conducting memory cells configured in this manner, the arrangement is, for example, as shown in FIG. 4.

Figure 4 shows 4 columns 2 which are part of Mask-ROM.
It is a diagram showing a state in which eight memory cells are arranged in a row, where MCa ₁₁ , MCa ₃₁ , MCa ₄₁ and MCa ₂₂ are non-conductive memory cells, and MCa ₂₁ , MCa ₂₂ , MCa ₃₂ ,
and MCa ₄₂ are constructed from conductive memory cells.

In each memory cell arranged in this way, the source regions 4a, 4b or the drain regions 3a, 3b of adjacent memory cells are made as common as possible, thereby achieving high integration. The source regions 4a and 4b of each memory cell are connected to ground lines GND _a1 , GND _a2 ,
GND _a3 and gate electrodes 6a and 6b are word lines.
The aluminum wiring layer 9 for W _a1 , W _a2 , W _a3 , and W _a4 also serves as bit lines.

In Mask-ROM as described above, conduction or non-conduction of the memory cell is determined depending on whether or not the gate insulating oxide film 10 is interposed between the gate electrode of the memory cell MC and the semiconductor substrate 1. , it is possible to share the drain regions 3a, 3b or the source regions 4a, 4b, which is very efficient in terms of the degree of integration.

By the way, in the manufacturing method of such Mask-ROM, a field oxide film 2 and a gate insulating oxide film are formed on the semiconductor substrate 1 according to the storage information specified by the user. A film 10 is formed at the same time, and then gate oxide films 5, 5 are formed, and then gate electrodes 6a, 6b are formed. Thereafter, using the field oxide film 2 and gate electrodes 6a, 6b as masks, N-type impurities are ion-implanted and diffused to form drain regions 3a, 3b and source regions 4a, 4b in self-alignment, and then a CVD oxide film 7 is formed. After forming on the entire surface of the one formed in the previous step, this CVD oxide film 7 is etched to form contact holes 8a and 8b.
This is to form an aluminum wiring layer 9.

However, Mask-
The problem with ROM is that there are many steps after the formation of the gate insulating oxide film 10, which is the process of writing storage information specified by the user, and as a result, the time from receiving the user's order until delivery to the user is extremely long. It was hot.

[Summary of the invention]

This invention has been made in view of the above points, and is a non-conducting memory cell consisting of a MOS structure between a gate electrode and the main surface of a substrate, insulated from both, and electrically connected to a source region. As such, we propose a Mask-ROM that reduces the number of steps after determining conductive and non-conductive memory cells, that is, the steps after writing memory information, thereby shortening the delivery time.

[Embodiments of the invention]

An embodiment of this invention is shown below in Figures 6 to 9.
This will be explained based on the diagram. 6a and 6b show non-conducting memory cells, 11a is the first
A first floating gate electrode is provided on one principal surface of the semiconductor substrate 1 between the source region 4a and the first drain region 3a with a first floating gate oxide film 12a having a thickness of about 700 mm interposed therebetween. is connected to the first source region 4a. Therefore, in this non-conductive memory cell, the potential of the first floating gate electrode 4a is the same as that of the first source region 4a, that is, 0V, and the first
Even if a potential of about 5 V is applied as an "H" potential to the first gate electrode 6a provided on the floating gate electrode 11a via the first gate oxide film 5a of 700 mm, an inversion layer is formed on the surface of the semiconductor substrate 1. The first drain region 3a and the first source region 4 are not formed.
a is not conductive.

On the other hand, FIGS. 7a and 7b show a conductive memory cell, and 11b is surrounded by a second floating gate oxide 12b and a second gate oxide 5.
b and field oxide film 2,
This is a second floating gate electrode provided between one main surface between the drain region 3a and source region 4b of the semiconductor substrate 1 and the second gate electrode 6b. Therefore, in this conductive memory cell,
When a voltage higher than the threshold voltage of 1.2 to 1.4V, for example, a potential of about 5V is applied as an "H" potential to the second gate electrode 6b, the electric field is blocked by the second floating gate electrode 11b. Instead, an inversion layer is formed between the second source region 3b and the second drain region 4b in the semiconductor substrate 1, and conduction is established between the second source region 3b and the second drain region 4b.

When a Mask-ROM is configured by the conductive memory cells and non-conductive memory cells configured in this manner, they are arranged as shown in FIG. 8, for example.

FIG. 8 is a diagram showing a state in which eight memory cells are arranged in four columns and two rows, which are part of Mask-ROM, and MCb ₁₁ , MCb ₃₁ , MCb ₄₁ , and MCb ₂₂ are the sixth memory cells.
Due to the non-conducting memory cells shown in figures a and b,
MCb ₂₁ , MCb ₁₂ , MCb ₃₂ and MCa ₄₂ are shown in Figure 6a,
This figure shows a case constructed from the conductive memory cells shown in FIG. In each memory cell arranged in this way, the source regions 4a, 4b or drain regions 3a,
3b are made common to each other as much as possible, thereby achieving high integration. Also, the source regions 4a, 4b of each memory cell
are the ground lines GNDb ₁ , GNDb ₂ , GNDb ₃ , and the first gate electrode 6a and the second gate electrode 6b are the word lines.
The aluminum wiring layer 9 for Wb ₁ , Wb ₂ , Wb ₃ and Wb ₄ also serves as bit lines.

Next, a method for manufacturing the Mask-ROM configured as described above will be explained with reference to FIG. First, a field oxide film 2 is formed (step) on a semiconductor substrate 1, and then a P-type impurity is implanted (step) to determine Vth, and then an N-type impurity is selectively implanted. Second drain region 3
A, 3b and first and second source regions 4a, 4b are formed (steps). Next, an oxide film with a thickness of about 700 mm is laminated all over the main surface of the semiconductor substrate 1.
Second floating gate oxide film 12a, 12b
form (step). Items formed in this manner are stored until an order is received from a user. Note that since one main surface of the semiconductor substrate 1 is covered with a 700% oxide film, one main surface of the semiconductor substrate 1 and the first and second source regions 4
a, 4b and first and second drain regions 3a, 3
b is protected. When an order is received from a user for a Mask-ROM having desired storage information, a mask is used according to the storage information to make the first mask ROM in the memory cell portion non-conductive.
A contact hole 13 is formed (stepped) in the floating gate oxide film 12a on the source region 4a, and then a first polysilicon layer is formed (stepped) over the entire surface. At this time, the first polysilicon reaches the semiconductor substrate 1, filling the contact hole 13. This first polysilicon layer is etched to form first and second floating gate electrodes 11a and 11b. Thereafter, an oxide film and then a second polysilicon layer are laminated, and they are etched into a desired shape to form gate oxide films 5a, 5b and gate electrodes 6a, 6.
b. After that, a CVD oxide film 7, a contact hole 8, and an aluminum layer 9 are formed (step XI) in the same way as shown in the conventional example to obtain a ROM as shown in FIGS. 6 to 8. be.

In addition, Mask− with the above structure
In the ROM, since the second floating gate electrode 11b is provided in the conductive memory cell, the gate electrode 6 of the non-conductive memory cell and the conductive memory cell are
Since the heights of the gate electrodes 6a and 6b are the same, there is less risk of disconnection of the word line, which forms part of the gate electrodes 6a and 6b, even if a plurality of memory cells are arranged. In this case, there is no need to provide the second floating gate electrode 11b.

In this case, in the step in FIG.
It is only necessary to remove the floating gate electrode 11a by etching, leaving only the floating gate electrode 11a. In this case, the threshold voltage of the conducting memory cell is lowered.

〔Effect of the invention〕

As explained above, the present invention provides a Mask-ROM having a conductive memory cell and a non-conductive memory cell having a MOS structure, in which a non-conductive memory cell is connected to a first floating gate electrode partially connected to a source region. is provided between one main surface of the semiconductor substrate between the source region and the drain region and the first gate electrode in a manner that is insulated from the one main surface of the semiconductor substrate and the first gate electrode. In addition, it is possible to form conductive and non-conductive memory cells with high reliability, and the process of writing memory information and subsequent processes can be reduced, which shortens the delivery time. This has the effect of being able to respond to

[Brief explanation of drawings]

Figure 1 is a schematic diagram of the memory portion of Mask-ROM, and Figures 2 to 5 are conventional Mask-ROM memory sections.
FIG. 2a is a pattern layout diagram of a non-conducting memory cell, FIG. 2b is a cross-sectional view of FIG. 2a, FIG. 3a is a pattern layout diagram of a conductive memory cell, and FIG. FIG. 3 is a cross-sectional view of FIG. 3a, FIG. 4 is a pattern layout diagram in which a plurality of memory cells shown in FIGS. 6A shows a pattern layout of a conductive memory cell, FIG. 6B is a cross-sectional view of FIG. 6A, and FIG. 7A is a pattern layout of a non-conducting memory cell. , FIG. 7b is a cross-sectional view of FIG. 7a, FIG. 8 is a pattern layout diagram in which a plurality of memory cells shown in FIGS. 6 and 7 are arranged, and FIG. 9 is a flowchart showing the manufacturing process. . In the figure, 1 is a semiconductor substrate, 3a and 3b are first and second drain regions, 4a and 4b are first and second source regions, respectively, 5a and 5b are first and second drain regions, respectively.
The second gate oxide films 6a and 6b are the first and second gate oxide films, respectively.
Gate electrodes 11a and 11b are first and second floating gate electrodes, respectively, and 12a and 12b are first and second floating gate oxide films, respectively.
Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] 1. A first source region and a first drain region of a second conductivity type that are provided on one main surface of a semiconductor substrate of a first conductivity type and are spaced apart from each other;
a first floating gate electrode provided on one main surface of the semiconductor substrate between the drain region and the semiconductor substrate via a first floating gate oxide film and partially connected to the source region; a non-conductive memory cell having a first gate electrode provided between the source region and the drain region on the gate electrode with a thin first gate oxide film interposed therebetween;
A second source region and a second drain region of a second conductivity type provided on one main surface of the semiconductor substrate at a distance from each other, and a main surface of the semiconductor substrate between the second source region and the second drain region. 1. A read-only semiconductor memory device comprising a conductive memory cell having a second gate electrode provided on the surface thereof with a thin second gate oxide film interposed therebetween. 2. The conducting memory cells and the non-conducting memory cells constitute memory cells arranged in the column direction, and the drain regions of the conducting memory cells and the non-conducting memory cells are respectively located in the same row and arranged adjacently. 2. The read-only semiconductor memory device according to claim 1, wherein the read-only semiconductor memory device also serves as a drain region of a memory cell. 3. The source region of the conducting memory cell and the non-conducting memory cell is formed of a part of a second conductivity type diffusion region formed linearly in the column direction, and is grounded. Paragraph 1 or 2
A read-only semiconductor storage device as described in 2.