JPH0471024A - Barrel shifting circuit - Google Patents

Abstract

PURPOSE:To shorten a delay time and to reduce a circuit size by extracting the data of Q bits from (m) barrel shifters. CONSTITUTION:A decoder 10 decodes shift variable specifying signals S1 to S4 and supplies decoded outputs d0 to d15 (namely, specified shift variable) of 16 bits to barrel shifters 11, 12. Thereby, each barrel shifter selects and outputs 16 bits in a certain range corresponding to the shifted variable from 31-bit input data (16 bits on MSB side and 15 bits on the LSB side). Data DOUT to be finally outputted are 32-bit data constituted of data selected and outputted from the barrel shifter 11, i.e. 16-bit data DM (O0 to O15) on the MSB side, and data selected and outputted from the barrel shifter 12, i.e. 16-bit data DL (O16 to O31) on the LSB side.

Description

[Detailed Description of the Invention] (Summary) Barrel shift circuits, particularly circuit configurations for matching source data to the word width of destination data during data transfer in image processing devices, etc., to shorten delay time and A barrel shift circuit that aims to reduce the circuit scale and selects and outputs Q bits in a certain range according to the amount of shift from input data of P bits; however, Q<P. m barrel shifters that respectively shift input data based on an instruction signal; and a selection circuit that distributes and inputs the P bit input data to the m barrel shifters approximately every P/m bit based on a selection signal. and said m
The configuration is such that the Q-bit data is taken out from the four barrel shifters.

(Industrial Application Field) The present invention relates to a barrel shift circuit, and particularly to the configuration of a circuit for matching source data to the word width of destination data during data transfer in an image processing device or the like.

[Prior art and problems to be solved by the invention]

A known typical barrel shifter, for example, as shown in FIG. 5, selects N bits (indicated by hatching) of t according to the shift amount from input data of 2N-1 bits (odd bits). and output it. Here, N indicates the number of bits constituting one word.

Conventionally, circuits that perform high-speed data transfer have been realized by using such barrel shifters.

However, as data transfer speeds have increased and the amount of information has increased in recent years, the word width of transfer data has also been expanded. As a result, the circuit scale increases, and the operation delay time during data transfer increases accordingly, which is becoming a problem.

The present invention was created in view of the problems in the prior art, and an object of the present invention is to provide a barrel shift circuit that can shorten delay time and reduce circuit scale.

[Means for Solving the Problems] In order to solve the above problems, the present invention distributes input data of multiple bits to each of a plurality of barrel shifters whose input bit width is smaller than that of a normal barrel shifter. Data of a predetermined bit width is selectively output by inputting the data and performing a predetermined shift process.

Therefore, according to the present invention, as shown in the principle block diagram of FIG.
. 0. A barrel shift circuit that selects and outputs
m barrel shifters L to 1a+ each perform shift processing of input data based on the shift amount instruction signal C1, and based on the selection signal C2, the P bit input data is transferred to the m barrel shifters approximately P/m bits. There is provided a barrel shift circuit characterized in that it is equipped with a selection circuit 2 that distributes and inputs data to each of the m barrel shifters, and extracts the Q-bit data from the m barrel shifters.

[Effect]

According to the configuration described above, the barrel shifter 1. Since each input bit width of ~1 m is approximately 1/m of the normal width, the time required for shift processing when selecting output data (ie, operation delay time) is also shortened accordingly.

Also, barrel shifter 1. Since the scale of each circuit of ~1 m is reduced to about 1/m2 of the normal size, the scale of the barrel shifter as a whole is reduced to about 1/m.

For example, when the number of barrel shifters is 2, it is approximately 1/2
The circuit scale is reduced to . In this case, although the circuit area increases by the selection circuit 2, this amount is sufficiently offset by the reduction in the area occupied by the barrel shifter, so it is possible to reduce the circuit scale of the barrel shift circuit as a whole. Become.

Note that other structural features and details of the operation of the present invention will be explained using the embodiments described below with reference to the accompanying drawings.

〔Example〕

FIG. 2 shows the configuration of a barrel shift circuit as an embodiment of the present invention.

The barrel shift circuit of this embodiment includes a decoder 10, two barrel shifters 11 and 12, and three multiplexers 13 to 12.
15, and 32 in the range corresponding to the shift amount from the 63-bit (■.~I,2) input data D1.4.
Output data D of bits (00-031). Select and output UT. In this case, input data I0 to 162 are four blocks Do (Io to ■3.), D+ (Li to ■, υ
, D2 (132-I4.) and D3 (Ls-16g
) and processing is performed.

80 to S indicate 5-bit external control data, of which 4 bits (s+-54) are input to the decoder 10 as a shift amount instruction signal, and the remaining 1 bit (So) is input to each multiplexer 13 to 15 as a selection signal. is input.

Multiplexers 13 to 15 each receive input A and selection signal S when selection signal S0 is at "L" level. Power S″H”
At level, input B is selected and output. In this case, as inputs A and B of multiplexer 13, 16
Bit data D. (Io=Ls) and 16-bit data DI (116 to 1.□) are supplied. Similarly,
1 each as inputs A and B of multiplexer 14.
6-bit data D+ (1++, ~■3.) and 16
Bit data D2 (13□ to I47) is supplied, and 15 bits on the MSB side of data D2 (I3□ to 6) and 15 bits of data D3 (Le""It, □) is supplied.

The decoder 10 decodes the shift amount instruction signal S1-S4 and supplies 16-bit decoded outputs d0 to d1. to the barrel shifters 11.12. (i.e., the shift amount instruction amount). As a result, each barrel shifter has 31 pins I.
input data (16 bits on the MSB side and 15 bits on the LSB side)
16 bits within a range corresponding to the shift amount are selected and output from the bits). In this case, the output of the multiplexer 13 is supplied to the MSB side 16 bits of the input of the barrel shifter 11, and the multiplexer 14 is supplied to the LSB side 15 bits.
The MSB side 15 bits of the output are provided. Similarly, the output of the multiplexer 14 is supplied to the MSB side 16 bits of the input of the barrel shifter 12, and the output of the multiplexer 15 is supplied to the LSB side 15 bits.

Data D that is finally output. UT is barrel shifter 1
The data selectively output from 1, that is, the 16-bit data D on the MSB side (00 to 01.), and the barrel shifter 1
This is 32-bit data consisting of the data selectively output from 2, that is, the LSB side 16-bit data DL (016 to 0, 1).

FIG. 3 shows input data 10 to l1z (four data blocks Do+J+Dz+) to the barrel shifter 11.12.
The form of the distribution of D,) is shown.

In the same figure, (a) shows the form of distribution when 32-bit data to be selectively output is in the range of data blocks D0 to Dt (indicated by hatching). This means that multiplexers 13 to 15 input A in the configuration shown in FIG.
This corresponds to the case where the selection signal S0 is selected (that is, the selection signal S0 is at the "L'" level).

On the other hand, FIG. 3(b) shows the form of distribution when the 32-pin data to be selectively output is in the range of data blocks D1 to D (indicated by hunting), and the multiplexers 13 to 15 input B This corresponds to the case where the selection signal S is selected (that is, the selection signal S is at the "H" level).

FIG. 4 shows an example of the configuration of the barrel shifter 1L12.

Each barrel shifter is composed of 16×16 MOS transistors arranged in a matrix. For example, taking the barrel shifter 11 as an example, the source (or drain) of each MOS transistor is connected to each signal line of 31-bit data (for example, I0 to I3°) selectively output from multiplexers 13 and 14, and each MO3I-
The drain (or source) of the transistor is connected to each signal line of 16-bit output data 00 to 0,5, and the gate of each MOS transistor is connected to each signal line of decode outputs d0 to dl of the decoder 10. There is.

For example, if only the data d2 among the outputs d0 to d15 of the decoder 10 is at the "H" level and all other data are at the "L" level, in the illustrated example, the input data ■2 to Il'1 are the output data 00 to It is selectively output as 0.5.

The barrel shifter 12 is also configured in the same manner, so its explanation will be omitted.

The table below shows the correspondence between each bit configuration of external control data 80 to S4 and output data 00 to 031.

Table In this embodiment, 63-bit input data 10 to I6
Divide into 2 and input, and finally 32 bits of data D.

ut (00-031) is selectively output.

If this same selection output were to be performed using one barrel shifter as in the conventional type, the barrel shifter would consist of MOS transistors arranged in a 32 x 32 matrix, as can be inferred from the configuration shown in FIG. Must be arranged and configured. That is, when comparing barrel shifters alone, the circuit scale of the conventional type is approximately four times that of this embodiment, and when comparing barrel shifters as a whole, the former is approximately twice as large as the latter.

In other words, according to this embodiment, the circuit scale of the entire barrel shifter can be reduced to about half the normal scale. In this case, although the circuit area increases by the amount of multiplexers 13 to 150, this amount can be sufficiently offset by the reduction in the area occupied by the barrel shifter.

In addition, the input bit width of each barrel shifter 11 and 12 is 31
In the case of the conventional type (corresponding to Fig. 2, it is 6 bits).
3 bits). Therefore, the time required for shift processing when selecting output data, that is, the operation delay time can also be reduced.

In the above-described embodiment, a case has been described in which the input data is divided into two barrel shifters and inputted, but it goes without saying that the number of divisions is not limited to two. In that case, there is a disadvantage that as the number of divisions increases, the data selection output control by the multiplexer becomes complicated.
This is more advantageous from the viewpoint of reducing circuit scale and delay time.

(Effects of the Invention) As explained above, according to the present invention, the time required for shift processing when selecting output data (operation delay time) can be shortened, and the area occupied by the entire circuit can be reduced. is also possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of a barrel shift circuit according to the present invention, FIG. 2 is a block diagram showing the configuration of a barrel shift circuit as an embodiment of the present invention, and FIGS. FIG. 4 is a circuit diagram showing an example of the configuration of the barrel shifter in FIG. 2; FIG. 5 is a diagram showing the concept of shift processing by the barrel shifter. (Explanation of symbols) 1, ~il, 11.12...barrel shifter, 2...
・Selection circuit, 13 to 15...Multiplexer, DIN+IO to XaZ...Input data, DOLIT+
oo~O1l"・Output data, CL S, ~S4...
- Shift amount instruction signal, C2, S, . . . selection signal. Fig. 1 is a principle block diagram of the barrel 778 circuit according to the present invention.

Claims (1)

[Claims] 1. Q bits in a certain range according to the shift amount from P bit input data (D_I_N); provided that Q<P, data (
m barrel shifters (1_1 to 1_m) each of which performs shift processing of input data based on the shift amount instruction signal (C1); and a selection signal (C2). a selection circuit (2) that distributes and inputs the P-bit input data to the m barrel shifters approximately every P/m bit based on the above, and extracts the Q-bit data from the m barrel shifters. A barrel shift circuit characterized by the following. 2, two barrel shifters (11, 12) are provided, and the selection circuit is configured with three multiplexers (13 to 15), thereby inputting 2N-1 bits of input data (I_
0 to I_6_2) are distributed and input to the two barrel shifters, and N-bit data (0_0 to 0_3_1) are selectively output based on the shift processing of the barrel shifters. barrel shift circuit. 3. Each of the barrel shifters (11, 12) is composed of a plurality of MOS transistors arranged in a matrix, and in each barrel shifter, each MOS transistor is connected to two adjacent ones of the three multiplexers.
Each signal line of multiple bits of data selectively output from multiplexers (13, 14; 14, 15) and N/2 bits of output data (0_0~0_1_5;0_1_6~
0_3_1), and each M
The gate of the OS transistor receives N/2 bit data (d_0 to d_
3. The barrel shift circuit according to claim 2, wherein the barrel shift circuit is connected to each of the signal lines 1_5).