JPH0469869A - Data separator - Google Patents

Abstract

PURPOSE:To improve the follow up ability for data by providing a mislock detecting circuit. CONSTITUTION:A mislock detecting circuit 1 is added which detects the mislock state by input data A and a frequency division signal B from a frequency dividing circuit 3, and the frequency dividing circuit 3 is controlled by an output C of this circuit 1. That is, the mislock detecting circuit 1 takes read data A and the output B from the frequency dividing circuit 3 as the input and detects the mislock state to output the set signal C synchronized with read data A to the frequency dividing circuit 3. When receiving this set signal C, the frequency dividing circuit 3 is so set that read data A is in the center of a window, thus correcting the window.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data separator in a magnetic disk drive, and particularly to a data separator for reading data from a magnetic disk drive.
The present invention relates to a data separator that generates playback data and window signals from code data.

[Conventional technology]

Traditionally, such data separators are face-locked
It is configured with a loop (PLL).

FIG. 6 is a block example of a data separator showing one such conventional example.

As shown in FIG. 6, the conventional data separator includes a phase comparator that compares input data and a frequency-divided signal, a low-pass filter (LPF) 4, an oscillation circuit 2, and a frequency division circuit 3A that creates a window signal. The 0 phase comparator 5, which has a 0 phase comparator 5, determines the phase difference between the -code data output from the disk drive and the output from the frequency dividing circuit 3A. The phase difference obtained by this phase comparator 5 is converted into DC by a low-pass filter 4 and then supplied to a frequency divider circuit 3A.
changes the output by changing the frequency division ratio to match the phase of the input signal. Note that the frequency division ratio is not changed when there is no phase difference.

FIG. 7 is a timing diagram when the data separator node in FIG. 6 is in a mislock state.

As shown in FIG. 7, when there is a regular bit shift α for 5YNC by ■· output from the disk drive as input data, P L, [.

This shows that the circuit is mislocked. Originally 5Y
When the transfer rate is 500 Kbps, the NC bit is output every 2 μs, but when the read head of the disk drive is asymmetrical or the amplifier inside the disk drive is misadjusted, the 1 bit output is output as shown in Figure 7. Data with a bit shift α is output every other time.

A disk drive to which such read data is output may fall into a mislock state at a data phase discontinuity point during writing. When this mislock occurs, the data separator cannot accurately generate playback data and window signals.

[Problems to be Solved by the Invention] ]-The conventional data separator mentioned above has a problem in that when there is a regular bit shift in the read data, C=, the (li'7 phase small continuation The drawback is that once a mislock occurs at a point, the window signal cannot follow up.

An object of the present invention is to provide a data separator that enables tracking of such a window signal.

[Means to solve the problem]

The data separator of the present invention is a data separator that has a built-in L1 circuit for separating read data output from a disk drive into playback data and a data window signal. a phase comparator that detects a phase difference between the read data from the disk drive and the window signal, and a plurality of holding circuits that sample playback data for each window signal and hold the sampling results. , a determination circuit that determines a misclock state based on a combination of outputs of a plurality of holding circuits, and when the determination circuit determines a misclock, the frequency dividing circuit is activated in synchronization with the next input read data. configured to set.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a data separator showing a first embodiment of the present invention.

As shown in FIG. 1, this embodiment adds a mislock detection circuit 1 that detects a mislock state from input data A and a frequency-divided signal B from a frequency divider circuit 3 to the conventional circuit described above. However, the output C is used to control the frequency division rgJ&'fi3. That is, the mislock detection circuit 1 detects the read data A and the output B from the frequency dividing circuit 3.
When a mislock state is detected, a set signal C synchronized by 5 degrees with the read data A is output to the frequency dividing circuit 3. When this set signal C is received, the frequency dividing circuit 3 moves the frequency dividing circuit 3 so that the read data A is at the center of the window.
and correct the window.

FIG. 2 is a diagram of the mislock detection circuit shown in FIG. 1.

As shown in FIG. 2, this mislock detection circuit includes a plurality of D-type flip-flop (D-F/F) circuits 6 and 7.
, a shift register 8 composed of a plurality of ll-F/Fs, and an output of the shift register 8 directly and an inverter 9.
．． A N I) gate 11 inputting through A
It is composed of an R8 type flip-flop 12 which is set by the output of an ND gate 11, and an AND gate 13.

FIG. 3 is a timing diagram of the mislock detection path shown in FIGS. 1 and 2. FIG.

As shown in FIG. 3, the timings of the input/output signals A, B, and C of the mislock detection circuit 1 and points a and b in FIG. 2 are shown here. A is read data, and B is a window signal created by dividing the frequency by two with a signal having twice the frequency of the window. Further, a is created by two D-F/F circuits 67 that sample read data for each window. The data sampled for each window is shifted by the shift register 8 for each window. As a result, a mislock is determined by the inverter 9.10 and the AND gate 11 based on the output of the shift register 8. In this embodiment, since the case where there is a regular bit shift is determined, when a mislock is determined, the mislock detection circuit Bl then sends a set signal in synchronization with the red data A that enters the data separator circuit. Output C. Therefore, when the set signal C is received, the frequency divider circuit 3 sets the frequency divider circuit 3 so that the read data A is at the center, so the mislock state is avoided by making the read data A the center of the window. can do.

In short, according to this embodiment, by providing a mislock state detection mechanism and setting the frequency dividing circuit 3 of the PLL circuit inside the data separator in synchronization with the read data, the read data is brought to the center of the window. Since there is a point of discontinuity in the phase of the data, it is possible to follow the window signal.

FIG. 4 is a mislock detection circuit diagram for explaining a second embodiment of the present invention, and FIG. 5 is a timing diagram of the mislock detection circuit shown in FIG. 4.

As shown in FIGS. 4 and 5, this embodiment is an example in which a mislock state is detected for a disk subjected to MFM modulation. In this MFM method, since data bits and clock bits do not appear in adjacent window signals, this property is utilized to detect mislock.

First, the two flip-flop circuits 6 and 7 sample read data for each window, and the shift register 14 connected to the output a of the flip-flop 6 shifts the data for each window. This shift register 1
The AND gate 15 which receives the outputs of 4 and 4 as inputs determines the mislock condition. Hereinafter, the flip-flop 12 and the AND gate 13 perform the same operation as in the first embodiment, and these are the input waveforms A and B and the output waveform C5 shown in FIG.
This is clear from the timing of internal waveforms a to d.

〔Effect of the invention〕

As explained above, the data separator of the present invention can avoid a mislock state by providing a mislock detection circuit, so it can improve data followability and eliminate discontinuous points in the data phase. The effect is that the window signal can follow even if there is a problem.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data separator showing the first embodiment of the present invention, FIG. 2 is a mislock detection circuit diagram shown in FIG. 1, and FIG. 3 is a mislock detection circuit diagram shown in FIGS. 1 and 2. 4 is a timing diagram of the detection circuit. FIG. 4 is a mislock detection circuit diagram for explaining the second embodiment of the present invention. FIG.
6 is a block diagram of a data separator showing a conventional example, and 7 is a timing diagram of the mislock detection circuit shown in the figure.
This figure is a timing diagram when the data separator in FIG. 6 is in a mislocked state. 1... Mislock detection circuit, 2... Oscillation circuit, 3.
・Frequency dividing circuit, 4...Low pass filter (LPF), 5
... Phase comparator, 6.7 ... D-type flip-flop (D-F/F), 8.14 ... Shift register, 9
．． 10...Inverter, 11,13.15...AN
D gate, 12...R3 type flip-prop (R8-
F/F).

Claims (1)

[Claims] PL for separating read data output from the disk drive into playback data and data window signals
A data separator incorporating an L circuit includes a frequency dividing circuit that divides a reference clock to generate a window signal, a phase comparator that detects a phase difference between the read data from the disk drive and the window signal, and the window signal. a plurality of holding circuits that sample reproduced data at each time and hold the sampled results; and a judgment circuit that judges a misclock state based on a combination of outputs of the plurality of holding circuits, and the judgment circuit detects a misclock state. A data separator characterized in that, upon determination, the frequency dividing circuit is set in synchronization with the next input read data.