JPH0469747A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To lower the generation probability of a restart processing caused by a comparison fault or a majority fault by requesting the reissue of an instruction, in the case of an error, etc., are detected by at least one piece of cache, and also, informing all caches of the generation of a fault and making cache data of the corresponding address invalid. CONSTITUTION:When a cache 21 generates a cache fault by a read-out operation, the cache 21 sets a cache error signal 111 to '1'. Subsequently, an OR circuit 40 generates a bus error signal 113, and distributes its signal to processors 10-12 and caches 20-22, respectively. When a bus error signal 113 is informed, the processors 10-12 suspend receiving the data sent through signal lines 130-132, and also, request a re-read-out operation of an instruction or data issued immediately before an input of the bus error signal 113 to the respective caches 20-22 through the signal lines 130-132. In such a way, the generation probability of a restart processing operation caused by a comparison or majority fault becomes low.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an arithmetic processing device having a circuit for comparing the processing results of a plurality of arithmetic processing units or for confirming majority decision, and in particular, it relates to an arithmetic processing device having a circuit for comparing processing results of a plurality of arithmetic processing units or for confirming a majority decision, and in particular, it relates to an arithmetic processing device having a circuit for comparing the processing results of a plurality of arithmetic processing units or for confirming a majority decision, and in particular for an arithmetic processing device having a circuit for comparing the processing results of a plurality of arithmetic processing units or for confirming a majority decision. The present invention relates to an arithmetic processing device having the present invention.

[Conventional technology]

Conventionally, this type of arithmetic processing device has a plurality of arithmetic units each including one microprocessor and one cache;
It has a majority circuit that compares the processing results of the respective arithmetic units with each other or confirms the majority decision. Each of the arithmetic units operates independently, and even if a cache failure occurs in one set of arithmetic units, that arithmetic unit bypasses the cache and accesses the main storage device for reading. Then, the operation of the calculation unit where the cache failure occurred is not synchronized with other calculation units,
A comparison or majority circuit detects whether there is a discrepancy in the processing results,
Cache failures were treated as comparison failures or majority failures.

This arithmetic processing device immediately resets all arithmetic units when a comparison failure occurs, and then performs restart processing. Furthermore, in the event of a majority vote failure, the internal information of the normal processor is saved to the main memory when processing is idle, and all arithmetic units (processor and cache) are reset. Then, after setting the saved internal information of the normal processor in each calculation unit, processing was restarted.

[Problem to be solved by the invention]

In the conventional arithmetic processing device described above, when a cache failure occurs, it is treated as a comparison or majority failure. As a result, the probability of occurrence of the restart processing operation is high, and the execution time of the restart processing cannot be ignored, which has the drawback of greatly affecting the effective operation of a system using this arithmetic processing device.

[Means to solve the problem]

The arithmetic processing device of the present invention has a plurality of arithmetic units each including one microprocessor and one cache, and a circuit that mutually compares the processing results of the arithmetic units or performs majority decision confirmation. In the processing device, means for transmitting a cache error signal when a read failure is detected; path error signal generating means connected to the plurality of caches and generating the bus error signal which is the logical sum of the cache error signals; and a microprocessor including means for requesting the cache to re-execute the access instruction.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows 1 of the present invention. FIG. 2 is a block diagram of an embodiment. Arithmetic processing device 1 is connected to main storage device 2 via bus 100 . The arithmetic processing unit 1 includes three processors 10.1
1 and 12, three caches 20, 2] and 22, and a majority circuit 3o. Processor 10 and cache 20, processor 11 and cache 21. Processor 12 and cache 22 each have a signal line 130
．． 131 or ] 32, and constitute three sets of arithmetic units. Cache 201 cache 21 and cache 22 are connected to signal line 1.20.1.21 or 1, respectively.
22 to the majority circuit 30. The OR circuit 40 included in the arithmetic processing device 1 has a cache 20 . Cache error signals 110, 111, or 112 output from the cache 21 and the cache 22 are inputted from respective connected signal lines. Furthermore, the bus error signal 113, which is the logical sum of the cache error signals 1.10, 111, and 112, is applied to the processors 10.11 and 12. It is distributed to caches 20, 21 and 22 by signal lines connected to each cache.

Next, the operation of the present invention will be explained in detail. Processor 1.
O,1,1 and 12 operate synchronously. Then, the command or data read command is transmitted to the signal lines 1.30, 1.
When issuing simultaneously to caches 20.21 and 22, which are connected via 31 or 132, respectively, caches 20.21 and 22 each consult the cache directory. If the data of the corresponding address is in the cache, the cache is read and the signal lines 130 and 13 are read.
1 or 132 to processors 10.11 and 12.

In such an operation, if a cache failure occurs in the cache 21 during a read operation, for example, the cache 21
sets the cache error signal 111 to '1'. The OR circuit 40 then generates a bus error signal 113 and sends the signal to the processors 10, 11 and 12 and the cache 20.
．． 21 and 22, respectively.

Processors 10.11 and 12 output bus error signal 11
When 83 is notified, signal line 1.30, 131 or 13
2. Stop receiving data sent via 2, and
A request is made to each of the caches 20.21 and 22 via the signal line 130.1.31 or ]32 to reread the instruction or data issued immediately before the input of the bus error signal 113.

On the other hand, when the caches 20, 21 and 22 are notified of the bus error signal 113, the cache data valid bits of the cache directories ``2'' corresponding to the address of the read operation issued immediately before the input of the notification are respectively programmed.
". At this time, processors 1.0, 1.
When an instruction or data read operation request comes from the caches 20, 21 and 22 again from the caches 20, 21 and 22, the valid bit of the cache register 1 and 2 at the corresponding address is reset to ``0''. Therefore, a cache miss occurs.Then, the caches 20, 21 and 22 transmit the read command to the signal lines 120, 121 or 1.
22 to the majority circuit 30. Majority circuit 30
performs a triple majority decision operation on the contents of the read commands sent from the caches 20, 21 and 22,
Check that the processing unit is operating normally.

Then, the majority circuit 30 sends the main memory read command to bus 1.
00 to the main storage device 2. The main storage device 2 is
Reads the data at main memory address "2" corresponding to the main memory read command sent. The majority circuit 3o is connected via the bus 100 to the caches 20, 21 and 22.
The read data is sent to the processors 10, 11 and ]2, respectively. Simultaneously cache 20.21
and 22 stores the data read from the main storage device 2 in the corresponding cache area, and sets address information and cache data valid pins 1 to "1" on the corresponding cache directory.

In this embodiment, in order to simplify the explanation, an arithmetic processing device using a triple majority voting method using three processors has been described, but the present invention is not limited to this, and may also be applied to a comparator circuit method using two processors. It goes without saying that this invention can be realized in the same way.

〔Effect of the invention〕

As explained above, the present invention is applicable to an operation in which simultaneous reading of multiple caches is performed in an arithmetic processing device that includes a plurality of arithmetic units each consisting of a processor and a cache and performs a synchronous comparison or majority decision operation. Furthermore, when an error or the like occurs in at least ] caches, it is possible to prevent the arithmetic units from becoming out of synchronization. In other words, if an error or the like is detected in at least one cache, that cache notifies all processors that a failure has been detected and requests reissue of instructions, and also indicates that the failure has occurred in all caches. notification and invalidate the cache data for the corresponding address. As a result, it becomes possible to synchronize the operations of multiple computing subcommittees, reducing the probability of restart processing due to comparison failure or majority vote failure, and allowing effective operation of the system using this computing device. .

FIG. 1 is a block diagram of one embodiment according to the present invention.

1... Arithmetic processing unit, 2... Main storage device, 10-1
2... Processor, 20-22... Cache, 3
0...Majority circuit, 40...OR circuit, 100...
・Bus, 110-112...cache error signal,
]13... Bus error signal, 1.20 to 1.22, 1
．． 30-132...Signal line.

Claims (1)

[Claims] Detecting a read failure in an arithmetic processing device having a plurality of arithmetic units each including one microprocessor and one cache, and a circuit that mutually compares processing results of the arithmetic units or performs majority decision confirmation. Then, a cache including means for sending a cache error signal and means for invalidating a cache data valid bit on a cache directory processed by a memory access instruction immediately before the input of the bus error signal by inputting the bus error signal; bus error signal generating means connected to the plurality of caches and generating the bus error signal that is a logical sum of the cache error signals; and requesting the cache to re-execute the memory access instruction upon input of the bus error signal. and a microprocessor including means.