JPH0469458B2 - - Google Patents
Info
- Publication number
- JPH0469458B2 JPH0469458B2 JP59219231A JP21923184A JPH0469458B2 JP H0469458 B2 JPH0469458 B2 JP H0469458B2 JP 59219231 A JP59219231 A JP 59219231A JP 21923184 A JP21923184 A JP 21923184A JP H0469458 B2 JPH0469458 B2 JP H0469458B2
- Authority
- JP
- Japan
- Prior art keywords
- microprocessor
- series
- bits
- parallel
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000001514 detection method Methods 0.000 claims description 6
- 230000001360 synchronised effect Effects 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 abstract description 11
- 238000010586 diagram Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/02—Power saving arrangements
- H04W52/0209—Power saving arrangements in terminal devices
- H04W52/0225—Power saving arrangements in terminal devices using monitoring of external events, e.g. the presence of a signal
- H04W52/0229—Power saving arrangements in terminal devices using monitoring of external events, e.g. the presence of a signal where the received signal is a wanted signal
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Power Sources (AREA)
- Mobile Radio Communication Systems (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、移動無線通信の移動端末装置に利用
される。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is utilized in a mobile terminal device for mobile radio communication.
本発明は、電池電源により動作する移動端末装
置が、受信される無線信号に同期して、自局宛の
通信が存在する可能性のある時間に限り受信回路
およびその他必要な回路に電源電流を供給して、
その電池の消耗を小さくするバツテリーセービン
グ受信装置に関する。 The present invention enables a mobile terminal device operating on battery power to synchronize with a received radio signal and supply power current to a receiving circuit and other necessary circuits only during times when there is a possibility that there is communication addressed to the mobile terminal device. supply,
The present invention relates to a battery saving receiving device that reduces battery consumption.
移動端末装置に対するバツテリーセービング方
式は、従来からさまざまな方式が知られていて、
受信回路の電源電流の経済化は相当程度に達して
いる。近年、移動端末装置には受信されるデータ
信号を識別処理するために、マイクロプロセツサ
が搭載されるが、受信回路の電源電流が経済化さ
れるにしたがつて、このマイクロプロセツサの消
費電流が相対的に大きくなつてきた。
Various battery saving methods have been known for mobile terminal devices.
The economicalization of the power supply current of the receiving circuit has reached a considerable degree. In recent years, mobile terminal devices are equipped with microprocessors to identify and process received data signals, but as the power supply current of receiving circuits becomes more economical, the current consumption of this microprocessor has decreased. has become relatively large.
このマイクロプロセツサは、かりに受信回路と
連動して間欠的に動作しても、無線信号の直列デ
ータの受信にしたがつて、データと取り込みおよ
び記憶などの処理を行うのでは、無線信号が受信
されている期間にわたり、連続的に電源電流を消
費することになる。 Even if this microprocessor operates intermittently in conjunction with the receiving circuit, it will not be able to perform processing such as capturing and storing the serial data of the wireless signal as it receives the serial data. This means that the power supply current will be consumed continuously over the period of time.
本発明はこのようなバツテリーセービング受信
装置の電源電流をさらに経済化することを目的と
する。
It is an object of the present invention to further economize the power supply current of such a battery saving receiving device.
本発明は、受信回路と、この受信回路の出力信
号から同期信号を検出する同期信号検出回路と、
この同期信号に応じて自局宛の通信信号が存在す
る可能性のある時間に限り上記受信回路の電源電
流を供給する制御回路と、上記受信回路の出力信
号を入力して処理識別を行うマイクロプロセツサ
とを備えたバツテリーセービング受信装置におい
て、上記受信回路の出力信号を並列信号に変換す
る直並列変換回路を備え、上記マイクロプロセツ
サは上記制御回路の動作に同期してこの直並列変
換回路の出力に間欠的にアクセスする制御手段を
含むことを特徴とする。
The present invention includes a receiving circuit, a synchronous signal detection circuit that detects a synchronous signal from an output signal of the receiving circuit,
In response to this synchronization signal, there is a control circuit that supplies power supply current to the receiving circuit only during times when there is a possibility that a communication signal addressed to the local station exists, and a microcontroller that inputs the output signal of the receiving circuit and performs processing identification. The battery saving receiving device includes a serial-to-parallel conversion circuit that converts the output signal of the reception circuit into a parallel signal, and the microprocessor converts the serial-to-parallel conversion circuit in synchronization with the operation of the control circuit. The apparatus is characterized in that it includes a control means for intermittently accessing the output of the apparatus.
マイクロプロセツサは、無線信号により直列的
に到来するデータに直列的にアクセスすることを
やめ、直列的に到来するデータを直並列変換回路
により所定のビツト数毎に並列信号に変換し、マ
イクロプロセツサは、この直並列変換回路の出力
並列信号に間欠的にアクセスすることにより、そ
の動作時間を数分の１に短縮することができる。
Microprocessors stop serially accessing data that arrives serially via wireless signals, and convert the serially arriving data into parallel signals for each predetermined number of bits using a serial/parallel conversion circuit. By intermittently accessing the output parallel signal of the serial-to-parallel conversion circuit, the setter can reduce its operating time to a fraction of a fraction.
第１図は本発明実施例装置のブロツク構成図で
ある。受信回路５の出力は、制御部４および直並
列変換部２ならびに同期パターン検出部３に入力
する。上記直並列変換部２の出力は、マイクロプ
ロセツサ１に入力する。上記同期パターン検出部
３の出力は、直並列変換部２と制御部４とに入力
する。制御部４の出力は動作要求線ｂを介してマ
イクロプロセツサ１に入力し、このマイクロプロ
セツサ１の出力はスタンバイ要求線ｄを介して制
御部４に入力する。
FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention. The output of the receiving circuit 5 is input to the control section 4, the serial/parallel conversion section 2, and the synchronization pattern detection section 3. The output of the serial/parallel converter 2 is input to the microprocessor 1. The output of the synchronization pattern detection section 3 is input to the serial/parallel conversion section 2 and the control section 4. The output of the control section 4 is input to the microprocessor 1 via the operation request line b, and the output of this microprocessor 1 is input to the control section 4 via the standby request line d.
通常マイクロプロセツサ１は待機状態つまり低
消費電力状態にある。シリアルデータは同期パタ
ーン制御部３に入力され、同期パターンを検出す
ると同期通報ラインａを通し直並列変換部２と制
御部４に通報される。直並列変換部２は直ちにシ
リアルデータの格納を開始し所定ビツト（この例
では８ビツト）格納する。制御部４は特定ビツト
格納したことをビツトカウントし、カウントアウ
トしたら動作要求線ｂを通しマイクロプロセツサ
１の待機状態を解き動作状態にする。マイクロプ
ロセツサ１は直並列変換部２のデータをデータ線
ｃを介して取り出し、内部RAM１ａに格納す
る。このとき消費電力は大となつている。マイク
ロプロセツサ１は所定ビツトをRAM１ａに格納
終了すると、スタンバイ要求線ｄを通じ制御部４
にスタンバイを要求し待機状態に入る。このとき
は低消費電力状態となる。これをＮ回繰り返す。
制御部４で信号受信終了を検出したらマイクロプ
ロセツサ１は信号の復号を行う。これを第２図の
消費電流遷移図に示す。受信信号のSTはスター
トフラグ、DATAは直列データ信号を示す。デ
ータ信号は８ビツト毎に直並列変換回路から並列
的にそれぞれ短時間で取り込まれる。このよう
に、所定ビツト毎にマイクロプロセツサの動作を
開始および停止させることによつて常時通電した
ままの状態に比べて、マイクロプロセツサについ
て大幅なパワーセービングが可能となる。 Normally, the microprocessor 1 is in a standby state, that is, a low power consumption state. The serial data is input to the synchronization pattern control section 3, and when a synchronization pattern is detected, it is notified to the serial/parallel conversion section 2 and the control section 4 through the synchronization notification line a. The serial/parallel converter 2 immediately starts storing serial data and stores predetermined bits (8 bits in this example). The control section 4 counts bits when a specific bit has been stored, and when the count is out, the microprocessor 1 is released from the standby state through the operation request line b and placed in the operating state. The microprocessor 1 takes out the data from the serial/parallel converter 2 via the data line c and stores it in the internal RAM 1a. At this time, power consumption becomes large. When the microprocessor 1 finishes storing the predetermined bits in the RAM 1a, it sends a request to the control unit 4 through the standby request line d.
requests standby and enters the standby state. At this time, it becomes a low power consumption state. Repeat this N times.
When the control section 4 detects the end of signal reception, the microprocessor 1 decodes the signal. This is shown in the current consumption transition diagram in FIG. ST of the received signal indicates a start flag, and DATA indicates a serial data signal. The data signal is taken in parallel from the serial/parallel converter circuit every 8 bits in a short time. In this way, by starting and stopping the operation of the microprocessor for each predetermined bit, it is possible to significantly save the power of the microprocessor compared to a state where the power is always on.
以上説明したように、本発明によれば、マイク
ロプロセツサは並列所定ビツト毎に動作開始およ
び停止をすることになり、動作停止の状態が長く
なつて、顕著なパワーセービングを行うことがで
きる効果がある。
As explained above, according to the present invention, the microprocessor starts and stops its operation every predetermined bit in parallel, and the state in which the operation is stopped becomes longer, resulting in significant power saving. There is.
第１図は本発明の実施例装置のブロツク構成
図。第２図は本発明による消費電流遷移図。
１……マイクロプロセツサ、１ａ……内部
RAM、２……直並列変換部、３……同期パター
ン検出部、４……制御部、５……受信回路、ａ…
…同期通報ライン、ｂ……動作要求線、ｃ……デ
ータ線、ｄ……スタンバイ要求線、Ｅ……直流電
源。
FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention. FIG. 2 is a consumption current transition diagram according to the present invention. 1... Microprocessor, 1a... Internal
RAM, 2...Serial-to-parallel conversion unit, 3...Synchronization pattern detection unit, 4...Control unit, 5...Receiving circuit, a...
...Synchronization report line, b...Operation request line, c...Data line, d...Standby request line, E...DC power supply.
Claims (1)
る同期信号検出回路と、 この同期信号に応じて自局宛の通信信号が存在
する可能性のある時間に限り上記受信回路の電源
電流を供給する制御回路と、 上記受信回路の出力信号を入力して処理識別を
行うマイクロプロセツサと を備えたバツテリーセービング受信装置におい
て、 上記受信回路の出力信号を並列信号に変換する
直並列変換回路を備え、 上記マイクロプロセツサは上記制御回路の動作
に同期してこの直並列変換回路の出力に間欠的に
アクセスする制御手段を含む ことを特徴とするバツテリーセービング受信装
置。[Claims] 1. A receiving circuit, a synchronous signal detection circuit that detects a synchronous signal from an output signal of this receiving circuit, and a synchronous signal detection circuit that detects a synchronous signal from an output signal of this receiving circuit, In a battery saving receiving device comprising a control circuit that supplies a power supply current to the receiving circuit, and a microprocessor that inputs the output signal of the receiving circuit and performs processing identification, the output signal of the receiving circuit is converted into a parallel signal. A battery-saving receiver comprising a serial-to-parallel converter circuit for converting the serial-to-parallel converter to .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59219231A JPS6198030A (en) | 1984-10-18 | 1984-10-18 | Battery-saving receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59219231A JPS6198030A (en) | 1984-10-18 | 1984-10-18 | Battery-saving receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6198030A JPS6198030A (en) | 1986-05-16 |
| JPH0469458B2 true JPH0469458B2 (en) | 1992-11-06 |
Family
ID=16732254
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59219231A Granted JPS6198030A (en) | 1984-10-18 | 1984-10-18 | Battery-saving receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6198030A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR910008738B1 (en) * | 1987-02-20 | 1991-10-19 | 닛본 덴기 가부시기가이샤 | Portable radio apparatus having battery saved channel scanning function |
| FR2770925B1 (en) * | 1997-11-12 | 2000-01-07 | Sagem | METHOD FOR TRANSMITTING REMOTE CONTROLS |
-
1984
- 1984-10-18 JP JP59219231A patent/JPS6198030A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6198030A (en) | 1986-05-16 |
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