JPH0469373U - - Google Patents
Info
- Publication number
- JPH0469373U JPH0469373U JP11381590U JP11381590U JPH0469373U JP H0469373 U JPH0469373 U JP H0469373U JP 11381590 U JP11381590 U JP 11381590U JP 11381590 U JP11381590 U JP 11381590U JP H0469373 U JPH0469373 U JP H0469373U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- electromagnetic relay
- signal
- gate element
- pulse signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 2
- 238000000746 purification Methods 0.000 claims 4
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000012544 monitoring process Methods 0.000 description 1
Description
第１図はこの考案によるアンチロツク制御装置
の全体概略ブロツク図、第２図は従来のアンチロ
ツク制御装置の全体概略ブロツク図、第３図は接
点浄化作用の作動タイミングを説明する図である
。
１……電源制御電磁リレー、２……接点、３…
…コイル、４……負荷群、４１，４２……４ｎ…
…ソレノイドバルブ、１０……電子制御装置、１
１……アンチロツク制御回路、１２，１３１……
１３ｎ……半導体スイツチ、１４……電源回路、
１５……電源印加監視回路、１６，１８……パル
ス発生回路、１７……遅延回路、２０……ブレー
キスイツチ、２１……Ｆ／Ｖ変換器、２２……比
較器、２３……ＯＲゲート素子、２４……ＡＮＤ
ゲート素子。
FIG. 1 is an overall schematic block diagram of an anti-lock control device according to this invention, FIG. 2 is an overall schematic block diagram of a conventional anti-lock control device, and FIG. 3 is a diagram illustrating the operation timing of a contact cleaning action. 1...Power control electromagnetic relay, 2...Contact, 3...
... Coil, 4 ... Load group, 4 1 , 4 2 ... 4 n ...
... Solenoid valve, 10 ... Electronic control device, 1
1... Anti-lock control circuit, 12, 13 1 ...
13 n ...semiconductor switch, 14... power supply circuit,
15... Power supply monitoring circuit, 16, 18... Pulse generation circuit, 17... Delay circuit, 20... Brake switch, 21... F/V converter, 22... Comparator, 23... OR gate element , 24...AND
gate element.
Claims (1)
部で種々の演算をし、加圧、減圧等の制御信号を
出力するアンチロツク制御回路と、その出力信号
により半導体スイツチを介して駆動される負荷の
複数組を並列に設けた負荷回路と、前記負荷回路
の共通端を電源に接続する経路途中に設けられた
電源制御電磁リレーと、この電磁リレーを開閉す
るための電源回路を含む電磁リレー駆動回路と、
電源回路からの出力信号を遅延させてパルス信号
を発生させそのパルス信号をゲート素子を介して
上記半導体スイツチの少なくとも１つに入力させ
て負荷を短時間だけ通電させる電磁リレー接点浄
化回路とを備え、さらに前記電磁リレー接点浄化
回路に対してブレーキ信号又は前記車輪速センサ
の速度信号を基準値と比較した所定以上の速度信
号のいずれかが入力されると前記接点浄化回路の
浄化作用を禁止する信号を前記ゲート素子へパル
ス信号が入力される途中に設けたもう１つのゲー
ト素子を介して入力するようにした接点浄化禁止
回路を設けたことを特徴とするアンチロツク制御
装置。 An anti-lock control circuit that performs various calculations internally based on input signals from wheel speed sensors and outputs control signals such as pressurization and depressurization, and multiple loads that are driven by the output signals via semiconductor switches. a power control electromagnetic relay provided in the middle of a path connecting a common end of the load circuit to a power source; and an electromagnetic relay drive circuit including a power supply circuit for opening and closing the electromagnetic relay. ,
and an electromagnetic relay contact purification circuit that delays an output signal from the power supply circuit to generate a pulse signal, inputs the pulse signal to at least one of the semiconductor switches via a gate element, and energizes the load for a short time. Further, when either a brake signal or a speed signal equal to or higher than a predetermined value obtained by comparing the speed signal of the wheel speed sensor with a reference value is input to the electromagnetic relay contact purification circuit, the purification action of the contact purification circuit is prohibited. An anti-lock control device comprising a contact cleaning prohibition circuit which inputs a signal through another gate element provided in the middle of inputting a pulse signal to the gate element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11381590U JPH0469373U (en) | 1990-10-29 | 1990-10-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11381590U JPH0469373U (en) | 1990-10-29 | 1990-10-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0469373U true JPH0469373U (en) | 1992-06-19 |
Family
ID=31861431
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11381590U Pending JPH0469373U (en) | 1990-10-29 | 1990-10-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0469373U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007053087A (en) * | 2005-08-17 | 2007-03-01 | Tyco Electronics Corp | Circuit for surface activation relay contact, and surface activation method of relay contact |
-
1990
- 1990-10-29 JP JP11381590U patent/JPH0469373U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007053087A (en) * | 2005-08-17 | 2007-03-01 | Tyco Electronics Corp | Circuit for surface activation relay contact, and surface activation method of relay contact |
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