JPH0467646A - Evaluation of crystal of semiconductor material - Google Patents

Abstract

PURPOSE:To make it possible to inspect the state of the crystal in the depth direction of a semiconductor material before the delivery of products and to eliminate defectives by a method wherein a change in the state of the crystal in the depth direction of the semiconductor material is evaluated on the basis of a change in a leakage current due to carriers, which are generated in a depletion layer while the depletion layer is made to expand in the semiconductor material. CONSTITUTION:A single crystal silicon wafer 1 is earthed under a low temperature of 10 deg.C, a positive voltage is applied to an N<+> impurity region 2 and a depletion layer is generated. The voltage and a current at this time are respectively measured by a voltmeter 3 and an ammeter 4. Then, a bias voltage being applied between the wafer 1 and the region 2 is modified by the operation of a variable resistor 5 and the voltage and the current are again measured. When a change in the value of the current to the bias voltages is measured in such a way, the state of the crystal of a semiconductor material can be estimated in the depth direction of the material. Moreover, the region 2 can be formed even at any arbitrary position in a sampling inspection of the wafer 1, but has only to be formed selecting a part, which has no trouble for the formation of an integrated circuit, of the wafer 1 in a non-destructive inspection of a product.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for evaluating crystals in semiconductor materials, and particularly relates to a method for evaluating crystals continuously from the surface of a semiconductor material in the depth direction. do.

[Prior Art] Conventionally, semiconductor materials cut into wafers (hereinafter referred to as semiconductor wafers) are subjected to a crystal evaluation test before being shipped, and semiconductor wafers containing crystal defects above a certain level are rejected. It is considered to be a good product.

Such a crystal evaluation test method is known, for example, as a photoelectric attenuation method, and a conventional crystal evaluation method using this photoelectric attenuation method will first be briefly explained.

In the photoelectric attenuation method, light of a predetermined wavelength is irradiated onto the surface of a semiconductor wafer, and carriers are generated within the semiconductor wafer by the irradiation. Since this carrier decays over time, the measurement terminal is brought into contact with the surface of the semiconductor wafer, and the carrier recombination lifetime is estimated from its decay characteristics. Since the quality of the crystal of the semiconductor wafer affects the recombination lifetime, the quality of the crystal of the semiconductor wafer is determined from the recombination lifetime estimated by the above method.

[Problems to be solved by the invention] In the crystal evaluation method using the photoelectric attenuation method described above, the carrier attenuation characteristics are the average characteristics of the entire semiconductor wafer, so the average crystal properties of the semiconductor wafer cannot be evaluated. However, the depth distribution of crystal properties from the surface cannot be evaluated.

Semiconductor wafers provide substrates for semiconductor devices, especially integrated circuits, and if the components of integrated circuits are formed near the surface of the semiconductor wafer, which is uniform in the depth direction, the conventional crystal evaluation method described above cannot be used. It can be said that it is sufficient. However, in intrinsic (IG) wafers and epitaxial wafers, which have been attracting attention in recent years, there is a possibility that the crystal properties change significantly in the depth direction, and the depth distribution of the crystal properties of semiconductor wafers cannot be changed. There was a need for a method that could be evaluated by destruction.

[Means for Solving the Problems] The present invention was made to solve the problems of the conventional crystal evaluation method described above. This method evaluates changes in the crystal state in the depth direction of semiconductor materials based on changes in leakage current caused by carriers.

Therefore, the gist of the present invention is to form a p-n junction or a Schottky junction in a semiconductor material, a step of applying a voltage to the p-n junction or a Schottky junction to form a depletion layer of a predetermined width, a step of measuring a leakage current flowing across the p-n junction or the Schottky junction;
- changing the voltage applied to the n-junction or Schottky junction to change the width of the depletion layer in the depth direction of the semiconductor material, and measuring the leakage current flowing beyond the p-n junction or Schottky junction, a step of estimating a change in the lifetime of generated carriers based on a change in a measured value of leakage current;
This method includes the step of evaluating the crystalline state of the semiconductor material in the depth direction based on the change in the generation lifetime.

[Operations and Effects of the Invention] The leakage current measured under a predetermined temperature condition is almost entirely occupied by carriers generated within the depletion layer, and the current J due to the generated carriers is determined by the carrier generation rate U and the bias voltage. When the width of the depletion layer when V is applied is W, and the amount of charge of carriers is q, it is expressed by Equation 1.

J=qj:Udw (Equation 1) Here, when the bias voltage is changed by dV, the current due to the generated carriers after the change increases by dJ, and the total current is expressed by Equation 2.

J+dJ=qJ:dIIUdw (Formula 2) Formula 2
From this, the amount of change in current dJ is dJ = qUdw = qU (dw/dv) dV (formula 3), and the carrier generation rate U is U = (1/q) (d J/dV)/ (dw/dv)
(Formula 4) On the other hand, the carrier generation rate U is the intrinsic carrier concentration n11
If the lifetime of the carrier is τθ, then the formula 5% formula % U = n i / (271! (w) ) (Formula 5) When formula 4 is substituted into formula 5 and solved for the lifetime γe (w), formula 6 is obtained. can get.

r[l(w)= (qn i/2)(dw/dv)/(
dj/dv) (Equation 6) The depletion layer width W when applying the bias voltage V is expressed by Equation 7 using depletion layer approximation.

w= ((2E9ε9 (vb+10V))/qNb)
2 (Equation 7) In Equation 7, ε3 and ε8 represent the relative permittivity and vacuum permittivity, respectively, V b i represents the internal potential, and N
b is the impurity concentration of the semiconductor material.

Differentiating Equation 7 with dv, dw/dv= (εsεe/2qNb (vbt+v)) ”2 (Equation 8
) Substituting Equation 8 into Equation 6, the lifetime τe(w) is τll(w) = (qn i/2) (tsεa/2
qNb (vb: 10v))”2/ (dj/dv) (Equation 9
) As is clear from Equation 9, by measuring the change in the generated current (dj/dw) with respect to the applied bias voltage, it is possible to know the distribution τB (W) of the generated lifetime due to the change in the depletion layer width.

In general, crystal defects in semiconductor materials promote recombination of carriers and shorten the generation lifetime. It is possible to estimate the crystal state in the horizontal direction. Since the change in the generated current with respect to the applied bias voltage can be measured nondestructively, the crystalline state of the semiconductor material in the depth direction can be inspected before shipping, and defective products can be eliminated.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1 and 2 are cross-sectional views showing steps according to an embodiment of the present invention, and 1 is a p-type single crystal silicon wafer.

An n-shaded region 2 with a high impurity concentration is formed near the surface of the single-crystal silicon wafer 1, and this n-shaded region 2 is formed, for example, by diffusing phosphorus or by implanting ions.

Next, the single crystal silicon wafer 1 is grounded at a low temperature of 10 degrees Celsius, and a positive voltage is applied to the n-type impurity region 2 to generate a depletion layer. The voltage and current at this time are measured using a voltmeter 3 and an ammeter 4, respectively.

Next, the bias voltage applied between single crystal silicon wafer 1 and n-type impurity region 2 is changed by operating variable resistor 5, and the voltage and current are measured again. By measuring the change in the current value with respect to the bias voltage in this way, the distribution of generation lifetime can be determined from the above equation 9, and the crystal state can be estimated in the depth direction.

Note that the n-type impurity region 2 can be formed at any arbitrary position for sampling inspection of single-crystal silicon wafers, but for non-destructive inspection of products, it may be formed in a selected area that is not inconvenient for the formation of integrated circuits. .

3 and 4 are cross-sectional views showing an evaluation method according to another embodiment of the present invention, and 11 is a wafer of a compound semiconductor, for example, gallium arsenide. An electrode 12 of metal, for example a gold-nickel alloy, is formed on the main surface of the wafer 11, and this electrode 12 can be formed, for example, by selective growth or vapor deposition.

In this way, the compound semiconductor wafer 11 and the metal electrode 12
When the wafer 11 is brought into contact with the compound semiconductor wafer 11, a Schottky barrier is generated at the interface thereof, and a depletion layer is extended from the Schottky barrier into the compound semiconductor wafer 11 by the bias voltage.Then, the wafer 11 is grounded at a temperature of 20 degrees Celsius, and the electrode 12 A positive voltage is applied to generate a depletion layer. The voltage and current at this time are measured using a voltmeter 13 and an ammeter 14, respectively.

Next, the bias voltage applied between the wafer 11 and the electrode 12 is changed by operating the variable resistor 15, and again,
Measure voltage and current. In this way, by measuring the change in current value with respect to the bias voltage, it is possible to know the distribution of the generation lifetime in the same way as in the case of p-n junctions.
The crystal state can be estimated in the depth direction.

Note that the metal electrode 12 can be formed at any arbitrary position for sampling inspection of a wafer, but for non-destructive inspection of a product, it may be formed at a selected location that is not inconvenient for forming an integrated circuit.

[Brief explanation of drawings]

1 and 2 are cross-sectional views showing steps of an evaluation method according to one embodiment of the present invention, and FIG. 3 and FIG. 4 are cross-sectional views showing steps of an evaluation method according to another embodiment of the present invention. It is. 1. , , , , Single crystal silicon wafer , 2 , , , , ,
Il type impurity region, 3.13. ,,,voltmeter, 4.14. ,,,Ammeter, 5.15. ,,,Variable resistor, 11,,, Compound semiconductor wafer, 12,,,
,,metal electrode. Patent Applicant Mitsubishi Metals Co., Ltd. Agent Patent Attorney Kiyoshi Kuwai - (1 other person) Cross-sectional diagram showing the process of the second embodiment

Claims (2)

[Claims] (1) A step of forming a p-n junction or a Schottky junction in a semiconductor material; a step of applying a voltage to the p-n junction or Schottky junction to form a depletion layer of a predetermined width; a step of measuring the leakage current flowing across the Schottky junction; a step of changing the voltage applied to the p-n junction or the Schottky junction to change the width of the depletion layer in the depth direction of the semiconductor material; A step of measuring the leakage current flowing across the n-junction or the Schottky junction and estimating the change in the lifetime of the generated carriers based on the change in the measured value of the leakage current, and the step of estimating the change in the lifetime of the generated carriers based on the change in the generated lifetime. A method for evaluating crystals of semiconductor materials, including a step of evaluating crystal states in directions. (2) A crystal evaluation method for a semiconductor material according to claim 1, wherein the leakage current is measured at a temperature (generally low temperature) at which the generated current is dominant over the diffusion current.