JPH0467435B2 - - Google Patents

Info

Publication number
JPH0467435B2
JPH0467435B2 JP59124747A JP12474784A JPH0467435B2 JP H0467435 B2 JPH0467435 B2 JP H0467435B2 JP 59124747 A JP59124747 A JP 59124747A JP 12474784 A JP12474784 A JP 12474784A JP H0467435 B2 JPH0467435 B2 JP H0467435B2
Authority
JP
Japan
Prior art keywords
circuit
signal
switching element
semiconductor switching
pulse width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59124747A
Other languages
Japanese (ja)
Other versions
JPS614470A (en
Inventor
Ryoji Saito
Yoshio Suzuki
Kazuhiro Senoo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Origin Electric Co Ltd
Original Assignee
Origin Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Origin Electric Co Ltd filed Critical Origin Electric Co Ltd
Priority to JP59124747A priority Critical patent/JPS614470A/en
Publication of JPS614470A publication Critical patent/JPS614470A/en
Publication of JPH0467435B2 publication Critical patent/JPH0467435B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体スイツチング素子を高周波変換
周波数でパルス幅変調して制御された出力を得る
電力変換装置の制御方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for controlling a power conversion device that obtains a controlled output by pulse width modulating a semiconductor switching element at a high frequency conversion frequency.

〔従来の技術とその問題点〕[Conventional technology and its problems]

第3図は従来の電力変換装置の制御方法を示す
図であり、第4図は第3図の各部の動作波形を示
す図である。第3図において、電力変換装置の出
力から誤差増幅器1を介して得られた出力誤差信
号を比較回路入力信号S1とし、該比較回路入力信
号S1とパルス幅制御基準信号S2とを比較回路2で
比較し、第4図に示すように上記比較回路入力信
号S1とパルス幅制御基準信号S2とが一致したとき
に比較回路2はパルス発生器3に信号を送付す
る。この信号が印加されるとパルス発生回路3は
半導体スイツチング素子4へオフ信号S3を送付
し、該半導体スイツチング素子4をオフする。し
かしこの従来の電力変換装置の制御方法では電力
変換装置の出力又は検出系統にノイズ等が発生し
た場合には、誤差増幅器1を介して比較回路入力
信号S1にノイズ等が重畳し、電力変換装置を誤動
作させる原因となる。また、このノイズ等を除去
する為に、抵抗及びコンデンサからなるフイルタ
(図示せず)を誤差増幅器1、比較回路2間に挿
入すると、電力変換装置の高速応答性が保持でき
なくなるという欠点があつた。
FIG. 3 is a diagram showing a conventional control method for a power conversion device, and FIG. 4 is a diagram showing operating waveforms of each part in FIG. 3. In FIG. 3, the output error signal obtained from the output of the power conversion device via the error amplifier 1 is used as the comparison circuit input signal S 1 , and the comparison circuit input signal S 1 and the pulse width control reference signal S 2 are compared. Comparison is made in circuit 2, and when the comparison circuit input signal S 1 and pulse width control reference signal S 2 match as shown in FIG. 4, comparison circuit 2 sends a signal to pulse generator 3. When this signal is applied, the pulse generating circuit 3 sends an off signal S3 to the semiconductor switching element 4 to turn off the semiconductor switching element 4. However, in this conventional power converter control method, if noise or the like occurs in the output or detection system of the power converter, the noise or the like is superimposed on the comparator circuit input signal S1 via the error amplifier 1 , and the power converter is This may cause the device to malfunction. Furthermore, if a filter (not shown) consisting of a resistor and a capacitor is inserted between the error amplifier 1 and the comparator circuit 2 in order to remove this noise, there is a drawback that the high-speed response of the power converter cannot be maintained. Ta.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は以上の欠点を除去するために高周波変
換周波数の周期毎にほぼ1周期にわたつて出力誤
差信号を積分し、該積分値をホールドし、該ホー
ルド値とパルス幅制御基準信号とを比較して半導
体スイツチング素子のパルス幅を制御することを
特徴とする電力変換装置の制御方法を提供するも
のである。
In order to eliminate the above drawbacks, the present invention integrates the output error signal over approximately one period for each period of the high frequency conversion frequency, holds the integrated value, and compares the held value with a pulse width control reference signal. The present invention provides a method for controlling a power conversion device, which is characterized by controlling the pulse width of a semiconductor switching element.

〔実施例〕〔Example〕

第1図は本発明の一実施例を示す図であり、第
2図は第1図の各部の動作波形を示す図である。
第1図において、電力変換装置の出力から誤差増
幅器1を介して得られた出力誤差信号を電圧電流
変換回路5により電流に変換して積分回路6でほ
ぼ1周期にわたつて積分し、該積分値をパルス発
生器3からのホールドパルス信号S4によりホール
ド回路7でホールドし、得られたホールド値を比
較回路入力信号S1とし、該比較回路入力信号S1
パルス幅制御基準信号S2とを比較回路2で比較
し、第2図に示すように上記比較回路入力信号S1
とパルス幅制御基準信号S2とが一致したときに比
較回路2はパルス発生回路3に信号を送付する。
この信号が印加されるとパルス発生器3は半導体
スイツチング素子4へオフ信号S3を送付し、該半
導体スイツチング素子4をオフする。一方上記ホ
ールド回路7で上記積分値がホールドされた直後
にパルス発生器3から積分回路6に積分リセツト
パルス信号S5が送付され積分回路6がリセツトさ
れ、再びほぼ1周期にわたつて積分されることと
なる。このような電力変換装置の制御方法にあつ
ては、電力変換装置の出力又は検出系統にノイズ
が発生しても、ノイズは変換周期で平均化される
のでノイズの影響を少なくでき、またスイツチン
グによるリツプル成分の影響をなくすことができ
る。更に以上のことを高速応答性を保持しながら
できる。
FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing operating waveforms of each part of FIG. 1.
In FIG. 1, an output error signal obtained from the output of a power conversion device via an error amplifier 1 is converted into a current by a voltage-current conversion circuit 5, and is integrated over approximately one cycle by an integration circuit 6. The value is held in the hold circuit 7 by the hold pulse signal S4 from the pulse generator 3, and the obtained hold value is used as the comparator circuit input signal S1 , and the comparator circuit input signal S1 and the pulse width control reference signal S2 The comparator circuit 2 compares the input signal S 1 with the comparator circuit input signal S 1 as shown in FIG.
The comparison circuit 2 sends a signal to the pulse generation circuit 3 when the pulse width control reference signal S 2 and the pulse width control reference signal S 2 match.
When this signal is applied, the pulse generator 3 sends an off signal S3 to the semiconductor switching element 4 to turn off the semiconductor switching element 4. On the other hand, immediately after the above-mentioned integral value is held in the above-mentioned hold circuit 7, an integration reset pulse signal S5 is sent from the pulse generator 3 to the integration circuit 6, the integration circuit 6 is reset, and the integration is again performed over approximately one cycle. That will happen. In such a control method for a power converter, even if noise occurs in the output or detection system of the power converter, the noise is averaged over the conversion cycle, so the influence of noise can be reduced, and the effects of switching can be reduced. The influence of ripple components can be eliminated. Furthermore, the above can be done while maintaining high-speed response.

第5図は本発明の他の一実施例を示す図であ
り、三相入力電源より、各相の入力電流を正弦波
状に保ちつつ直流出力を得る電力変換装置であ
る。第6図は第5図の各部の動作波形を示す図で
ある。第5図において、電力変換装置の出力から
誤差増幅器1を介して得られた電圧を電圧電流変
換回路5により電流に変換して積分回路6でほぼ
1周期にわたつて積分し、該積分値をパルス発生
器3からのホールドパルス信号S4によりホールド
回路7でホールドする。一方上記ホールド回路7
で上記積分値がホールドされた直後にパルス発生
器3から積分回路6に積分リセツトパルス信号S5
が送付され、積分回路6はリセツトされ、再びほ
ぼ1周期にわたつて積分されることとなる。次に
高周波コンバータ8の半導体スイツチング素子を
通流する主回路電流を電流検出回路9により検出
し、乗算器10により上記ホールド値との乗算値
を得、電圧電流変換回路11により電流に変換し
てゲート回路12(U、V、W)がゲートされて
いる期間のみ積分回路13(U、V、W)で積分
し、該積分値を比較回路入力信号S1(UVW)
し、該比較回路入力信号S1(UVW)とパルス幅制
御基準信号S2(UVW)とを比較回路2(U、V、
W)で比較し、第6図に示すように上記比較回路
入力信号S1(UVW)と電流基準信号S2(UVW)
が一致したときに比較回路2(U、V、W)はパ
ルス発生回路3に信号を送付する。この信号が印
加されるとパルス発生回路3は高周波インバータ
8の半導体スイツチング素子へオフ信号
S3(UVW)を送付して該半導体スイツチング素子
をオフし、同時に積分回路13(U、V、W)に
リセツトパルス信号S6(UVW)を送付して該積分
回路13(U、V、W)を瞬時にリセツトする。
ゲート回路12(U、V、W)は対応する高周波
コンバータ8の半導体スイツチング素子が導通し
ている間ゲートする。該半導体スイツチング素子
は上記比較回路2(U、V、W)が信号を発生し
てから制御回路の遅れ、上記半導体スイツチング
素子のストレージタイム等による遅れで暫く導通
するが、この電流を上述の動作にて積分回路13
(U、V、W)に電流積分値として取り込む。従
つてターンオフの遅れによる電流は次のサイクル
のパルス幅決定で補正され、上記半導体スイツチ
ング素子を通流する電流の1サイクルの積分値と
電流基準制御信号S2(UVW)とは上記半導体スイ
ツチング素子のターンオフやオフ信号の遅れに拘
わらず良い線形性を保つことができる。即ち電流
基準制御信号S2(UVW)の大小に応じて主回路電
流を良い比例関係を保つて制御することができ
る。第5図の実施例は電力変換装置の電力制御と
して2つの制御入力即ち出力誤差制御信号と電流
基準制御信号を持ち、いずれにしても電力制御が
可能であるが電力変換装置が2つの制御目標を持
つ時特に有効である。他は第1図の実施例で述べ
たのとほぼ同様の効果がある。尚、14(U、
V、W)はゲート回路12(U、V、W)、積分
回路13(U、V、W)及び比較回路2(U、
V、W)からなる積分比較回路である。
FIG. 5 is a diagram showing another embodiment of the present invention, which is a power conversion device that obtains DC output from a three-phase input power source while maintaining the input current of each phase in a sinusoidal waveform. FIG. 6 is a diagram showing operating waveforms of each part in FIG. 5. In FIG. 5, a voltage obtained from the output of the power conversion device via an error amplifier 1 is converted into a current by a voltage-current conversion circuit 5, and is integrated over approximately one cycle by an integrating circuit 6, and the integrated value is A hold pulse signal S4 from the pulse generator 3 is used to hold the signal in the hold circuit 7. On the other hand, the above hold circuit 7
Immediately after the above integral value is held, an integral reset pulse signal S5 is sent from the pulse generator 3 to the integrating circuit 6.
is sent, the integration circuit 6 is reset, and integration is again performed over approximately one cycle. Next, the main circuit current flowing through the semiconductor switching element of the high frequency converter 8 is detected by the current detection circuit 9, multiplied by the above-mentioned hold value by the multiplier 10, and converted into a current by the voltage-current conversion circuit 11. The integration circuit 13 (U, V, W) integrates only during the period when the gate circuit 12 (U, V, W) is gated, and the integrated value is used as the comparison circuit input signal S 1 (U , V , W) , The comparison circuit input signal S 1 (U , V , W) and the pulse width control reference signal S 2 (U , V , W) are connected to the comparison circuit 2 (U, V, W).
When the comparison circuit input signal S 1 (U , V , W) and the current reference signal S 2 (U , V , W) match as shown in FIG. U, V, W) send signals to the pulse generation circuit 3. When this signal is applied, the pulse generating circuit 3 sends an off signal to the semiconductor switching element of the high frequency inverter 8.
S 3 (U , V , W) is sent to turn off the semiconductor switching element, and at the same time, a reset pulse signal S 6 (U, V, W) is sent to the integrating circuit 13 (U , V , W) to turn off the semiconductor switching element. Instantly resets the integration circuit 13 (U, V, W).
The gate circuit 12 (U, V, W) is gated while the semiconductor switching element of the corresponding high frequency converter 8 is conductive. The semiconductor switching element conducts for a while after the comparison circuit 2 (U, V, W) generates a signal due to a delay in the control circuit, a delay due to the storage time of the semiconductor switching element, etc., but this current is passed through the operation described above. Integrating circuit 13 at
(U, V, W) as the current integral value. Therefore, the current due to the turn-off delay is corrected by determining the pulse width of the next cycle, and the integral value of one cycle of the current flowing through the semiconductor switching element and the current reference control signal S 2 (U , V , W) are Good linearity can be maintained regardless of the turn-off of the semiconductor switching element or the delay of the off signal. That is, the main circuit current can be controlled while maintaining a good proportional relationship depending on the magnitude of the current reference control signal S 2 (U , V , W) . The embodiment shown in FIG. 5 has two control inputs, that is, an output error control signal and a current reference control signal, for power control of the power converter, and although power control is possible in any case, the power converter has two control targets. This is especially effective when you have . Other effects are substantially the same as those described in the embodiment shown in FIG. In addition, 14 (U,
V, W) are the gate circuit 12 (U, V, W), the integrating circuit 13 (U, V, W) and the comparison circuit 2 (U,
This is an integral comparison circuit consisting of V, W).

第5図の実施例では、複数個のスイツチング素
子を時分割で制御しているが、回路方式により複
数個のスイツチング素子を同時につまり多重制御
しても同様の効果がある。
In the embodiment shown in FIG. 5, a plurality of switching elements are controlled in a time-division manner, but the same effect can be obtained even if a plurality of switching elements are controlled simultaneously, that is, multiplexed, using a circuit system.

〔発明の効果〕 以上述べたように本発明は高周波変換周波数の
周期毎に出力誤差信号をほぼ1周期にわたつて積
分し、該積分値をホールドし、該ホールド値とパ
ルス幅制御基準信号とを比較して半導体スイツチ
ング素子のパルス幅を制御することを特徴とする
電力変換装置の制御方法である。本発明はこのよ
うな特徴を有するので高速応答性を保ちつつ、ノ
イズの影響を少なくし、また変換周期のリツプル
の影響をなくすことができる。また、複数個の半
導体スイツチング素子を制御する場合には各半導
体スイツチング素子間の制御バランスが良くな
る。
[Effects of the Invention] As described above, the present invention integrates the output error signal over approximately one period for each period of the high frequency conversion frequency, holds the integrated value, and uses the held value and the pulse width control reference signal. This is a control method for a power conversion device, characterized in that the pulse width of a semiconductor switching element is controlled by comparing the pulse width of the semiconductor switching element. Since the present invention has such characteristics, it is possible to reduce the influence of noise and eliminate the influence of ripples in the conversion period while maintaining high-speed response. Furthermore, when controlling a plurality of semiconductor switching elements, the control balance among the semiconductor switching elements is improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す図、第2図は
第1図の各部の動作波形を示す図、第3図は従来
の電力変換装置の制御方法を示す図、第4図は第
3図の各部の動作波形を示す図、第5図は本発明
の他の一実施例を示す図、第6図は第5図の各部
の動作波形を示す図である。 1……誤差増幅器、2……比較回路、3……パ
ルス発生器、4……半導体スイツチング素子、
5,11……電圧電流変換回路、6,13……積
分回路、7……ホールド回路、8……高周波コン
バータ、9……電流検出回路、10……乗算器、
12……ゲート回路、14……積分比較回路。
FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing operating waveforms of each part of FIG. 1, FIG. 3 is a diagram showing a conventional control method for a power converter, and FIG. FIG. 5 is a diagram showing another embodiment of the present invention, and FIG. 6 is a diagram showing operating waveforms of each part in FIG. 5. 1...Error amplifier, 2...Comparison circuit, 3...Pulse generator, 4...Semiconductor switching element,
5, 11... Voltage current conversion circuit, 6, 13... Integrating circuit, 7... Hold circuit, 8... High frequency converter, 9... Current detection circuit, 10... Multiplier,
12...gate circuit, 14...integral comparison circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 少なくとも1つの半導体スイツチング素子を
高周波変換周波数でスイツチングし、出力誤差信
号によりパルス幅変調して制御された出力を得る
電力変換装置の制御方法において、上記高周波変
換周波数の周期毎に略1周期にわたつて上記出力
誤差信号を積分し、該積分値をホールドし、該ホ
ールド値とパルス幅制御基準信号とを比較して上
記半導体スイツチング素子のパルス幅を制御する
ことを特徴とする電力変換装置の制御方法。
1. A method for controlling a power conversion device in which at least one semiconductor switching element is switched at a high frequency conversion frequency, and a controlled output is obtained by pulse width modulation using an output error signal, in which the switching element is switched at approximately one period for each period of the high frequency conversion frequency. A power conversion device comprising: integrating the output error signal over the output signal, holding the integrated value, and comparing the held value with a pulse width control reference signal to control the pulse width of the semiconductor switching element. Control method.
JP59124747A 1984-06-18 1984-06-18 Controlling method of power converter Granted JPS614470A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59124747A JPS614470A (en) 1984-06-18 1984-06-18 Controlling method of power converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59124747A JPS614470A (en) 1984-06-18 1984-06-18 Controlling method of power converter

Publications (2)

Publication Number Publication Date
JPS614470A JPS614470A (en) 1986-01-10
JPH0467435B2 true JPH0467435B2 (en) 1992-10-28

Family

ID=14893105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59124747A Granted JPS614470A (en) 1984-06-18 1984-06-18 Controlling method of power converter

Country Status (1)

Country Link
JP (1) JPS614470A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6443668A (en) * 1987-08-08 1989-02-15 Kenzai Kako Kk Method of cut-off construction of concrete wall

Also Published As

Publication number Publication date
JPS614470A (en) 1986-01-10

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