JPH0467299U - - Google Patents
Info
- Publication number
- JPH0467299U JPH0467299U JP10893090U JP10893090U JPH0467299U JP H0467299 U JPH0467299 U JP H0467299U JP 10893090 U JP10893090 U JP 10893090U JP 10893090 U JP10893090 U JP 10893090U JP H0467299 U JPH0467299 U JP H0467299U
- Authority
- JP
- Japan
- Prior art keywords
- pull
- buffer circuit
- nmos
- transistor
- push
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Electronic Switches (AREA)
- Logic Circuits (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10893090U JPH0467299U (enExample) | 1990-10-19 | 1990-10-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10893090U JPH0467299U (enExample) | 1990-10-19 | 1990-10-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0467299U true JPH0467299U (enExample) | 1992-06-15 |
Family
ID=31856072
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10893090U Pending JPH0467299U (enExample) | 1990-10-19 | 1990-10-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0467299U (enExample) |
-
1990
- 1990-10-19 JP JP10893090U patent/JPH0467299U/ja active Pending
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