JPH0467279B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a redundant circuit used in place of a defective memory cell thereof.

[Conventional technology]

The larger the capacity of a semiconductor memory device, the more likely it is that defective memory cells will occur. Therefore, by creating extra memory cells in advance (creating redundant word lines and/or bit lines), it is possible to detect defective cells during testing. Then, the word line or bit line containing the defective cell is replaced with a redundant word line or bit line.

FIG. 3 shows a previously proposed circuit (Japanese Patent Application No. 59-238581) in which a bipolar memory is provided with redundant word lines.
1 is a memory cell array, 10 is a redundant word line, 2 is
. . . 11 is a word driver, 4 is an address buffer, 12 is a PROM that stores the address of the word line where the defective memory cell is located, and 13 is an exclusive OR gate. ADD is an address for accessing the memory, and although only one bit is shown and explained here, it is actually a plurality of bits, and there are also a plurality of address buffers 4, exclusive OR gates 13, etc.

When the address bit ADD is H (high) "1", the inverted output of gate 4 is L (low), the non-inverted output is H, and since the decoder of this memory is L selection, L
A word driver connected to the decoder lines 51 and 52 (only one of which is set to L by an address buffer not shown), which is at the high level, sets the word line to the H level and selects the word line. The address bit ADD is also applied to one input terminal of the exclusive OR gate 13, and if the address of the word line containing the defective cell output by the PROM 12 does not match, the output SR of the gate 13 becomes H level (reference level). Activate 2...,
11 to the word line non-selected state.

On the other hand, address bit ADD and PROM1
When the output address bits of the word drivers 2 and 11 match, the output SR of the exclusive OR gate 13 goes to the L level, which puts the word drivers 2... into the word line non-selected state and the 11
to the word line selected state. In this way, in this memory, when a defective cell (more specifically, word line) is accessed, a redundant word line is selected, and the corresponding memory cell (more specifically, word line) of the normal memory cell array 1 is unselected, and a non-defective cell is accessed. The opposite is true when

FIG. 4 shows details of FIG. 3. The memory cell array 1 has a large number of word line pairs WL+, WL-, bit line pairs BL, BLB, and flip-flop type memory cells MC provided at each intersection of these. The redundant word line 10 has a similar configuration, but in this example, only one word line is provided. WL(R) is its redundant word line. Word driver 2 is resistor R1
, transistors Q ₁ to Q ₃ and constant current source IS1,... resistor R2, transistors Q ₄ to Q ₆ and constant current source IS2,...
...Resistor R8, transistors _Q20 to _Q22 , and constant current source
Each set of IS14 is included for each word line. Address buffer 4 consists of transistors Q ₇ to Q ₁₀ and resistor R
3, R4, and constant current sources IS3 to I5, and the output drives the decoder line 5 via transistors _Q11 and _Q12 . Exclusive OR gate 13 is a transistor
_Q13 to _Q19 , resistors R5 to R7, diode D1,
It consists of constant current sources IS10 to IS13. Vcc, Vee are power supplies, VRF2 to VRF5 are reference voltages, IS6 to IS9
is a constant current source.

[Problem that the invention seeks to solve]

Redundant cells are word line or bit line units,
It is normal to have a small number of bottles, such as one or two bottles. If a large number of memory cells are provided, it is possible to cope with the occurrence of a large number of defective cells and improve yield, but this increases the capacity of the PROM that stores defective addresses, the scale of the address comparison circuit, etc., and is constrained in this respect.

The present invention aims to improve these points and provide a redundant circuit that can cope with the occurrence of a large number of defective wires without increasing the size of the comparator circuit or the like.

[Means for solving problems]

The semiconductor memory device of the present invention has an upper address input terminal to which an upper address signal is input, a lower address input terminal to which a lower address signal is input, a plurality of word lines and bit lines, and a plurality of word lines and bit lines. A regular memory cell array with memory cells arranged at intersections, a plurality of word lines or bit lines, and memory cells connected to them, and a redundant memory cell array with a smaller capacity than the regular memory cell array. a first selection means for selecting a word line or a bit line belonging to the regular memory cell array according to the upper address signal and the lower address signal, the ECL gate and the driver transistor; a second selection means for selecting a word line or a bit line belonging to the redundant memory cell array according to the lower address signal, and storing an upper address included in the address corresponding to the defective memory cell in the normal memory cell array. The redundant address storage means compares the input upper address signal with the address stored in the redundant address storage means, and when the two match, the level of the reference input of the ECL gate of the first selection means is changed. and control means for controlling the level of the reference input of the ECL gate of the second selection means to a level that prohibits selection of the regular memory cell array and instead sets the level of the reference input of the ECL gate of the second selection means to a level that allows selection of the redundant memory cell array. It is characterized by

[Effect]

If the redundant circuit is made up of multiple word line segments or bit line segments, and the redundant circuit is selected instead of the word line or bit line when a defective memory cell is accessed, the bits of the defective cell address to be stored will be The number of defective cells can be reduced, making the circuit relatively small-scale, and within the range of the plurality of cells, a large number of defective cells can be replaced with redundant circuits, which is extremely effective.

〔Example〕

FIG. 1 shows an embodiment of the present invention. The same parts as in FIGS. 3 and 4 are given the same reference numerals. The address of the word line containing the defective cell is stored in a PROM (programmable ROM), and when the address ADD for accessing the memory matches this PROM storage address, the output of the exclusive OR gate 13 becomes L level, which is passed through the OR gate 15. Then, the word driver 2 of the regular memory cell is set to non-selected word line, and the signal is passed through the inverter 16 to the driver 11 of the redundant word line to set it to the word line selected state, and the memory access address ADD is set to the word line selected state.
If it does not match the PROM memory address, reverse this.
That is, the point that the word driver 2 is activated and the word line 11 is made non-selected is the same as in FIG. 3, but in this circuit, this switching is performed in units of blocks (a plurality of word lines or bit lines). In this way, the number of bits of the address to be stored in the PROM and compared is only a portion, and the PROM capacity can be reduced and the comparison circuit can be simplified. Furthermore, even if defective cells occur in a plurality of word lines or bit lines within the block, this can be dealt with, and the repair range is expanded, thereby improving yield.

In this figure 1, the address to access memory is
ADD is divided into two parts, ADD ₁ (upper) and ADD ₂ (lower), and the former is connected to address inverter 4...
...The decoder line group 5A is driven through the transistors Q ₁₁ , Q ₁₂ ..., and the latter is the address inverter 1.
4. Drive the decoder line group 5B via transistors Q ₄₁ and Q ₄₂ . In word driver 2, that
Transistors Q ₁ and Q ₃₁ that constitute the ECL gate are connected to one line of the line groups 5A and 5B, and when the input SR of the exclusive OR gate 13 is at H level (reference level) and both of these decoder lines are at L level, the corresponding Set the word line to H level (same for drivers for other word lines).

The address stored in the PROM is part of the memory access address, in this example the upper address ADD ₁
This is quite significant, and Exclusive OR Gate 13 is based on this
Compare ADD ₁ and PROM storage address. In Figure 1, only 1 bit of ADD ₁ and 1 bit of PROM are shown, but in reality, ADD ₁ , PROM, and exclusive OR gates are provided as many as the number of bits of the upper address.
The respective outputs are combined by an OR gate 15, and the logical sum output becomes the output SR.

When PROM storage address and memory access upper address ADD ₁ match, signal SR and its inversion
SRB is output, transistor Q ₂ ... is turned off, and word driver 2 ... for the regular memory cell is turned off.
... to the word line unselected state, and the transistor
Apply a reference level (signal SRB) to Q ₂₀ ... to activate driver 11 for the redundant word line, and connect the driver connected to the line whose transistor Q ₂₁ ... is at the L level of line group 5B to the redundant word line. Make it selected.

FIG. 2 shows the details of FIG. 1 assuming that the cell array 1 has 32 word lines and the redundant circuit has 4 word lines. If there are 32 word lines, the number of address bits is five, and if there are four redundant word lines, the number of address bits for the word line segment of the redundant circuit is two. Therefore, the upper address ADD ₁ has 3 bits, the lower address ADD ₂ has 2 bits, the address stored in the PROM has 3 bits, and the number of exclusive OR gates 13 is also 3. Transistor Q ₄₃ ,
Q ₄₄ constitutes an OR circuit 15 for the outputs of these exclusive OR gates, and transistor Q ₅₀ constitutes an inverter 16 for the outputs of the OR gates 15. Output a corresponds to the SR, and output b corresponds to the SRB. When a cell of the regular memory cell array is selected (usually), output a is H and b is L; when a redundant cell is selected (redundant), output a is L and b is H.

In addition to one block of 4 word lines, the redundant circuit includes
When n and m are arbitrary integers of 2 or more, one block of n-bit lines, m blocks of n-word lines (in this case, the number of addresses to be stored is m), etc. can be set.

〔Effect of the invention〕

As explained above, in the present invention, a plurality of redundant word lines and/or redundant bit lines that can be represented by a part of an address are used as a unit, and a word line and/or bit line having a defective cell is replaced with this redundant circuit. , the comparison circuit etc. can be simplified,
Since a large number of defective cells occurring within the unit can be replaced by the single redundant circuit without impairing high speed, the range of possible repairs is expanded and the yield can be improved.

[Brief explanation of the drawing]

FIG. 1 is a schematic circuit diagram showing an embodiment of the present invention, FIG. 2 is a detailed circuit diagram of FIG. 1, and FIGS. 3 and 4 are already proposed circuit diagrams. In the drawing, 1 is a memory cell array, WL is a word line, BL, BLB are bit lines, MC is a memory cell,
10 is a redundant circuit, PROM is a memory for storing addresses, and 13 is a comparison circuit.

Claims (1)

[Scope of Claims] 1. A semiconductor memory device comprising: an upper address input terminal to which an upper address signal is input; a lower address input terminal to which a lower address signal is input; a plurality of word lines and bit lines; A regular memory cell array in which memory cells are arranged at the intersections of word lines or bit lines, and has a plurality of word lines or bit lines and memory cells connected thereto, Redundant memory cell array with low capacity, ECL gate and driver transistor,
a first selection means for selecting a word line or a bit line belonging to the regular memory cell array according to the upper address signal and the lower address signal, comprising an ECL gate and a driver transistor;
a second selection means for selecting a word line or a bit line belonging to the redundant memory cell array based on the lower address signal; a redundant address memory for storing an upper address included in an address corresponding to a defective memory cell in the normal memory cell array; Comparing the input upper address signal with the address stored in the redundant address storage means,
When the two match, the ECL of the first selection means
control to control the level of the reference input of the gate to a level that prohibits selection of the regular memory cell array, and instead the level of the reference input of the ECL gate of the second selection means to a level that allows selection of the redundant memory cell array; 1. A semiconductor memory device comprising: means.