JPH0463672U - - Google Patents
Info
- Publication number
- JPH0463672U JPH0463672U JP10753590U JP10753590U JPH0463672U JP H0463672 U JPH0463672 U JP H0463672U JP 10753590 U JP10753590 U JP 10753590U JP 10753590 U JP10753590 U JP 10753590U JP H0463672 U JPH0463672 U JP H0463672U
- Authority
- JP
- Japan
- Prior art keywords
- power
- terminal
- substrate
- power terminal
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims 2
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Mounting Of Printed Circuit Boards And The Like (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
第１図はこの考案の一実施例を示す要部図解図
である。第２図は第１図に示すプリント基板をシ
ステムに初期的に挿入した時の状態を示す図解図
である。第３図は第１図に示すプリント基板を第
２図に示した状態から、システムにさらに挿入し
た時の状態を示す図解図である。
図において、１０はプリント基板、１２は基板
、１４は第１の電源端子、１６は第２の電源端子
、１８は抵抗、２０はコンデンサ、２２は別の端
子、２４はさらに別の端子、１００はシステムを
示す。
FIG. 1 is an illustrative view of the main parts showing an embodiment of this invention. FIG. 2 is an illustrative view showing the state when the printed circuit board shown in FIG. 1 is initially inserted into the system. FIG. 3 is an illustrative view showing the state in which the printed circuit board shown in FIG. 1 is further inserted into the system from the state shown in FIG. 2. In the figure, 10 is a printed circuit board, 12 is a board, 14 is a first power terminal, 16 is a second power terminal, 18 is a resistor, 20 is a capacitor, 22 is another terminal, 24 is yet another terminal, 100 indicates a system.
Claims (1)
前記第１の電源端子と間隔を隔てて並列に配置さ
れ、前記基板をシステムに挿入したときに最終的
に前記システム側の電源回路に接続される第２の
電源端子、 前記第１の電源端子と前記第２の電源端子との
間に接続される抵抗、および 前記第２の電源端子に接続されるコンデンサを
含む、プリント基板。[Claims for Utility Model Registration] A substrate, a first power terminal formed at an end of the substrate,
a second power terminal that is arranged in parallel with the first power terminal at an interval and is finally connected to a power circuit on the system side when the board is inserted into the system; the first power terminal; and the second power supply terminal; and a capacitor connected to the second power supply terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10753590U JPH0463672U (en) | 1990-10-13 | 1990-10-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10753590U JPH0463672U (en) | 1990-10-13 | 1990-10-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0463672U true JPH0463672U (en) | 1992-05-29 |
Family
ID=31854099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10753590U Pending JPH0463672U (en) | 1990-10-13 | 1990-10-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0463672U (en) |
-
1990
- 1990-10-13 JP JP10753590U patent/JPH0463672U/ja active Pending
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