JPH0463444A - Manufacturing device of semiconductor memory device - Google Patents

Manufacturing device of semiconductor memory device

Info

Publication number
JPH0463444A
JPH0463444A JP2177014A JP17701490A JPH0463444A JP H0463444 A JPH0463444 A JP H0463444A JP 2177014 A JP2177014 A JP 2177014A JP 17701490 A JP17701490 A JP 17701490A JP H0463444 A JPH0463444 A JP H0463444A
Authority
JP
Japan
Prior art keywords
fixing material
wire bonding
semiconductor memory
frame
molding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2177014A
Other languages
Japanese (ja)
Inventor
Yuko Ozeki
尾関　祐子
Takayuki Miyamoto
宮元　崇行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2177014A priority Critical patent/JPH0463444A/en
Publication of JPH0463444A publication Critical patent/JPH0463444A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

Abstract

PURPOSE:To increase in stability at the time of molding and wire bonding in order to prevent generation of a defect by connecting supporting projections in one or several spots to a frame by means of a fixing material. CONSTITUTION:A substance to be melted or buried into a finished article at the time of molding is used for a fixing material. Both ends of the fixing material 8 is fixed to a frame 1, and supporting projections 7 are fixed by this fixing material 8 followed by wire bonding pads 3 and lead terminals 4 with wires 5, and after wire bonding the whole is molded as it is. Thereby, generation of defectives to be caused by instability of semiconductor chips at the time of wire bonding and molding can be prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体記憶装置の製造装置に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an apparatus for manufacturing a semiconductor memory device.

〔従来の技術〕[Conventional technology]

従来の半導体記憶装置のアセンブリ時のフレーム形状を
第２図に示す。FIG. 2 shows the frame shape of a conventional semiconductor memory device when assembled.

従来のフレーム形状は図に示すように、フレーム（１）
にグイバット（２）が一方向から支持されている。The conventional frame shape is frame (1) as shown in the figure.
Guibat (2) is supported from one direction.

ボンディングパット（３）とリード端子（４）をワイヤ
（５）で接続している。A bonding pad (3) and a lead terminal (4) are connected by a wire (5).

次に動作について説明する。Next, the operation will be explained.

半導体記憶装置のアセンブリ時、ダイパット（２）に半
導体チップ（６）をダイボンディングする。その後、リ
ード端子（４）とボンディングバット（３）をワイヤ（
５）でワイヤボンディングする。ワイヤボンディング終
了後、全体をモールド成形して不必要な部分をカットす
る。When assembling a semiconductor memory device, a semiconductor chip (6) is die-bonded to a die pad (2). Then, connect the lead terminal (4) and bonding butt (3) to the wire (
5) Perform wire bonding. After wire bonding is complete, mold the entire piece and cut out unnecessary parts.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体記憶装置の製造装置は以上のように構成さ
れていたので、ダイパットが一方向からしか支持されて
おらず、ボンディングパットとリード端子をワイヤでワ
イヤボンディングする時、又はその後モールド成形をす
る際の不安定のために不良が生じるという問題点があっ
た。Conventional semiconductor memory device manufacturing equipment was configured as described above, so the die pad was supported only from one direction, and when the bonding pad and lead terminal were wire bonded with wire, or after molding. There was a problem that defects occurred due to instability during the process.

この発明は上記のような問題点を解決するためになされ
たもので、モールド成形時、ワイヤボンディング時に発
生する不良を防止することを目的とする。This invention was made to solve the above-mentioned problems, and its purpose is to prevent defects that occur during molding and wire bonding.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体記憶装置の製造装置は、１か所又
は数か所に支持突起を設け、プラスチックなどの固定材
料で支持突起とフレームを結合固定するようにしたもの
である。In the semiconductor memory device manufacturing apparatus according to the present invention, support protrusions are provided at one or several locations, and the support protrusions and the frame are coupled and fixed using a fixing material such as plastic.

〔作　用〕[For production]

この発明における半導体記憶装置の製造装置は１か所又
は数か所の支持突起を固定材料でフレームと結合するこ
とにより、モールド時ワイヤボンディング時の安定性を
増大して不良発生を防止する。The semiconductor memory device manufacturing apparatus according to the present invention increases stability during wire bonding during molding and prevents defects by connecting one or several support protrusions to the frame using a fixing material.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第１図において、（１）はフレーム、（２）はダイパッ
ト、（３）はボンディングパット、（４）はリード端子
、（５）はワイヤ、（６）は半導体チップ、（７）は新
たに設けられた支持突起、（８）は支持突起（７）をフ
レーム（１）と固定するための固定材料である。In Figure 1, (1) is a frame, (2) is a die pad, (3) is a bonding pad, (4) is a lead terminal, (5) is a wire, (6) is a semiconductor chip, and (7) is a new The provided support projection (8) is a fixing material for fixing the support projection (7) with the frame (1).

なお固定材料（８）はモールド時に溶解又は完成品内に
埋め込まれるものを使用している。The fixing material (8) used is one that is melted during molding or embedded in the finished product.

固定材料（８）の両端をフレーム（１）に固定し、支持
突起（７）をこの固定材料（８）で固定する。Both ends of the fixing material (8) are fixed to the frame (1) and the support projections (7) are fixed with this fixing material (8).

以上のような構成において支持突起（７）を固定材料（
８）によって固定した後、ボンディングパット（３）と
リード端子（４）をワイヤ（５）でワイヤボンディング
する。ワイヤボンディング後そのまま全体をモールド成
形する。In the above configuration, the support protrusion (7) is fixed with a fixing material (
8), the bonding pad (3) and the lead terminal (4) are wire-bonded using the wire (5). After wire bonding, the entire structure is molded.

ワイヤボンディング時、モールド時の半導体チップの不
安定性が引き起す不良発生を防止する効果がある。This has the effect of preventing defects caused by instability of the semiconductor chip during wire bonding and molding.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、半導体記憶装置の製造
装置において、アセンブリ時の不承発生を減少させるこ
とができ、量産性の向上が図れるという効果がある。As described above, according to the present invention, in a semiconductor memory device manufacturing apparatus, it is possible to reduce the occurrence of disapproval during assembly, and it is possible to improve mass productivity.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の一実施例である半導体記憶装置の製
造装置のアセンブリ時のワイヤボンディングモールドを
行う場合のフレームを示す平面図、第２図は従来の半導
体記憶装置の製造装置のフレームを示す平面図である。 図において、（１）はフレーム、（２）はダイパット、
（３）はボンディングパット、（４）はリード端子、（
５）はワイヤ、（６）は半導体チップ、（７）は支持突
起、（８）は固定材料を示す。 なお、図中、同一符号は同一、または相当部分を示す。FIG. 1 is a plan view showing a frame for performing wire bonding molding during assembly of a semiconductor memory device manufacturing apparatus which is an embodiment of the present invention, and FIG. 2 is a plan view showing a frame of a conventional semiconductor memory device manufacturing apparatus. FIG. In the figure, (1) is a frame, (2) is a die pad,
(3) is a bonding pad, (4) is a lead terminal, (
5) is a wire, (6) is a semiconductor chip, (7) is a support protrusion, and (8) is a fixing material. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 　半導体記憶装置を製造装置にアセンブリする時、ダイ
パットが一方向からしか支持されないフレーム形状にお
いて、固定材料を用いて他方向からもダイパットを支持
できるようにしたことを特徴とする半導体記憶装置の製
造装置。When assembling a semiconductor memory device into a manufacturing device, a frame shape in which the die pad is supported only from one direction is made so that the die pad can be supported from the other direction using a fixing material. .
JP2177014A 1990-07-02 1990-07-02 Manufacturing device of semiconductor memory device Pending JPH0463444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2177014A JPH0463444A (en) 1990-07-02 1990-07-02 Manufacturing device of semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2177014A JPH0463444A (en) 1990-07-02 1990-07-02 Manufacturing device of semiconductor memory device

Publications (1)

Publication Number Publication Date
JPH0463444A true JPH0463444A (en) 1992-02-28

Family

ID=16023657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2177014A Pending JPH0463444A (en) 1990-07-02 1990-07-02 Manufacturing device of semiconductor memory device

Country Status (1)

Country Link
JP (1) JPH0463444A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5869884A (en) * 1996-06-27 1999-02-09 Nec Corporation Semiconductor device having lead terminal on only one side of a package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5869884A (en) * 1996-06-27 1999-02-09 Nec Corporation Semiconductor device having lead terminal on only one side of a package
KR100270496B1 (en) * 1996-06-27 2000-11-01 가네꼬 히사시 Semiconductor device having lead terminal on only one side of a package

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