JPH0462629A - Electronic computer - Google Patents

Abstract

PURPOSE:To surely receive the data read out of a display storage means based on an address given from a CPU through the CPU by securing the synchronous operations between the CPU and a display control means. CONSTITUTION:The address outputted from a host CPU 1 is given to a VRAM 3 via an address bus 7 and a multiplexer 6. The data to be written into the VRAM 5 are transferred to the VRAM 3 via a data bus 8, a bidirectional buffer 10, and a VRAM bus 9. Meanwhile the data to be read out of the VRAM 3 and to be sent to the CPU 1 are transferred to the CPU 1 via the bus 9, the buffer 10, and the bus 8. A display control circuit 2 reads the data out of the VRAM 3 and displays them on a display screen 4, and the address outputted from the circuit 2 is given to the VRAM 3 via a signal line 11 and the multiplexer 6. Then the circuit 2 receives the data read out of the VRAM 5 via the bus 9 and also controls the multiplexer 6.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to electronic computers, and in particular to central processing units (CP).
U) and an improvement in an electronic computer having a display memory (VRAM) accessed by a display control circuit.

(Prior art) When adopting a bitmap control method for a display device with a relatively large screen in a conventional electronic computer, it is necessary to increase the speed of writing and reading data to and from VRAM by the host CPU. For VRA
A VRAM access method is widely used in which the access timing to M is time-divided into a read period by a display control circuit for display control and a read/write period by a host CPU.

FIG. 2 schematically shows a main part of an example of a conventional electronic computer using such a VRAM access method. Hoss) CP
The UIOI operates based on a clock signal generated from a clock generator composed of an external crystal 113 and a built-in circuit (not shown). The address output from host CPU I O1 is given to VRAM 103 via address bus 107 and multiplexer 106.

Write data from host CPUI O1 to VRAM 103 is sent to data bus lO8, buffer 110 and VR.
It is transferred to VRAMIO3 via AM bus 109.

Read data from the VRAM 103 to the host CPU 101 is transferred to the host 1-CPUIOI via the VRAM bus 109, latch 105, and data bus 108.

The display control circuit 102 reads data from the VRAMIO 3 and uses the data to display on a display device 104 such as an LCD (liquid crystal display) or CRT. The display control circuit 102 uses an external crystal 114.
It operates based on a clock signal generated from a dedicated clock generator consisting of a built-in circuit (not shown) and a built-in circuit (not shown). The address output from the display control circuit 102 is given to the VRAM 103 via a signal line 111 and a multiplexer 106. Display control circuit 1
02 is the read data from VRAM103 to VRA.
The receipt is received via the M bus 109. Display control circuit 102 also controls multiplexer 106 and latch 105.

As can be seen from the above description, the host CPU 101 and the display control circuit 102 each have their own clock source 17 and operate asynchronously with each other. The clock signal of the host CPU 10I has a lock frequency that is most appropriate for the operation of the post CPU 10I. The clock frequency of the clock signal of the display control circuit 102 is selected so that the display device 104 does not flicker or interfere with lighting or the like.

In the computer shown in FIG. 2, the display control circuit 102 has priority access to the VRAM 103. The display control circuit 102 operates, for example, with 32 clock pulses of the clock signal of the display control circuit 102 as one cycle, and reads data from the VRAM 103 during the period of 16 clock pulses in the first half of each cycle.

Therefore, the host CPU 10I is in the second half of each cycle.
VRAMI O3 can be accessed during 6 clock pulses. During the second half of this cycle, an address from host CPU 10I is selected by multiplexer 106 under control of display control circuit 102 and applied to VRAM 103. Also, host CP
UI O1 is notified by display control circuit 102 via signal line 112 that the second half of the cycle has begun. As a result, the host CPU 10I uses VRAM
Data can be read and written to 103. In this way, the display control circuit 102 and the host CPU I O1 access the VRAM 103 in a time-sharing manner. According to this method, host CPUI O1 is V
RAMI O3 can be treated like normal memory.

(Problems to be Solved by the Invention) In the dual electronic computers, the following problem occurs regarding data reading from the VRAMI 03 by the host CPUI O1. Host CPUl01 is VRAM
After starting the data read operation from the host CPU 103 and outputting the address, several wait states are usually inserted into the machine cycle of the host CPU 101 in consideration of the cycle of the display control circuit 102. When the above-mentioned period in which host CPUl0I is allowed to access VRAM103, the address becomes VRAM101.
03, and the data is output to the VRAM bus 109. However, as mentioned above, since the host CPU 10I and the display control circuit 102 operate asynchronously, the latch 1
05 to latch the data on the VRAM bus 109 under the control of the display control circuit 102. For this reason, the circuit configuration related to the bus has become complicated. Furthermore, when data is read from the VRAM 103 by the host CPUI O1, the latch 1 is
Since it was necessary to synchronize the post CPU 101 and the display control circuit 102 using the CPU 05, it was not possible to increase the access speed of the host CPU 01 to the VRAMI 03 beyond a certain level. Furthermore, a host CPU 101 and a display controller circuit 10
2, a separate clock generator is used, resulting in an unavoidable increase in cost.

The present invention was made in view of the current situation, and
The purpose is to provide an electronic computer in which the bus-related circuit configuration is simpler than before.

(Means for Solving the Problems) An electronic computer of the present invention includes a central processing unit that operates based on a clock signal from a clock generator, a display control unit that operates based on the clock signal, the central processing unit, and the central processing unit that operates based on the clock signal. A display storage means connected to the display control means via at least a data transfer signal line, and an address from the central processing unit and an address from the display control means are selectively selected under the control of the display control means. and multiplexing means for providing the data to the storage means, thereby achieving the above object.

The clock generator may be built into the central processing unit or may be externally attached to the central processing unit.

(Function) In the electronic computer of the present invention, the central processing unit and the display control means operate based on a clock signal generated from the same clock generator, and therefore, unlike the conventional art, they operate synchronously. Addresses from the central processing means are selectively applied to the display storage means by the multiplexing means under control of the display control means. The data read from the display storage means based on the address from the central processing unit is reliably received by the central processing unit because the central processing unit and the display control means operate synchronously.

(Example) The invention will now be described with reference to examples.

FIG. 1 schematically shows essential parts of an embodiment of the present invention. 1st
The electronic computer in the figure has a host CPU1, an LCD, and a CRT.
The display control circuit 2 for controlling the display device 4 such as the above uses a method in which the VRAM 3 is accessed in a time-division manner.

The CPU 1 operates based on a clock signal generated from a clock generator composed of an external crystal 5 and a built-in circuit (not shown).

The host CPUI supplies the clock signal CLK generated from this clock generator to the display control circuit 2, and the display control circuit 2 operates based on the clock signal CLK. As described above, in this embodiment, the host CPU 1 and the display control circuit 2 share the basic oscillation, that is, the host CPU 1 and the display control circuit share the basic clock signal.
1 and the display control circuit operate synchronously.

In the display control circuit 2, the display device 4 is an LC
If the clock signal C from the host CPU 1 is adjusted, the time to interrupt the data transfer is adjusted, and if the display device 4 is a CRT, the retrace time is adjusted.
Even if LK is used, care is taken to ensure that the frame frequency of the display device 4 is such that the display device 4 does not cause flicker or interference with lighting or the like. In this embodiment, the host CPU 1 has almost all of the circuits necessary for clock generation built-in, so the clock signal CLK is supplied to the display control circuit 2 of the host CPU. Host C of the required type of CPU
When used as a PUI, the clock signal generated from the clock generator may be supplied to both the host CPU 1 and the display control circuit 2.

The address output from the host CPUI is given to the VRAM 3 via the address bus 7 and multiplexer 6. Write data from the host cPU 1 to the VRAM 3 is transferred to the data bus 8, the bidirectional buffer 10, and the VRAM 3.
The data is transferred to the VRAM 3 via the bus 9. Read data from the VRAM 3 to the host cPU 1 is transferred to the host CPU I via the VRAM bus 9, bidirectional buffer 10, and data bus 8.

The display control circuit 2 reads data from the VRAM 3 and displays the data on the display device 4 using the data. The address output from the display control circuit 2 is
It is applied to the VRAM 3 via the signal line 11 and the multiplexer 6. The display control circuit 2 receives read data from the VRAM 3 via the VRAM bus 9. Display control circuit 2 also controls multiplexer 6.

In the electronic computer shown in Figure 1, as in the past, VRAM
The display control circuit 2 has priority access to 3. The display control circuit 2 operates every 8 clock pulses of the clock signal, and reads data from the VRAM 3 during the first 5 clock pulses of each cycle. Therefore, the host CPUI can write to or read from VRAM 2 during the remaining three clock pulses of each cycle. That is,
The period of the first 5 clock pulses in one cycle including 8 clock pulses is set to VR by the display control circuit 2.
This is a cycle for AM access, and the period of the remaining three clock pulses is a cycle for VRAM access by host CPU 1.

The host CPUI outputs an address to the address bus 7 at the start of an access operation to the VRAM 3. After the address is output, several wait states are usually inserted into the machine cycle of the host CPU in consideration of the VRAM access cycle of the display control circuit 2. The address output to address bus 7 is sent to multiplexer 6
and is not provided to VRAM3. Thereafter, when the period of five clock pulses at the beginning of each cycle ends, the multiplexer 6 selects the address being output from the CPU (host) and applies it to the VRAM 3 under the control of the display control circuit 2. At this time, the display control circuit 2 provides a signal to the host CPU 1 via the signal line 12 to notify that a cycle for VRAM access by the host CPU has started.

After (-), the host CPU outputs data to the data bus 8 in the case of writing data to VRAM3, using the 3 clocks allocated for VRAM access by the post-t-CPU 1, and reads data to VRAM3. In this case, the data output to the VRAM bus 9 is received via the bidirectional buffer 10 and the data bus 8. In this embodiment, the host CPU 1 and the display control circuit 2 operate synchronously. Therefore, there is no latch for latching data on the VRAM bus 9 (read data can be reliably captured).

(Effects of the Invention) According to the present invention, there is no need for a latch to temporarily latch read data from a storage device for storing display data, and the circuit configuration related to the bus is simpler than before. Provided is an electronic computer capable of reducing costs. According to the present invention, a clock generator for generating a clock signal for the display control circuit is not required, and the circuit configuration of the electronic computer is simplified.
Costs are reduced. Furthermore, in the electronic computer of the present invention, C
Since the PU and display control circuit operate synchronously, the number of wait states of the CPU when accessing VRAM is optimized compared to conventional electronic computers, and as a result, writing and reading from VRAM by the cPU is faster than before will be faster than.

Earth-E-plane ρJ It is a diagram.

DESCRIPTION OF SYMBOLS 1... Host CPU (central processing unit), 2... Display control circuit, 3... VRAM (display storage means), 4... Display device, 5... Crystal, 6... Multiplexer (Multiplexing means).

that's all

Claims (1)

[Claims] 1. A central processing unit that operates based on a clock signal from a clock generator, a display control unit that operates based on the clock signal, and at least a device for data transfer to the central processing unit and the display control unit. a display storage means connected via a signal line, and a display device for selectively providing an address from the central processing unit and an address from the display control means to the storage means under control of the display control means; An electronic computer equipped with multiplexing means.