JPH0462182B2 - - Google Patents

Description

[Detailed Description of the Invention] (Technical Field) This invention utilizes a light-emitting light-receiving transistor,
The present invention relates to a light emitting device that combines an integrated shift register and a load light emitting device.

(Prior art) A conventional integrated light emitting device consists of a light emitting diode array using a compound semiconductor and a single semiconductor to drive it.
It used an integrated circuit using Si and a drive circuit, and its configuration was such that it was integrated by combining different types of integrated devices.

Therefore, manufacturing requires complexity and precision machining, is expensive, and has somewhat poor controllability.

(Objective of the Invention) It is an object of the present invention to provide a light emitting device that eliminates these drawbacks, can be easily configured, and can be easily controlled by external signals.

(Structure of the Invention) The light emitting device of the present invention configures a bistable circuit using a light emitting light receiving transistor and a diode that determines the direction of a trigger signal, and connects a load light emitting light receiving transistor to this bistable circuit to form a bistable circuit. This basic cell is connected in multiple stages, and at a time specified by an external control signal, a load light emitting/receiving transistor driven by a bistable circuit is excited to a specified intensity to emit light. −
A light-emitting and light-emitting transistor, a diode, and a load light-emitting and light-receiving transistor are formed into the same device structure by epitaxial growth on the same substrate made of a group compound semiconductor.

(Example) Hereinafter, an example of the light emitting device of the present invention will be described based on the drawings. FIG. 1 is a schematic diagram of the first embodiment. Its configuration includes both electrical and optical elements.

In the figure, Q1 to Q5 are light-emitting and light-receiving transistors, which are made of compound semiconductors such as GaAs, AlGaAs,
It is made of - group compound semiconductors such as InP and InGaAsP.

Electrically, these light-emitting and receiving transistors Q1 to Q5 have a current amplification function similar to that of a normal bipolar transistor, and optically, they have a photoelectric conversion function with light-receiving sensitivity over a wide wavelength range. This is a transistor with a current-light conversion function that emits light in a narrow wavelength range. Furthermore, when a large current is applied, laser light may be emitted near the base region.

The electric circuit shown in FIG. 1 is constructed using a flip-flop circuit and a load transistor as basic cells. Therefore, there are some electrical variations of this circuit that are customary. A and C are high potential bias terminals on the collector side, and B is a low potential bias terminal on the emitter side.

X1 and X2 are signal input terminals for making each stage of the flip-flop sequentially correspond to one of the two states corresponding to logic "1" and "0", and X3 is a signal input terminal for this flip-flop circuit system. Clock signal terminal common to each stage for control,
4 is a light emitting/receiving transistor Q as a load in each stage.
This is a control terminal for controlling 5 and Q4 to an appropriate operating state at an appropriate time and causing them to emit light.

R1 to R11 are electrical resistors and are used to determine the electrical and optical operating conditions of the light emitting and receiving transistors Q1 to Q5 together with the drive signal line.

C1 to C2 constitute a differential circuit together with resistors R2, R6, R1, and R5, and a light emitting/receiving transistor Q
This is a capacitor for applying a trigger signal to the base of Q2.

Capacitors C3 and C4 are additional capacitors for improving the high frequency characteristics of the pulse of the flip-flop circuit, but are not essential.

D1 and D2 are diodes for limiting the potential direction of the trigger signal. L1 and L2 are light guide paths (or fibers) for guiding the light emitted from the light emitting and receiving transistors Q4 and Q5 as loads to the outside, and are made of, for example, optical glass or transparent resin.

Furthermore, circuit modifications in which other resistors, capacitors, diodes, and transistors are added are omitted for the sake of simplicity.

E is a light shielding part for optically and electrically insulating and separating the light emitting/receiving transistors Q1 to Q5 and the diodes D1 and D2 and the outside from them; for example,
It can be composed of an insulating material such as black resin, powder, solid, or liquid.

Light-emitting and light-receiving transistor Q forming a bistable circuit
1 and Q2 are connected to signal input terminals X1 and X2 via diodes D1 and D2, respectively. Capacitors C1 and C2 are connected in series between the signal input terminals X1 and X2. The connection point between capacitors C1 and C2 is connected to clock signal terminal X3. The bases of the light emitting and receiving transistors Q1 and Q2 are connected to a low potential bias terminal B via resistors R3 and R4, respectively.

The collectors of the light emitting and receiving transistors Q1 and Q2 are connected to a high potential bias terminal A on the collector side via resistors R5 and R6.

The collector of the light emitting and receiving transistor Q1 is connected to the base of the light emitting and receiving transistor Q2 through a parallel circuit of a resistor R1 and a capacitor C3, and is also connected to the base of the light emitting and receiving transistor Q3.

Similarly, the collector of the light emitting and receiving transistor Q2 is connected to the base of the light emitting and receiving transistor Q1 via a parallel circuit of a resistor R2 and a capacitor C4.
connected to the base of.

The emitter of the light emitting/receiving transistor Q3 is a resistor R.
7 to the emitter side bias terminal B, and a light emitting/receiving transistor (Q2
compatible) is connected to the base.

The collector of the light emitting/receiving transistor Q3 is connected to the high potential bias terminal A.

The collector of the light emitting and receiving transistor Q4 is connected to the high potential bias terminal C, and its emitter is connected to the collector of the light emitting and receiving transistor Q5, and also connected to the light emitting and receiving transistor of the next stage bistable circuit ( (corresponds to Q1)
connected to the base of.

The base of the light emitting/receiving transistor Q5 is a resistor R9.
It is connected to the control terminal X4 through the resistor R8, and its emitter is connected to the low potential bias terminal B through the resistor R8.

A light guide path L1 faces the bases of the light emitting and receiving transistors Q4 and Q5.

Next, the operation of the light emitting device of the present invention configured as above will be explained. FIG. 2 is an example of control signals for driving the circuit of FIG. 1 shown in time series. In this example, the potentials of the high potential bias terminals A and C on the collector side of the light emitting/receiving transistor and the low electron bias terminal B on the emitter side are not shown as being fixed at direct current.

Figure 2a and Figure 2b are respectively signal input terminals
2c shows the clock signal applied to the clock signal terminal X3, and FIG. 2d shows the control signal applied to the control terminal X4.

It is now assumed that the light-emitting transistor Q1 is on, the light-emitting transistor Q2 is off, and is in a logic "1" state, and the next stage is in the opposite state, "0".

The signal input terminal X1 is normally at a low potential, as shown in Figure 2a, and the signal input terminal
As shown in FIG. 2, when the transistor Q1 is at a high potential and a negative clock pulse is applied to the clock signal terminal X3, the light emitting/receiving transistor Q1 is in the OFF state, and the light emitting/receiving transistor Q2 is in the ON state, thus becoming in the "0" state.

Therefore, the light emitting and receiving transistor Q3 changes from an off state to an on state, and the light emitting and receiving transistor Q4 changes from an on state to an off state.

As a result, the next stage light-emitting/receiving transistor Q
The gate line potential connected to the base of the transistor corresponding to 1 and Q2 is the opposite of this,
Therefore, when the clock pulse of the clock signal terminal X3 is applied, the light emitting and receiving transistor Q
The next-stage light-emitting/receiving transistor corresponding to Q1 changes from the on state to the off-state, and the next-stage light-emitting/receiving transistor corresponding to the light-emitting/receiving transistor Q1 changes from the off to the on state, thus changing from the "0" state to the "1" state.

As a result, the next-stage light emitting and receiving transistor corresponding to the light emitting and receiving transistor Q4 changes from off to on. Therefore, the state of the first stage has moved to the second stage.

Similar state transitions are performed in the second and third stages in the above operation, but since the second stage was in the "0" state, the "0" state is transferred to the third stage. This shift register operation may be performed in any number of stages.

Next, the light emitting and receiving transistor Q4 as a load
is in the on state, the control terminal X4 is normally kept at a relatively low potential of X40 as shown in FIG. state, and when necessary, apply a high potential in synchronization with the clock pulse as appropriate.
Creates a highly conductive state and a highly luminous state.

By driving in this way, the "1" state moves to the right one section at a time by repeating the synchronization signal, and the emitted light is extracted from the light guide paths L1, L2, etc. as strong or weak light emission at the appropriate stage. , it is possible to convert a time-sequential light emission pattern into a temporal and spatial sequence light-emission pattern.

In addition, in order to convert the first stage from "0" to "1", the signal input terminal X1 is set to a high potential, the signal input terminal This can be achieved by turning on.

Furthermore, the emitted light is emitted by a light emitting/receiving transistor Q4,
It may be taken out from either one or both of Q5. Then, the high potential bias terminal C is connected to the control terminal
By using it instead of 4, the control terminal
It is also possible to remove the line connected to the light emitting/receiving transistor Q5.

Further, after connecting N stages, the same pattern can be repeated by returning the output terminals to the signal input terminals X1 and X2.

FIG. 3 shows a cross-sectional view of an embodiment of a specific construction method corresponding to the schematic diagram of FIG. 1. In this configuration example, the resistors R1 to R11 are not shown as external connections, but they are connected inside the semiconductor substrate 19 or in the upper layers 11 to 26 shown in FIG. 3 using impurity diffusion or ion implantation. Can be configured within a single substrate.

In addition, since any equivalent resistance other than a pure resistor is sufficient, it is also possible to use a transistor or diode instead, but since this is not an essential requirement, specific examples will not be detailed for the sake of brevity. I omitted it.

Further, the light emitting/receiving transistors Q1, Q3 and the diodes D1, D2 have similar structures, and the semiconductor substrate 1
9, illustration thereof is omitted.

In the figure, compound semiconductor layers 11 to 26 constitute light emitting/receiving transistors. The insulating compound semiconductor substrate 19 is made of, for example, GaAs or InP, and the light emitting/receiving transistors Q1 to Q5 are formed on it.
and diodes D1 and D2 are simultaneously constructed on a single substrate. Below, light emitting light receiving transistor Q
1, Q3, and diodes D1 and D2 will be omitted.

Compound semiconductor layers 14, 18, 23 constituting the collector portions of the light emitting/receiving transistors Q2, Q4, Q5 are formed on the semiconductor substrate 19, and compound semiconductor layers 13, 17, 22 forming the base portions and emitter portions are further formed on the semiconductor substrate 19. Compound semiconductor layers 12, 16, 2
1. Epitaxially grow compound semiconductor layers 11, 15, and 20 as contact layers to enable good ohmic connection of the emitter electrodes.

Next, the same P as the base layer to take out the base electrode from the top (n in the case of a pnp transistor)
A modified layer 24 of a compound semiconductor layer in which a type of impurity is modified using a diffusion method or an ion implantation method,
Compound semiconductor 1 with 25 and 26 as base layers
Form up to 3, 17, and 22.

After that, a part of the emitter section is removed by chemical or physical mesa etching, or the emitter section is insulated using ion implantation.
Partial insulation between the bases and light emitting parts 27 and 28 to the base layer are formed.

Therefore, this part may be simply a vacuum or gas, but it is preferably made of resin or other material that is transparent at each wavelength of input and output light and has a refractive index as close as possible to that of a semiconductor or light guide (fiber). It is composed of liquid or fixed material.

After that, the light emitting and receiving transistors Q2, Q4, Q
Etching is performed to provide a collector electrode No. 5, and etching is performed to electrically insulate the light emitting and receiving transistors Q2, Q4, and Q5 from each other. Thereafter, ohmic electrodes for each layer are added using a vapor deposition method, a plating method, a sintering method, or the like.

In general, it is desirable that the compound semiconductor layers 12, 16, 21 as emitter layers have a larger energy gap than the compound semiconductor layers 13, 17, 22 as base layers, thereby reducing the fractional carriers from the emitters. Injection efficiency can be improved.

For example, a compound semiconductor layer 1 as a base layer
When 3, 17, 22 are made of GaAs or InP, compound semiconductor layers 12, 1 as emitter layers
For example, AlGaAs or InGaAs is used for each of 6 and 21.

Moreover, if this is done at the same time, the emitter layer can be made optically transparent to the wavelength of light to be absorbed by the base layer, making it possible to further enhance the photoelectric conversion efficiency.

Although the compound semiconductor layers 11, 15, and 20 as emitter contact layers are essentially unnecessary, the compound semiconductor layers 12, 16, and 2 as emitter contact layers are essentially unnecessary.
It is used as an auxiliary layer when it is difficult to attach an ohmic electrode directly to the layer 1.

Compound semiconductor layers 13, 17 as base layers,
22 are generally made with the same composition at the same time, but if it is desired to variously change the wavelength characteristics of the output light, they are made to have different compositions.

This can be achieved, for example, by changing the composition of the base material crystal using selective epitaxial growth, or by selectively diffusing impurities after growing a crystal with the same composition or modifying it using ion implantation. be.

Also, this base layer is the light emitting/receiving transistor Q.
This layer has a particularly important effect on the electrical and optical properties of 2, Q4, and Q5, and particularly desirable properties are often obtained for - group compound semiconductors when group elements are used as impurities.

That is, characteristics such as a long minority carrier diffusion length and high conversion efficiency for light emission or light reception can be obtained.

The light-shielding portion E in the figure is made of the above-mentioned material for providing mutual optical and electrode insulation between the light emitting and receiving transistors Q2, Q4, Q5 and the light guide path L1.

This makes it possible to separate the outputs of each stage and to avoid malfunctions of the light-emitting and light-receiving transistors.

In addition, although the figure shows a structure in which all the light guide paths L1 are taken out from the top, it is also possible to attach them to the lower part of the semiconductor substrate 19, or in particular when emitting laser light, it is possible to take out the output in the lateral direction. It is desirable to install the light guide path L1.

In addition, although the light shielding part E is added only to the upper part of the semiconductor part, in order to achieve more complete optical shielding,
It is preferable to add it to the lower part and the lateral part as well.

FIG. 4 is a schematic diagram of a partially modified embodiment of the configuration example of FIG. 1. In this circuit configuration example, a signal from a shift register circuit based on a bistable circuit is applied to the base of the load light-emitting and light-receiving transistor Q5 to turn it on, and the current and light emission intensity of the light-emitting and light-receiving transistor Q5 are controlled by the control terminal X4. This allows modulation to be performed. Signal input terminal
1, X2, clock signal terminal X3, control terminal X4
Since the pulse signal series applied to is almost the same as in FIGS. 2a to 2d, details will be omitted.

However, since the normal state of the control terminal X4 is independent of the register circuit, the low potential level pulse of the on-state body X40 is unnecessary.

The emitter of the light emitting and receiving transistor Q4 is connected to the emitter of the light emitting and receiving transistor Q5 via a resistor R8, and is connected to the base of the light emitting and receiving transistor Q5 via a resistor R9. The collector of the light emitting/receiving transistor Q5 is connected to the control terminal X4 via a resistor R12.
The other configurations are the same as in FIG. 1.

As explained above, in this embodiment, the active elements of the light-emitting and light-receiving transistors have multi-functional characteristics in terms of electro-optics, so a large number of them can be constructed on the same substrate with a relatively simple circuit and simple configuration. be.

In addition, it has the advantage that electrical controllability can be easily obtained, and since it is an optical output signal,
It can operate electrically in a completely isolated state from other circuits, and has great advantages in its independence and controllability.

These devices can be connected in parallel or in series, and can be integrated in large numbers on the same plane.

In addition, although the above-mentioned embodiment shows only an example using an npn type light-emitting/light-receiving transistor, it is easily possible to implement a similar configuration with a pnp type, so the explanation is omitted.

(Effects of the Invention) As described above, according to the light emitting device of the present invention,
A bistable circuit is formed using light-emitting and light-receiving transistors, and basic cells connected to load light-emitting and light-receiving transistors of this bistable circuit are connected in multiple stages to provide a shift register circuit function, and the load light-emitting and light-receiving transistor is specified by an external control signal. Since the light is emitted at a predetermined intensity at a certain time, the shift register circuit and the load light emitting circuit can be formed on the same substrate.

Accordingly, a light emitting device with an optical spatial arrangement with good controllability can be obtained with a simple manufacturing method and an inexpensive structure, and can be applied to other optical sweep circuits, delay circuits, displays, and printing devices.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of the light emitting and receiving device of the present invention, and FIGS. 2a to 2d are diagrams each showing an example of a drive pulse time series applied to the light emitting and receiving device of the present invention, FIG. 3 is a cross-sectional view showing the structure of the main part of the light emitting and receiving device as described above, and FIG. 4 is a schematic diagram of the structure of another embodiment of the light emitting and receiving device of the present invention. Q1 to Q5... light emitting light receiving transistor, D1,
D2...Diode, R1-R11...Resistance, C
1 to C4... Capacitor, A, C... High potential side bias terminal, B... Low potential side bias terminal, X
1, X2...Signal input terminal, X3...Clock signal terminal, X4...Control terminal, L1, L2...Light guide path, E...Light blocking section, 11-26...Compound semiconductor layer, 24-26... Altered layer, 27, 28... light emitting part.

Claims (1)

[Scope of Claims] 1. First and second light-emitting and light-receiving transistors that turn on and off in opposite directions;
third and fourth light-emitting and light-emitting transistors whose bases are respectively connected to the high potential side when the light-emitting and light-receiving transistor is off, and anodes of which are respectively connected to the bases of the first and second light-emitting and light-receiving transistors, and the trigger signal is a bistable circuit having first and second diodes that limit the potential direction of the transistor; basic cells connected in multiple stages, each of which has a load light-emitting light-receiving transistor that turns on in response to input and generates output light with an intensity specified by the external control signal when turned on; a light-shielding portion for optically and electrically insulating and separating the first to fourth light emitting/receiving transistors, the first and second diodes, and each of the basic cells connected in multiple stages; - group compound; The first to fourth light-emitting and light-receiving transistors made of a − group compound, the load light-emitting and light-receiving transistor, and the first and second diodes are formed into the same device structure by epitaxial growth on the same substrate made of a semiconductor. A light emitting device.