JPH0461693A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To execute the page write to a large capacity EPROM by inputting a page write mode setting signal from an address signal or read-out/write control signal terminal, and using newly a part of a data pin as a signal input terminal. CONSTITUTION:When the device becomes a page write mode, a select gate 31 to which a data input/output terminal D8 is connected is closed by setting so that a control signal (a) becomes an L level, and the data input/output terminal D8 becomes a cut-off state. The connecting relation of input/output terminals of the remaining each memory array 21 and the select gate is also the same. That is, D8-D15 in the data input/output terminals D0-D15 become unnecessary, therefore, one piece of them is used as an address terminal A17, and other one piece is used newly as a -PGM signal terminal being one of read-out/write control signals. In such a way, the device of a large capacity whose write time is shortened is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device that can significantly shorten data write time.

[Conventional technology]

Data writing to a conventional semiconductor memory device will be explained with reference to FIG. In FIG. 3, l is a memory array constructed by arranging, for example, floating gate type memory transistors in the row and column directions, and 16 memory arrays 1 (MO to M15) are arranged to form a non-volatile memory. It consists of 2 is an address terminal, 3 is an address buffer, 4 is a row decoder, 5 is a column decoder, 6 is a column selection gate, 7 is a read/write control signal terminal, 8 is a read/write control circuit, and 9 is a data input/output buffer. be. 00 to D15 are a total of 16 data input/output terminals coupled to each input/output buffer.

Next, the operation of the semiconductor memory device shown in FIG. 3 will be explained.

First, when a certain address is input from address terminal 2,
The output of the 0 row decoder 4, whose row address component and column address component are supplied to the row decoder 4 and column decoder 5, respectively, is supplied to the memory array 1, and the output of the column decoder 5 is input to the column selection gate 6, which Accordingly, a memory transistor at a desired address in each memory array MO to M15 can be selected. In this way, each memory array M
Since the output of the same row decoder 4 and the output of the column selection gate 6 are inputted in parallel to O-M15, the same address of 16 memory arrays MO-M15 is simultaneously selected by one address specification.

Next, in order to read information from this nonvolatile memory, a read signal must be set to the read/write control signal terminal 7. For example, if we take a general-purpose EFROM, the CE shown in FIG.
=L, 0E=L, PGM=H, etc.), set to read mode. As described above, when a desired address signal is input from the address terminal 2, the memory transistor corresponding to the specified address is selected, passes through the column selection gate 6, is amplified by the data input/output buffer 9, and is input/output. It is output in parallel to terminals DO to D15.

To write information to this non-volatile memory.

Similarly, set a write signal to the read/write control signal terminal 7 (for example, CE=L, OE=H1PGM=H, etc.) to enter the write mode. Then, as in the case of reading, a desired address signal is input from the address terminal 2 to select the memory transistor, and the data input/output terminal DO
~ Desired information can be written into the memory transistor by inputting necessary data to D15 and further inputting a write signal (similarly a PGM pulse signal, etc.) from the read/write control signal terminal. .

Tpw shown in the L pulse portion of the PGM signal is called a write pulse.

Floating gate type memory transistors 50 constituting memory arrays MO to M15 are shown in FIG. 5. In the figure, 10 is a P-type semiconductor substrate, 11 is a source, 12 is a drain, 13 is a control gate, and 14 is a floating gate. be. In this floating gate type memory transistor 50, writing is performed by accumulating charges in the floating gate 14. In this case, before the information is written, the floating gate 14
There is no charge in the drain current (Io) vs. control gate voltage (Vc) characteristic as shown in curve A in FIG. An avalanche breakdown phenomenon occurs nearby, generating high-energy electrons and injecting them into the floating gate 14. Therefore, vl of the memory transistor 50
The J value increases, and the drain current (ID)-control gate voltage (VG) characteristic changes as shown by curve B in FIG. 6, and is held as written information. The high voltage applied to the drain 11 and control gate 14 during this write is applied as a pulse voltage synchronized with Tpw of the write pulse input PGM, so the threshold voltage (VMT) of the memory transistor 50 in FIG. 7 - cumulative applied pulse As shown in the @(Tp) characteristic, the threshold value changes in proportion to the cumulative pulse application width. In order to perform sufficient writing, a write pulse width of approximately several hundred 1Lsec to several tens of m5ec is normally required, and in the signal timing diagram shown in FIG. It turns out.

However, in conventional semiconductor memory devices, one memory transistor is 1 megabit, and the data structure is
In the case of 16 types, that is, the one with memory array MO-M15, one memory array l includes 65,536 bits of memory transistors, and 65,536 addresses are required to specify all of them. is necessary. Assuming that the pulse width required for writing is 1.0sec, and writing to all addresses, the time required for writing is 1.0m5ecX G5,5364
This is 65 seconds, but as the memory capacity becomes larger, the time required for writing becomes even longer. Methods to increase the number of data that can be written in parallel are difficult to implement because they are strongly constrained by the number of package pins, etc. For this reason, methods such as shortening the write pulse width by improving the physical characteristics of the memory transistor itself and , a method called the page write method has been considered.

Next, a semiconductor memory device employing a page write method will be described as a conventional example. FIG. 8 shows a block diagram of a semiconductor memory device configured based on the page write method. In the figure, parts indicated using the same reference numerals as in FIG. 3 represent the same or equivalent parts. In the figure, reference numerals 1a to 1d indicate memory arrays in which floating gate type memory transistors, such as those shown in FIG. A configuration corresponding to the memory array 1 in FIG. 3 is assumed. Gates 6a to 6d are provided corresponding to the memory arrays 1a to 1d, and are column selection gates having a function of latching data to be written to the memory transistors in each memory array. 1
A bus 5 transmits information read from the memory transistors in each memory array 1 to the input/output buffer 9.

The memory blocks 20, 20, . . . in FIG.

Next, the operation of the semiconductor memory device employing the page write method shown in FIG. 8 will be explained. The method of selecting and reading a desired memory cell is the same as in the conventional semiconductor memory device shown in FIG. That is, when selecting a desired memory cell, a certain address is supplied to address terminal 2,
The row address component is supplied to the memory array l via the row decoder 4, and the column address component is input to the column selection gates 6a to 6d via the column decoder 5. Thereby, a memory transistor at a desired address of memory array l in each memory block 20 can be selected.

When reading information from memory transistors, read/write
A read signal is set to the write control signal terminal 7 to set the read mode. Then, as described above, when a desired address signal is input from the address terminal 2, the memory transistor corresponding to the specified address is selected, and the read information is supplied to the data input/output buffer 9 via the column selection gates 6a to 6d. The data is appropriately amplified by the data input/output buffer 9 and output in parallel to the data input/output terminal Do-015.

To perform page writing, a signal is set to the read/write control signal terminal 7, and a part of the address signal (usually a part of the column address is often used) is used to select the column selection gates) 6a to 6d. Make it work. Further, an address signal for selecting a desired memory transistor is input from address terminal 2, and data input/output terminals DO~0
15, and a signal for data latching is inputted from the read/write control signal terminal 7 to cause the column selection gates 6a to 6d to latch the write data in sequence. FIG. 9 shows the timing of each of the above-mentioned signals. In the same figure, the address signal (AOlAI) and the read/write control signals (CE, OE, PGM)
DATAO (=input signal from data input/output terminal DO)
By generating the L pulse of OE in the figure in the four states of the address signal (AO, AI) (latch 1 to latch 4), which represents the state in which the address signals (AO, AI) are latched to the column selection gates 6a to 6d, The data (Dl, D2, D3.D4) input to DATAO is sent to the column selection gate (6
a to 6d), and write the PGM write pulse Tp.
By applying w, memory arrays 1a-1d in FIG.
In this case, data is simultaneously written into one memory transistor for each memory transistor, that is, a total of four memory transistors. Needless to say, at this time, writing is also performed simultaneously on the remaining memory arrays corresponding to the data input/output terminals D1 to D15.

With this page write mode, the conventional 1 megapix) E
In PROM (X16 type), approximately 65
sec [Problem to be Solved by the Invention] However, due to the limitation on the number of terminals due to the package mentioned above, even larger capacity semiconductor memory devices (for example, 4
(Megapits) EFROM, etc.), a problem has arisen in that page writing cannot be performed. The reason for this will be explained using FIG. 10 as an example. Figure 10 shows examples of 1 megabit, 2 megabit, and 4 megabit EFROMs, all of which are housed in packages with 40 terminals (all data configurations are X16 type). As is clear, in 1 megabit and 2 megabit EFROM,
Since a terminal for the PGM signal, which is one of the read/write control signals, can be used, page writing is possible. However, since a 4-megabyte EFROM requires a terminal for the address A17, the terminal for the PGM signal mentioned above can be used. Therefore, using the assumptions shown in the conventional example, the write time is 1, Om5ec The time required to write all bits is approximately 260 seconds (= 4 x 65 seconds
), which is a big problem from the viewpoint of productivity, ease of use, etc.

This invention was made to solve the above-mentioned problems, and its purpose is to shorten the write time of a large capacity semiconductor memory device.

[Means to solve the problem]

The semiconductor memory device according to the present invention inputs a page write mode setting signal from either the address signal or the read/write control signal terminal, and connects some of the data pins to the address or read/write control signal input terminal. By newly using it as a memory card, page writing to a large capacity EFROM can be realized.

A large-capacity semiconductor memory device with shortened write time can be obtained while maintaining the same number of terminals.

〔Example〕

Hereinafter, the semiconductor memory device of the present invention will be described with reference to FIG. 1, including its page write mode setting method and data input method. In Figure 1.

Portions using the same reference numerals as those in the conventional semiconductor memory device shown in FIG. 3 or FIG. 8 represent the same or equivalent portions.

In the figure, 21, 21, . . . are memory arrays, and each memory array includes memory blocks 20a and 20b. Each memory array 21 has data input/output terminals Do, D8; Di, D9 . Three select gates 31 are provided for transmitting or blocking data input from D7 and D15 to the memory blocks 20a and 20b. The select gate 31 receives control signals a, which are supplied to each of these select gates 31,
Conductive when b and c are at H level and cut off when they are at L level. 32 and 33 are paths for transmitting read data of each memory block. 34 shows an example of a logic circuit necessary for data input control, and 35 shows the above-mentioned AI? This is a page write mode setting signal generation circuit using signals.

Next, the operation of the semiconductor memory device shown in FIG. 1 will be explained.

The method of selecting and reading a desired memory cell in each memory array 21 is the same as in the conventional semiconductor memory device shown in FIG. The row address component is supplied to each memory block 20a, 20b of the memory array 21 via the row decoder 4, and the column address component is supplied via the column decoder 5 to gates similar to column select gates 6a to 6d in FIG. (not shown). Thereby, a memory transistor at a desired address in each memory block 20a, 2Ob can be selected.

When reading information from memory transistors, read/write
A read signal is set to the write control signal terminal 7 to set the read mode. As described above, when a desired address signal is input from the address terminal 2, the memory transistor corresponding to the specified address is selected, and the read information is transferred to the column selection gates 6a to 6d in FIG. Data output buffer and data input/output terminals DO, D8; Di, D9;
It is output in parallel to D7.015.

In the semiconductor memory device shown in FIG. 1, in order to perform page writing, for example, one of the address terminals 2 (
In this example, by applying a high voltage page write mode switching signal to the address terminal A17) in FIG. 1O, the page write mode setting signal generation circuit 35 generates the H level page write mode setting signal Pa. This page write mode setting signal PI is read/write control circuit 8
By inputting this, the semiconductor memory device enters the page write mode.

When the semiconductor memory device shown in FIG. 1 enters the page write mode, if the control signal a is set to the L level, the select gate 31 to which the data input/output terminal D8 is connected is closed, and the data input/output terminal D8 is closed. becomes blocked. Since the connections between the input/output terminals and the select gates of the remaining memory arrays 21 are the same, when the control signal a becomes L level, the select gates to which the data input/output terminals D9 to D15 are connected are also closed. These data input/output terminals D9 to DI5 are cut off. In other words.

D8~ of the 16 data input/output terminals Do-D15
D15 becomes unnecessary. Therefore, one of these eight data input/output terminals D8 to D15 is connected to the address terminal AI?
As an example of using one terminal as a terminal and the other one as a PGM signal terminal, which is one of the read/write control signals, as shown in Figure 1, data input/output terminal D8 is connected to address A17 terminal. The data input/output terminal D9 is used as a PGM terminal. This allows the use of the same 40-terminal device as before.

Address signal terminals for AO-A17, data input/output terminals for DO to D7, read/write control signal terminals for CE, OE, and PGM, and power supply system terminals are obtained. This makes it possible to input an address according to the memory capacity and a control signal according to page write control.

FIG. 2(a) and FIG. 2(b) show the control signals a, b, c, the memory block 20a on the data input/output terminal DO side, the data Memory block 2 on the input/output terminal D8 side
As shown in Fig. 2(a), when the page write mode is not set, the data input/output to/from 0b is shown.
If control signal a is set to H level and control signals S and C are set to L level, memory blocks 20a of each memory array 21,
Data can be input or output using the data input/output terminal Do-D15 corresponding to 20b. On the other hand, in the page write mode, as shown in FIG. 2(b), the control signal a is set to L level, and the control signals S and C are combined with the address signals AO, At and the control signal OE. (If a signal system similar to that shown in FIG. 9 is used, logically b=OE・AO, C=OEφAO). By using these signals, two in each memory array 21 Data can be input alternately to the memory blocks 20a and 20b. Furthermore, inside the memory block 20a or 20b, a conventional latching operation of write data during page write may be performed, and the contents of the internal circuit and page write control circuit 8 are the same as the conventional semiconductor memory device shown in FIG. Things can be used.

For example, the page write mode setting signal generation circuit 35 used in the semiconductor memory device of the present invention shown in FIG.
A structure as shown in Fig. 1 is used. In the same figure, 4
0 is the address A17 input terminal, 41 is, for example, 5. Ov power supply terminal, 42 is P channel transistor, 43 is N
Channel transistor, 44 is ground, 45 is P channel transistor 46 and N channel transistor 47
This is an inverter circuit consisting of.

In the circuit of FIG. 11, the voltage V2 of the page write mode switching signal Vl11 applied to the address A17 input terminal 40
becomes equal to or greater than the sum of the power supply voltage V+ (for example, 5.OV) supplied to the power supply terminal 41 and the threshold voltage Vl11 of the P-channel transistor 42 (that is, VIN>
5. OV+Vth), the P channel +7 channel transistor 42 is turned on and the output is V. ut becomes H level. Output Vo
uL is supplied to the control circuit 8 of FIG. 1 as a page write mode detection signal Pg.

〔Effect of the invention〕

As described above, according to the semiconductor memory device of the present invention, the 4 megapixel EFROM used in the embodiment conventionally required approximately 260 seconds to write, but by realizing page writing, this In the above example, it is possible to write to four addresses at the same time by applying one write pulse, so that all addresses can be written. This greatly improves both productivity and ease of use.

Note that in the above embodiment, the data input/output terminals DO to DI
5, the data length was changed from 16 bits to 8 bits, but the combination method is not limited to this. Also, in the embodiment, four addresses can be written simultaneously by applying one write pulse. Although the structure is configured to allow writing, the method of page launch and the number of addresses to be latched at the same time are not limited to this, and can be changed. As for the page write mode fast signal generation circuit 35, any configuration other than the embodiment shown in FIG. 11 can be used. Furthermore, although the description has been made assuming that a floating gate type transistor is used as the memory, the present invention can produce similar effects even if the memory has a different structure.

As described above, the circuit configuration is such that page writing can be performed even in a semiconductor memory device in which page writing is not possible due to packaging restrictions, so that the writing time can be significantly shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a semiconductor memory device according to the present invention, and FIGS.
3 is a block diagram illustrating an example of a conventional semiconductor memory device, and FIG. 5 is a schematic cross-sectional view illustrating the structure of a floating gate type memory transistor forming a memory array; FIGS. 6 and 7 are timing diagrams of control signals to explain the operation of a semiconductor memory device; FIGS. 8 is a block diagram showing an example of a conventional semiconductor memory device that can operate in page write mode. FIG. 9 is a diagram illustrating the operation of the semiconductor memory device of FIG. 8. FIG. 10 is a terminal arrangement diagram of a 40-pin package, and FIG. 11 is an example of a page write mode setting signal generation circuit used in the semiconductor memory device of the present invention shown in FIG. 1. The circuit diagram shown in FIG. 12 is an operation characteristic diagram illustrating the operation of the page write mode setting signal generation circuit of FIG. 11. 2... Address terminal, 7... Read/write control signal terminal, 20a, 20b... Memory block, 21... Memory array, 31... Select gate, 32°33. ...Bus, 34...Logic gate, DOND15...Data input/output terminal. Deputy Jindai Iwa Masu Yuyumi, 0 Kufuguchienshikabuto] 0th NC: No Comecion Procedural amendment (voluntary)

Claims (1)

[Claims] (1) In a semiconductor memory device in which, by specifying an address, information at the specified address can be read in parallel from a plurality of memory blocks constituted by a plurality of memory transistor groups, and information can be written in parallel from the outside, a plurality of signal input terminals including an address terminal and a read/write control signal terminal; a plurality of data input/output terminals coupled to each of the plurality of memory blocks; and a signal of any one of the plurality of signal input terminals. A page write mode setting signal generation circuit generates a page write mode setting signal in response to a page write mode switching signal supplied to an input terminal, and when the page write mode setting signal is generated, the plurality of data input/output terminals are A circuit that cuts off inputs other than the necessary number and at the same time forms another signal input bus for the cut off data input/output terminals, and the necessary number of data input/output terminals and all the memory transistor groups mentioned above. In the page write mode, a plurality of independent write circuits are provided in order to write to a plurality of memory transistor groups in the same memory block. 1. A semiconductor memory device characterized in that a plurality of data can be simultaneously written into a plurality of memory transistor groups in the same memory block.