JPH0461578A - Video printer - Google Patents

Abstract

PURPOSE:To simplify and reduce the printer circuit and to reduce the cost by using one ROM for control program storage and for video signal conversion in common and using one RAM for CPU processing and for video signal conversion and using a same gate array for a print control section, a memory control section and a CPU control section. CONSTITUTION:One common ROM 10 is used for a ROM for CPU control program and a ROM for video signal conversion lookup table, a common RAM 12 is used for a RAM for CPU processing and a RAM storing a data during video signal conversion. Moreover, one gate array 14 is used for controlling a picture memory 118, a CPU 100 and a printer mechanism section 140. Furthermore, a changeover switch 20 and an address selector circuit 16 are provided to use terminal pins for address output and video signal output for the ROM 10 and the RAM 12 in common and then the entire printer circuit is made small.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video printer device, and particularly to a circuit configuration of a signal processing system.

[Prior Art] Recent video printers use control circuits for writing and reading input video signals into image memory, control circuits for converting video signals read from image memory into video signals suitable for printing, etc. is composed of a gate array (G/A).

FIG. 2 shows the circuit configuration of a recent video printer. As shown in the figure, a system bus 102 extending from a CPU (central processing AFI 100) is connected to a memory control unit 110, a CPU
A U control unit 1201 is connected to a print control unit 130, and gate arrays 112 and 122 are connected to each of these control units.
．． 132 are included.

In memory IIJII#110, video input terminal 10
An analog video signal input from the outside (television receiver, VTR, etc.) through 4 is converted into a digital video signal by an A/D converter 114, and then written into an image memory 118 by a memory control gate array 112. The digital video signal for one frame stored in the image memory 118 is read out from the image memory 118 by the memory control gate array 112 for video display or printout, and then converted into an analog video signal by the D/A converter 116. After conversion, it is sent to a display device (not shown) via the video output terminal 106, or once passed to the CPU 100, and then sent from the CPU 100 to the print control gate array 132 of the print control unit 130 via the system bus 102. Sent.

In the print control unit 130, when the gate array 132 receives the video signal from the image memory 118 as described above, the gate array 132 performs a look-up Φ stored in the video signal conversion ROM (read-only memory) 134. Using a table, the video signal (for example, an RGB video signal) is converted into a video signal suitable for printing (for example, a YMC video signal). During this conversion, the video signal is processed line by line, so the RAM (
Random access memory) 136 is used as a data (video signal) buffer. The video signal after conversion is
The gate array 132 sends the print data to the printer mechanism section 140.

In the mechanism section 140, a head, a scanning mechanism, etc. operate to record an image on paper.

In the CPU control unit 120, the gate array 122
It inputs a control signal from a keyboard (not shown) or the like, converts it into a code signal that can be read by the CPU, and transfers the food signal to the CPU 100. ROM12B is CP
U100(7) Stores a control program for specifying execution processing, and RAM 124 stores data processed by the CPU 100.

[Problems to be Solved by the Invention] As described above, in the conventional video printer, separate ROMs 126.
Separate RAMs 124 and 136 were provided respectively for Celtic memory, CPU processing, and video signal conversion. However, such a dual memory configuration increases the size and cost of the device circuit. Also, a memory control unit 110, a CPU control unit 120, a print control unit 130
gate array 12 for each control section. I22.
132, this also led to further increase in scale and cost of the circuit device.

The present invention was made in view of such problems, and the RO
A video printer device that achieves significant simplification, downsizing, and cost reduction of the device circuit by minimizing the number of memories such as M, RAM, etc., and also minimizing the number of gate arrays used. The purpose is to provide.

[Means for Solving the Problems] In order to achieve the above object, the video printer device of the present invention combines a control program used by a CPU and a look-up table for video signal conversion used by a print control unit. A ROM that is stored together, a RAM that stores data processed by the CPU, and data processed by the print control unit during video signal conversion, and these ROMs.
and a control means for switching memory access of the CPtJ and print control unit to each of the RAMs.

Furthermore, in order to simplify, downsize, and reduce the cost of the control section, the print control section is provided in the same gate array together with the control section for the image memory and the control section for the CPU.

In addition, in order to realize further miniaturization of the gate array and further miniaturization of the device circuit, addresses from the CPU and addresses from the print control section can be selectively transferred to ROM or RA.
The control means includes an address selector means for supplying the address to the video input terminal, and a changeover switch means for selectively sending the video signal inputted from the video input terminal or the video signal read from the image memory to the video output terminal. The configuration is such that address signals for the ROM and RAM of the array and video signals for the video output terminal are output from a common terminal pin.

[Operation] In the present invention, R for the control program is stored in one ROM.
The OM and the ROM for the look-up table for video signal conversion are used together, and one RAM is used also as the work RAM of the CPU and the panzer memory (RAM) for video signal conversion. Due to the function of the control means, these shared ROM and shared RAM generally receive memory access from the print control unit only during video signal conversion, and at other times
Receives PU memory access. Although the CPU is in a standby state while the print section accesses the memory, the processing time for video signal conversion is short, so the throughput of the CPU does not decrease much.

In this way, in addition to sharing ROM and RAM, by configuring the print control unit, image memory control unit, and CPU control unit in the same gate array, the number of gate arrays used is significantly reduced. do.

Further, an address selector means is interposed between the shared gate array and the ROM and RAM, and a changeover switch means is interposed between the video input terminal and the gate array and the video output terminal, so that the shared terminal pin ROM,
By selectively outputting the address signal to the RAM and the video signal to the video output terminal, and by extension the video signal to the display, the number of terminal pins of the gate array is reduced.
The gate array pancage becomes smaller.

[Embodiment] FIG. 1 shows the circuit configuration of the main part of a video printing/displaying device according to an embodiment of the present invention. In the figure, a CPU 100, a system bus 102, a video input terminal 14, a video output terminal 10
6. A/D converter 114 The D/A converter 116, the image memory 118, and the printer mechanism section 140 have the same configuration and functions as each section with the same reference numeral in FIG. 2 (conventional device). May be attached.

In this embodiment, the ROM10 stores a control program that defines the processing executed by the CPU 100, and also stores a look-up table for converting video signals during printing. The data terminal of ROMl0 is connected to the gate array 14 via the data bus 18.
It is also connected to the CPU 100 via a data bus 18.7 and a stem bus 102. Such RO
The CPU 100 and the /stem control gate array 14 selectively perform memory access to M10 via the address selector circuit 16. That is, CPU10
0 outputs a control program from the ROM 10 to proceed with its own operation or processing, and the gate array 14 outputs a video signal (for example, an RGB video signal suitable for printing).
For example, when converting to YMC system), a conversion look-up table in the ROM 10 is used.

Similarly to the ROM10, the address terminal of the RAM12 is connected to the address selector circuit 1 via the address bus 20.
6, and its data terminal is connected to the gate array 14 and the CPU 100 via a data bus 18. The CPU 100 and the gate array 14 also selectively access the RAM 12 via the address selector circuit 16. In other words, the CPU
Reference numeral 100 uses the RAM 12 as a work RAM, and gate array 14 uses the RAM 12 as a buffer during video signal conversion.

The selector circuit 16 is controlled by a selection control signal SE from the gate array 14, and the gate array 14 is controlled by a selection control signal SE from the gate array 14 in the ROM10 for video signal conversion.

Gate array 1 only when using the up table
At other times, it switches to the CPU 100 side. When using the memory 10.12, the gate array 14 sends a standby signal WAIT to the CPU 100.
send. As a result, the ROM10. of the CPU 100. R
Memory access to AM12 will be prohibited. However, since the time spent on video signal conversion is short, the processing efficiency of the CPU 100 is not significantly impaired.

The gate array 14 controls writing and reading video signals to and from the image memory 118 (memory control), controls the CPU 100 in response to user operations from a keyboard, etc. (CPU control), and performs the above-mentioned operations during printing. It is a one-chip circuit that performs all the functions of controlling the printer mechanism (printing control) as well as video signal conversion.

In this gate array 14, when the video signal read from the image memory 118 is sent to the video output terminal 106 for display, the video signal is sent from the same terminal pin that outputs the address signal to the address selector circuit 16. Output. At this time, the selector switch 20 is set to terminal 2.
Since the switch is switched to the Ob side, the analog video signal obtained from the D/A converter 116 is sent to the video output terminal 106 through this switch 20. Note that the address selector circuit 16 has been switched to the CPU 100 side at this time.

The changeover switch 20 is controlled by a changeover control signal SW from the gate array 14, and when displaying the video signal from the image memory 118 (memory image video signal) on the display, it switches to the terminal 20 b II, and the video input terminal 104 When displaying the input video signal (source picture video signal) on the display, it is switched to the terminal 2Oa side.

As described above, in this embodiment, one shared ROM 10 is used as the ROM that stores the CPU control program and the ROM that stores the look-up table for video signal conversion, and the RA that stores data for CPU processing
Since one shared RAM 12 is used as the RAM for storing M and data during video signal conversion, the number of ROMs and RAMs used is halved compared to the conventional device t (Fig. 2). The configuration is significantly smaller and simpler, and the equipment cost is also significantly lower.

In addition, since one gate array 14 controls the image memory 118, the CPU 100, and the printer mechanism 40, the number of gate arrays used is 1/3 that of the conventional device (FIG. 2). The circuit configuration has become smaller and simpler, and the equipment cost has also become lower.

Furthermore, by providing the changeover switch 20 and the address selector circuit 6, it is possible to share the terminal pin for address output to the ROM10°RAM 12 and the terminal pin for outputting the video signal to the display. The size is becoming smaller, and thus the volume of the entire device circuit is becoming smaller.

[Effects of the Invention] The present invention achieves the following effects by incorporating the above-described configuration.

According to the video printer device of claim 1, a ROM for storing a control program and a look-up memory for video signal conversion are provided.
One ROM is used as the ROM that stores the table,
One RAM is used for both the CPU's work RAM and the buffer memory (RAM) for video signal conversion, which reduces the number of ROM and RAM used, making the device circuit smaller, simpler, and lower in cost. It can be realized.

According to the video printer device of the second aspect, in connection with the above-mentioned dual use (common use) of ROM and RAM, the print control section is integrated with the control section for the image memory and the control section for the CPU in the same gate array. By configuring the device within the same area, it is possible to significantly reduce the number of gate arrays used and further promote miniaturization, simplification, and reduction in load of the device circuit.

According to the video printer device of claim 3, address selector means is interposed between the gate array and the ROM and RAM, and a changeover switch means is provided between the video input terminal and the gate array and the video output terminal. By interposing the address signal for the ROM and RAM and the video signal for the video output terminal and eventually the display from the common terminal pin, the video signal is selectively output.
The number of terminal pins of the gate array can be reduced, the gate array package can be made smaller, and the device circuit can be further miniaturized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the circuit configuration of the main parts of a video printer according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the circuit structure of the main parts of a conventional video printer. In the drawings, 10...ROM1 12...RAM. 14... System control gate array, 16...
Address selector circuit, 20... changeover switch, 100=...-CPU. 104...Video input terminal, 106...Video output terminal, 140...Printer mechanism section.

Claims (3)

[Claims] (1) A ROM that stores together a control program used by the CPU and a look-up table for video signal conversion used by the print control unit; a RAM that stores data processed by the print control unit; and a CPU for each of the ROM and the RAM.
and a control means for switching memory access of the print control section. (2) The video printer apparatus according to claim 1, wherein the print control section is constructed of the same gate array together with the control section for the image memory and the control section for the CPU. (3) The address from the CPU and the address from the print control unit are selectively stored in the ROM or the RAM.
The control means includes an address selector means for supplying the video signal to the video input terminal, and a changeover switch means for selectively transmitting the video signal input from the video input terminal or the video signal read from the image memory to the video output terminal. A video printer device characterized in that the address signal for the ROM and the RAM of a gate array and the video signal for the video output terminal are outputted from a common terminal pin.