JPH0461516A - Voltage controlled oscillator - Google Patents

Abstract

PURPOSE:To obtain a stable oscillating frequency by using 1st and 2nd switch control means so as to turn on/off complementarily 3rd and 5th FETs. CONSTITUTION:When the potential at a connecting point 13 exceeds a 1st threshold level, the output of a 1st threshold level decision circuit 91 goes to an H level, FETs 64b,76b are turned off and FETs 64a, 76b are turned on, and a FET 63 is turned off and a FET 75 is turned off. Thus, a charge charged in a capacitor 80 flows to a ground potential VSS via a connecting point N13 and the FET 75 and is discharged at a time constant depending on an ON- resistance of the FET 75 and the capacitance of the capacitor 80. When the potential at the connecting point N13 is decreased up to a 2nd threshold level, the output of a 2nd threshold level decision circuit 92 goes to an H level, the FET 63 is turned on, the FET 75 is turned off to start the charging of the capacitor 80.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is applicable to, for example, a CCD (Charge Couple).
edDevice) It is used as an internal charge transfer lock signal source in an integrated circuit device, etc., and relates to a voltage controlled oscillator whose oscillation frequency changes depending on the input voltage.

(Prior art) Conventionally, as a technology in this field, Japanese Patent Application Laid-Open No. 2-37
There was one described in Publication No. 820.

The configuration will be explained below using figures.

FIG. 2 is a circuit diagram showing an example of a conventional voltage controlled oscillator.

This voltage controlled oscillator connects the first connection point N1 and the ground potential V
It has a constant current circuit 1 connected between SS and controlled by an input voltage Vin, and has a first connection point N1 connected to a first current circuit 1 to set a charging current for a charging/discharging capacitor 32. A mirror circuit 10 is connected. The first current mirror circuit 10 includes a P-channel type first current mirror circuit 10 connected to a power supply potential CC. Second. The third FET (having a field effect transistor >11.12.13, whose FET1
Each of the gates 1 to 13 is commonly connected to the first connection point Nl. The FET 12 is connected via the second connection point N2,
A second Karen 1-Miller circuit 20 for setting a discharge current for the capacitor 32 is connected. The second current mirror circuit 20 has N-channel type fourth and fifth FETs 24 and 25 connected to the ground potential VSS, and the FE
Each gate of T24°25 is commonly connected to the second connection point N2.

Between the FETs 13 and 25, a P-channel type FET 30 and an N-channel type FET 31 for switching charge/discharge of the capacitor 32 are connected in series. This FET30
．． 31 is connected to the ground potential VSS via a charging/discharging capacitor 32, and is also connected to a level detection circuit B40.

Level detection circuit #140 detects the potential at the third connection point N3 and determines whether the detection result is "H" level or "
While outputting the output voltage Vout of L” level,
The output voltage ■out is fed back to F
This circuit turns on and off the ETs 30 and 31 in a complementary manner. This level detection circuit 40 includes a two-stage inverter 41
A first threshold value determining circuit 41 for charging/discharging switching consisting of a and 41b, a second threshold determining circuit 42 for charging/discharging switching consisting of a one-stage inverter 42a, and a second HII level or "L" level output voltage Vout. It is configured with a reset/set type frig-frozop (hereinafter referred to as R3F'F) 43 that outputs .

Next, the operation will be explained.

The constant current circuit 1 generates a current proportional to the input voltage Vin.
When current flows through FET II, a similar current (2) also flows through FETs 12 and 1B due to the current mirror effect.

When the output terminal Q of R3-FF4B is “L” level, the FE
Since T30 is in the on state and FET31 is in the off state,
The capacitor 32 is charged by the current (2) flowing through the FET 13 through the FET 30 and the connection point N3. FE
Since the on-resistance of T1B or the on-resistance of FET30 is set larger than that of FET30, the potential of the connection point N3 is
It increases according to a time constant determined by the on-resistance of 1B and the capacitor 32.

When the potential at the connection point N3 exceeds the first threshold, the output of the first threshold value determination circuit 41 becomes "H" level, and R5-F
F43 is set and its output terminal Q is ll L II
level changes to "H°" level.

Then, FET30 turns off and FET31 turns off.
is turned on, and the charge in the capacitor 32 is discharged to the ground potential VSS through the connection point N3 and the FETs 31 and 25. Since the on-resistance of FET25 is set larger than that of FET31, the connection point N3
The potential of is the on-resistance of the FET 25 and the capacitor 32.
It descends according to a time constant determined by

When the potential of the connection point N3 drops to the second threshold value, the output of the second threshold value determination circuit 42 becomes H°" level, and R3-
FF4B is reset and its output terminal Q goes to the "L" level. As a result, the FET30 is in the on state, and the FE
T31 turns off, and the charging operation of the capacitor 32 begins5. In this way, the charging and discharging of the capacitor 32 is repeated.
Output voltage Vout with oscillation frequency corresponding to input voltage Vin
is output from output terminal Q.

In this type of voltage controlled oscillator, a current (2) proportional to the input voltage Vin flows through the FET 11 due to the constant current circuit 1, a current (2) flows through the FET12.13 due to the current mirror effect, and a current (2) also flows through the FET2425. Therefore, the charging current to the FETs 1B and 30 and the capacitor 32 and the discharging current from the capacitor 32 to the FETs 31 and 25 have the same value. Here, the charging/discharging current of the capacitor 32 is determined by the input voltage ■in determined by the constant current circuit 1.
Since the current is proportional to , it does not fluctuate even if the power supply potential VCC fluctuates, and as a result, the charging and discharging time remains constant and a stable oscillation frequency can be obtained.

Furthermore, since the charging and discharging currents of the capacitor 32 are equal, an oscillation output with a Tute ratio of 50% can be easily obtained.

(Problems to be Solved by the Invention) However, in the voltage controlled oscillator having the above configuration, the on-resistance of the FETs 30 and 31 for charge/discharge switching varies due to variations in the power supply potential VCC and variations in temperature. Furthermore, the on-resistance of the FETs 30 and 31 varies due to manufacturing variations. If the on-resistance of the FETs 30, 3 changes, the charging/discharging current to the capacitor 32 changes, which causes a problem in that the oscillation frequency changes.

In order to solve this problem, it is conceivable to set the on-resistance of FETs 13 and 25 to be large while the on-resistance of FETs 30 and 31 can be ignored. However, FET13,25
If the on-resistance is set to a large value, the operating speed will decrease and it will not be possible to support high oscillation frequencies.Therefore, there is a limit to the increase in on-resistance, and it may not be possible to obtain a technically satisfactory result. Ta.

The present invention addresses the problem that the prior art had, in that the oscillation frequency becomes unstable due to fluctuations in the on-resistance of the charge/discharge switching FET due to fluctuations in power supply potential, fluctuations in temperature, and manufacturing variations. The present invention provides a voltage controlled oscillator that solves the problem.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a system in which each gate of the 1st to 9th second and third FETs is commonly connected to a connection point to charge and discharge a capacitor. A first current mirror circuit for setting a current, and a constant current corresponding to the input voltage are connected to the first current mirror circuit through the connection point. 2nd and 3rd F
That's it for ET? a second current mirror circuit in which the gates of the fourth and fifth FETs are commonly connected to the source or drain of the second FET to set a discharge current to the capacitor; In a voltage controlled oscillator equipped with a level detection circuit that detects the potential of a capacitor and outputs a high-level or low-level signal according to the detection result, the following means are provided.

That is, in the present invention, based on the output of the level detection circuit, the first switch control means turns on and off the third F E to charge the capacitor; , a second switch control means for turning on and off the fifth FET in a complementary manner to the third FET to discharge the capacitor.

(Function) According to the present invention, since the voltage controlled oscillator is configured as described above, the constant current circuit is connected to the first oscillator through the connection point. A constant current is passed through each of the second and third FETs, and the third FET
It has the function of controlling the gate voltage of ET. Furthermore, the second
The constant current flowing through the FET also flows through the fourth PET, and further through the fifth FET due to the current mirror effect. Therefore, the gate I-voltage of the second FET is controlled by a constant current circuit. And this third
The fifth FET is turned on and off in a complementary manner by the first and second switch control means, and has the function of switching the charging/discharging of the charging/discharging capacitor to oscillate at a frequency corresponding to the input voltage. .

In this way, the third and fifth FETs are controlled by their gate voltages or constant current circuits, so that they can withstand fluctuations in power supply potential, temperature fluctuations, and manufacturing variations.
The charging and discharging currents flowing through the third and fifth FETs are kept constant, and the oscillation frequency is stabilized. Therefore, the above problem can be solved.

(Example of Solid Line) FIG. 1 is a circuit diagram of a voltage controlled oscillator showing one embodiment of the present invention.

This voltage controlled oscillator is a complementary Mo5t-runsistor (
(hereinafter referred to as CMO3), and the input voltage V
A constant current circuit 50 controlled by in is connected between the first connection point N11 and the ground potential VSS. A current mirror circuit 60 for setting a charging current for the charging/discharging capacitor 80 is connected to the first connection point Nil.

The first current mirror circuit 60 is a P-channel type first current mirror circuit that flows a constant current. A first switch control means consisting of a second FET 61, 62, a P-channel type third FET 63 for switching charging/discharging of the capacitor 80, and P-channel type FETs 64a and 64b for turning on and off the FET 63. 64.

The first connection point N11 is connected to the gate I and the source of the FET 61, and the drain of the FE, T61, is connected to the power supply potential vccc. As a result, an output voltage corresponding to the value of the constant current (2) is generated at the connection point NIL of the second line. Moreover, the first connection point Nil is an FET
It is connected to gates 1 to 62 of FET 62, and also to the gate of FET 63 via FET 64b. FET62
The source of is connected to the second connection point NL2, and the drain thereof is connected to the power supply potential VCC. As a result, F
The configuration is such that a voltage value corresponding to the current I flowing through the ET62 is output to the second connection point N12.

The source of the FET 63 is connected to the third connection point N13, its drain is connected to the power supply potential VCC, and its gate is further connected to the power supply potential VCC via the FET 64a. A second current mirror circuit 70 for setting a discharge current for the capacitor 80 is connected between the third connection point N12.813 and the ground potential VSS.

The second current mirror circuit 70 includes a fourth N-channel type FET 74 through which a constant current (1) flows, and a second N-channel type FET 75 for switching charging and discharging of the capacitor 804.
Then, turn on FET75.

The second switch control means 76 includes N-channel type FETs 76a and 76b that are turned off.

The second connection point N12 is connected to the gates 1 to 1 of the FET 74, and is also connected to the gate of the FET 75 via the FE'l'' 76a. N12, the source is connected to the ground potential \°SS, the drain to 1 of the FET 75 is connected to the third connection point N1'3, the source is connected to the ground potential ■SS, and the gate is connected to the ground potential SS. , FET76b
It is connected to ground potential VSS via.

The third connection point N 1 B is a charge/discharge capacitor 80 of approximately 5 to 20 PF formed of MO5O5, for example.
It is connected to the ground potential VSS via. Further, the third connection point N13 is connected to the level detection circuit 90.

The level detection circuit 90 detects the potential of the third connection point N1B and determines the level of
While outputting an output signal Vout of L++ level,
It has a function of feedback controlling the first and second switch control means 64 and 76 using the output voltage Vout. This level detection circuit 90 is a two-stage CMO
A first threshold determination circuit 91 for charging/discharging switching consisting of S inverters 91a and 91b, and a one-stage CMOS inverter 9
A first threshold value determining circuit 92 for charge/discharge switching consisting of 2a and a CN70S for temporarily holding the take;
FF93 and CN・l OS inverter 9 for signal inversion
4.

The third connection point N13 is connected to the cent terminal S of R3-FF93 via the first threshold value determination circuit 91, and
It is connected to the reset/reset terminal R of the R5-FF 93 via the second threshold value determination circuit 92. The output terminal Q of R5-FF93 is connected to an inverter 94 tt, and the inverter 94 outputs an output voltage Vout. The output terminal Q of R5-FF93 is connected to the FETs 64b and 7 in the first and second switch control means 64.76.
The output terminal of the inverter 94 is further connected to each gate of the FETs 64a and 76b.

Next, the operation will be explained.

When the constant current circuit 50 causes a current proportional to the input voltage Vin4 to flow through the FET 61, a similar current (2) flows through the FETs 62 and 74 due to the current mirror effect.

When the output terminal Q of R3-FF9B is at the "L" level and the output of the inverter 94 is at the H level, FETs 64b and 7
6b is in an on state, and FETs 64a and 76a are in an off state. As a result, the FET 63 is turned on and the FET 7) is turned off. The potential of the connection point N13 is FE
It increases according to a time constant determined by the on-resistance of T6B and the capacitor 80.

This charging current is determined by the on-resistance of the FET 63, but since the gate of the FET 63 is connected to the gate of the FET 61, a current proportional to the input voltage Vin flows through the FET 6B due to the current mirror effect. It becomes two.

When the potential at the connection point N13 exceeds the first threshold, the output of the first threshold determination circuit 91 becomes "H°" level, and R3-
FF93 is set and its output terminal Q becomes HIGH level. As a result, FET64b and 76b are turned off, FET64a and 76a are turned on, and FET
63 is in the off state, and FET7"5 is also in the off state. Therefore, the charge in the capacitor 80 flows to the ground potential VSS side via the connection point NIB and the lower ET7, and the FET7"5 is in the off state.
The discharge continues with a time constant determined by the on-resistance of the ET75 and the capacitor 80.

This discharge current is caused by the on-resistance between F E and T7, which are connected in common to the gates of FET61 and FET62, and the gate of FET74 is connected to FET76a via FET76a.
Since it is connected to the gate of ET7, a current proportional to the input voltage Vin is caused by the current mirror effect.
ET7F).

When the potential at the connection point N 1 B drops to the second threshold,
The output of the second threshold value determination circuit 892 becomes "H" level, R3-FF93 is reset and its output terminal Q becomes "L" level.
” level.Then, FET6B is in the on state, and the FE
T73 is turned off, and charging of the capacitor 80 is stopped.

In this way, the charging and discharging operation of the capacitor 80 is repeated h, and the output voltage V with an oscillation frequency that is not proportional to the input voltage Vin.
out will be output from the inverter 94.

This embodiment has the following advantages.

(a> In this embodiment, the first and second switch control means 64, 76 control the FET 6B for charge/discharge switching.
, 7 is turned on and off, and its FET 63 is turned on and off.
, 75 are controlled by a constant current circuit 50 in the preceding stage. Therefore, the power supply potential V
The charging and discharging currents flowing through the FETs 6B and 75 are kept constant even with CC variations, temperature variations, and FET manufacturing variations, thereby making it possible to obtain a stable oscillation frequency.

In particular, since the capacitor 80 is charged and discharged only through the FET 6375, not only stable oscillation characteristics are obtained against fluctuations in the power supply potential and temperature, or manufacturing variations, but also the FET 6375 By reducing the on-resistance of 75, the operating speed can be increased and a high oscillation frequency can be supported.

(b) Even with fluctuations in the power supply potential VCC and temperature, as well as manufacturing variations, the charging and discharging currents flowing through the FETs 63 and 73 are made equal, resulting in a highly accurate oscillation output with a 0.0000000 ratio. Tutee ratio is FET6
By appropriately selecting dimensions such as 3.7, etc., it is also possible to set the tutee ratio of the oscillation output to a value other than 5088.

Note that the present invention is not limited to the above embodiments, and various modifications are possible. Examples of variations include the following.

(i) Even if the P-channel FET in Fig. 1 is configured as an N-channel FET, the N-channel FET is configured as a P-channel FET, and the power supply potential VCC and the ground potential ■SS are of opposite polarity. Almost the same action and effect as in Figure 1 can be obtained.

(ii) The circuit in Fig. 1 is converted to F'E other than CMO3.
It may also be composed of T or the like. Furthermore, the level detection circuit 90 may be modified to other circuit configurations. For example, inverk9
4 may be omitted, and instead, an inverted output terminal may be provided in R3-FF93, and the output voltage Vout may be output from the inverted output terminal.

Furthermore, this R3-FF 93 may be configured with another flip-flop, or this level detection circuit 90 may be configured with another circuit using a comparator or the like.

(Effects of the Invention) As described above in detail, according to the present invention, the third and fifth FETs are turned on and off in a complementary manner by the first and second switch control means. 3.
Charging and discharging of the capacitor is switched only through the fifth FET. Moreover, the third one. The gate voltage of the fifth FET is controlled to be a constant voltage by a constant current circuit due to the current mirror effect. Therefore, third. The charging and discharging current for the capacitor flowing through the fifth capacitor becomes constant, and a stable oscillation frequency that is not affected by fluctuations in power supply potential, fluctuations in temperature, and variations in device manufacturing can be obtained.

Furthermore, due to the current mirror effect, the gate voltages of the third and fifth FETs are controlled by the constant current circuit.
Since the third and fifth FETs are turned on and off in a complementary manner to charge and discharge the capacitor, stable oscillation can be achieved even if the on-resistance of the third and fifth FETs is small. Not only can the frequency be increased, but by reducing the on-resistance, the operating speed can be improved, and as a result, stable output can be obtained even at high oscillation frequencies.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a voltage controlled oscillator showing an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional voltage controlled oscillator. 50... Constant current circuit, 60.70...
1st. Mirror circuit to second current l, 61, 62.6B
, 74.75... 1st. Second. Third. 4th. 5th FET, 64.76... 1st. Second switch control means, 80...Capacitor, 90...
...Level detection circuit, Nl 1. N12. N13・
...First. Second and third connection point, V in...
...Input voltage, Vout - output voltage.

Claims (1)

[Claims] A first current mirror circuit in which the gates of the first, second, and third FETs are commonly connected to a connection point to set a charging current to a charging/discharging capacitor; a constant current circuit that flows a corresponding constant current to the first, second, and third FETs through the connection point, and each gate of the fourth and fifth FETs is connected to the source or drain of the second FET; a second current mirror circuit commonly connected to the capacitor for setting a discharge current for the capacitor; and a level detection circuit for detecting the potential of the capacitor and outputting a high level or low level signal according to the detection result. In the voltage controlled oscillator comprising, based on the output of the level detection circuit, the third FET
a first switch control means that charges the capacitor by turning on and off the third FET based on the output of the level detection circuit;
and second switch control means for turning on and off the fifth FET in a complementary manner to discharge the capacitor.