JPH0461376A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To highly integrate by so forming a contact hole as to reach a semiconductor substrate through a layer insulating film, a first wiring pattern and an insulating film. CONSTITUTION:A layer insulating film 5 is covered with a resist film 9, the film 9 is formed in a predetermined pattern in a photo step, then etched, and a contact hole 6 reaching a semiconductor substrate l is opened through the film 5, a gate electrode 4 and a silicon oxide film 2. Then, phosphorus ions are implanted to form an N-type diffused layer 7 also under the hole 6, the film 9 is removed, and polysilicon interconnections 8 of high resistance is so formed as second interconnection pattern on the film 5 and in the hole 6 as to be brought into contact with both the electrode 4 and the substrate l. Accordingly, the electrode 4 is brought into contact with the substrate l through the interconnections 8 in the hole 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, to a semiconductor device having a multilayer wiring structure, in which a contact portion to a semiconductor substrate is improved.

(Conventional technology) S RAM (Static Random Access
- For boat fishing, resistor R1 and NMO3) transistor (N channel M
O3 type transistor) Nl connects power supply VCC and ground GND
and resistor R2 and NMO3) transistor N! Connect between the power supply VCC and the ground GND, and connect between the resistor R0 and the range metal N3
Connected to the gate of S transistor N2, resistor R2 and N
NMO3) transistor N,
A memory cell M connected to the gate of is used. Note that memory cells using MOS transistors in place of the resistors R3 and R2 are also common.

In such a memory cell M, the storage node Q3 is connected between the resistor R3 and the NMOS transistor N1, and the resistor R2 and the NMOS transistor N1 are connected to each other.
3l and transistor N2 is a storage node Q0, one storage node Q1 is connected to bit line B via NMO3) transistor N, and the other storage node Q0
is connected to the bit line B0 via a transistor N4, and the gates of these NMOS transistors N3 and N4 are connected to the word line W.

Here, storage nodes Q and Qo are resistors R1 or R2
, the gate of the MOS transistor, and the source/drain of the MOS transistor are connected to each other, and its conventional cross-sectional structure is as shown in FIG. 3 or 4, for example.

That is, in the conventional example (first conventional example) shown in FIG. 3, a gate electrode 4 constituting the gate of a MOS l-transistor is formed on a semiconductor substrate 1 on which a thin silicon oxide film 2 and a LOCO3 oxide film 3 are formed. At the same time, the gate electrode 4 is covered with an interlayer insulating film 5.

Then, a contact hole 6 is opened that penetrates the interlayer insulating film 5 and the insulating film 2 so that the end of the gate electrode 4 and the surface of the semiconductor substrate 1 are exposed.
A diffusion layer 7 constituting the source and drain of the MOS transistor is formed below the MOS transistor, and a diffusion layer 7 is formed on the interlayer insulating film 5 and in the contact hole 6 so as to be in contact with the end of the gate electrode 4 and the surface of the semiconductor substrate 1. A polysilicon wiring 8 constituting the resistor R7 or R2 of the memory cell M is formed on.

Therefore, gate electrode 4 is in contact with semiconductor substrate 1 via polysilicon wiring 8 .

On the other hand, in the conventional example (second conventional example) shown in FIG. 4, the end of the gate electrode 4 is in direct contact with the surface of the semiconductor substrate 1, and a diffusion layer 7 is formed below the end of the gate electrode 4. A contact hole 6 is opened to reach the upper surface of the end portion of the gate electrode 4.

A polysilicon wiring 8 is formed on the upper surface of the interlayer insulating film 5 and within the contact hole 6.

Therefore, in this example, the polysilicon wiring 8 constituting the resistor R1 or R2 is connected to the semiconductor substrate 1 through the gate electrode 4.
has been contacted.

[Problem to be solved by the invention]

In this way, the storage nodes Q1 and Qo of the memory cell M can be configured using the first and second conventional techniques, but these conventional techniques have the following drawbacks.

That is, in the first conventional example, the contact hole 6 is
Both the end of the gate electrode 4 and the upper surface of the semiconductor substrate l must be exposed, and when errors in alignment are taken into consideration, the diameter of the contact hole 6 (r in FIG. 3) becomes large. This has been a hindrance to higher integration of semiconductor devices.

Further, in the second conventional example, since the contact hole 6 only needs to expose the upper surface of the end portion of the gate electrode 4, there is no need to make the diameter of the contact hole 6 so large. There are no problems.

However, since the gate electrode 4 is brought into direct contact with the upper surface of the semiconductor substrate 1, a photo process is required to remove a part of the silicon oxide film 2 before forming the gate electrode 4, which is more difficult than the first conventional example. The number of steps increases, and the photo step is performed with the silicon oxide film 2 exposed, so if the surface is cleaned with hydrofluoric acid or the like after the photo step, the silicon oxide film 2 will be contaminated. The gate oxide film is damaged and the performance of the MOS transistor is adversely affected.

This invention was made by focusing on the unresolved problems of the conventional technology, and by improving the part where all of the multilayer wiring contacts the semiconductor substrate,
It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that does not impede higher integration of semiconductor devices and reduces the risk of contamination of gate oxide films and the like.

[Means to solve the problem]

In order to achieve the above object, the invention described in claim (1) forms a first wiring pattern on a semiconductor substrate on which an insulating film is laminated, and also forms an interlayer insulating film on the first wiring pattern. A semiconductor device in which a second wiring pattern is formed through a contact ball that penetrates the interlayer insulating film, the first wiring pattern, and an insulating film to reach the semiconductor substrate; , was also formed in the contact hole so as to be in contact with the first wiring pattern and the semiconductor substrate.

The invention as set forth in claim (2) is a method for manufacturing a semiconductor device, which includes the steps of: forming a first wiring pattern on a semiconductor substrate on which an insulating film is laminated; forming an interlayer insulating film on the first wiring pattern; and opening a contact hole penetrating the interlayer insulating film, the first wiring pattern, and the insulating film to reach the semiconductor substrate. , forming a second wiring pattern on the interlayer insulating film and in the contact hole so as to be in contact with the first wiring pattern and the semiconductor substrate.

[Effect]

In the present invention, the contact hole includes an interlayer insulating film,
Since the contact hole reaches the semiconductor substrate by penetrating the first wiring pattern and the insulating film, the diameter of the contact hole may be small.

Further, in the invention as set forth in claim (2), since the interlayer insulating film, the first wiring pattern, and the insulating film are opened at the same time, the semiconductor substrate can be completely removed. (The photo process is not performed with the film exposed, and the number of photo processes can be reduced.

〔Example] Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1(a) to 1(d) are diagrams showing one embodiment of the present invention, in which the storage node Q of the memory cell M shown in FIG.
, Q shows the manufacturing process of the parts.

First, a gate of an MO3h transistor is placed on a P-type semiconductor (silicon) substrate 1 on which a thin silicon oxide (Si02) film 2 as an insulating film and an OCO3 oxide film 3 forming an element isolation region are laminated. 1 to 4 are formed as the first wiring pattern (see Fig. 1(a)).
)reference).

Next, ion implantation (gate self-alignment) is performed using the gate/electrode 4 as a mask to form an N-type diffusion layer 7 that constitutes the source/train of the MOS transistor. For example, CVD
5 i Form an interlayer insulating film 5 made of O□ film (first
(See Figure (1))).

Then, the glabellar insulating film 5 is covered with a resist film 9, and the resist film 9 is formed into a predetermined pattern by a photo process, and then etched to form a semiconductor through the interlayer insulating film 5, the gate electrode 4, and the silicon oxide film 2. A contact hole 6 reaching the substrate 1 is opened (see FIG. 1(C)).

Next, phosphorus ions (P') may be implanted to form an N-type diffusion layer 7 below the contact hole 6 and then the resist film 9 is removed.After the resist film 9 is removed, phosphorus ions may be implanted. ), and a high-resistance polysilicon wiring 8 as a second wiring pattern is formed on the interlayer insulating film 5 and in the contact hole 6 so as to be in contact with both the gate electrode 4 and the semiconductor substrate 1 (the first (See figure (d)).

Therefore, gate electrode 4 is in contact with semiconductor substrate 1 via polysilicon wiring 8 in contact hole 6 .

In this way, in this embodiment, the contact hole 6
passes through the gate electrode 4 and reaches the semiconductor substrate 1, and polysilicon has a good step coverage, so
The diameter of the contact hole 6 may be the minimum dimension of the process,
The device can be miniaturized, and it is effective for increasing the size of semiconductor devices.

Moreover, the interlayer insulating film 5. Since the gate electrode 4 and the silicon oxide film 2 are opened at the same time, only one photo process is required.
Since there is no need to perform the photo process with the silicon oxide film 2 exposed, the silicon oxide film 2 constituting the gate oxide film will not be damaged and adversely affect the performance of the MOS transistor.

[Effects of the Invention] As explained above, according to the inventions described in claims ( ) and (2), the diameter of the contact hole may be the minimum dimension of the process, so the element can be miniaturized, and the semiconductor device can be improved. It is effective for increasing the height of buildings.

Further, according to the invention as set forth in claim (2), the number of photo steps is reduced, and furthermore, there is an effect that the insulating film on the semiconductor substrate is not damaged by the photo step.

[Brief explanation of the drawing]

1(a) to (d) are cross-sectional views showing the manufacturing process of an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the configuration of an SRAM, and FIG. 3 is a cross-sectional view showing a conventional example. FIG. 4 is a sectional view showing another conventional example. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Silicon oxide film (insulating film), 3... L OCOS oxide film, 4... Gate electrode (first wiring pattern), 5... Interlayer insulating film, 6...
・Contact hole, 8... Polysilicon wiring (second
wiring pattern) 4'7 one tot @ book 1 3LOCO5 determination

Claims (2)

[Claims] (1) In a semiconductor device in which a first wiring pattern is formed on a semiconductor substrate on which an insulating film is laminated, and a second wiring pattern is formed on the first wiring pattern via an interlayer insulating film, a contact hole passing through an interlayer insulating film, a first wiring pattern, and an insulating film to reach the semiconductor substrate, and having the second wiring pattern in contact with the first wiring pattern and the semiconductor substrate. A semiconductor device characterized in that a contact hole is also formed within the contact hole. (2) forming a first wiring pattern on a semiconductor substrate on which an insulating film is laminated; forming an interlayer insulating film on the first wiring pattern; opening a contact hole that penetrates the wiring pattern and the insulating film to reach the semiconductor substrate;
A method for manufacturing a semiconductor device, comprising the step of forming a second wiring pattern on the interlayer insulating film and in the contact hole so as to be in contact with the first wiring pattern and the semiconductor substrate.