JPH0461088A - Digital signal recording and reproducing device - Google Patents

Abstract

PURPOSE:To prevent the discontinuity of a frame address at the joint of a consecutive recording by providing a means which detects an address information from a digital signal to be reproduced, and loads a value in accordance with the detected address information to an address counter. CONSTITUTION:When a magnetic tape 1 becomes a normal running state, a normal frame address is detected by an ID detection circuit 9, a first frame address to be detected is loaded to a frame address counter 10, and the output data of the address counter 10 is added to the digital signal which is recorded as the address information. The value of the address information outputted from the address counter 10 become equal to the address value at the digital signal stored on the track on the magnetic tape 1 scanned by rotary heads 2a,2b, and the value of the address information of the digital signal to be recorded becomes equal to that of the address information of the digital signal on the track where it is recorded. Thus, the address information is continuous at the joint of the consecutive recordings.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal recording and reproducing device that digitizes information signals and records and reproduces them on a magnetic tape.
The present invention relates to splicing recording in which a new digital signal is recorded following a previously recorded green signal on a magnetic tape that has already been recorded.

[Prior Art] A recording/reproducing apparatus is known that uses a magnetic tape as a recording medium and records digitized information signals such as digital audio signals using a rotating head.

In such a digital signal recording and reproducing device, according to the Japan Electronics Industry Association standard CP-2305 for DAT (digital audio tape recorder), one frame of a digital signal is divided into two tracks, a + azimuth track and a - azimuth track. This digital signal includes a 4-bit frame address for frame identification and 2 frames (4 tracks) as a pilot signal for tracking control during playback. ) The pattern repeats every time ATF (Automatic Track)
(Finding) signal is added.

[Problems to be Solved by the Invention] Incidentally, in such a digital signal recording and reproducing device, as in a video tape recorder, a new signal can be added to a magnetic tape on which data has already been recorded. Digital signals may be recorded. This is hereinafter referred to as splice recording, but when this splice recording is performed, the seam between the already recorded digital signal and the newly recorded digital signal (hereinafter referred to as the seam in spliced recording) There was a problem that the frame address, A, and TF signals were discontinuous, and tracking was disturbed at this joint during playback.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital signal recording and reproducing apparatus that solves such problems and can prevent discontinuity of frame addresses and ATF signals at joints in spliced recording.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides means for detecting address information from a reproduced digital signal and loading a value corresponding to the address information into an address counter. The output data of the counter is added to the digital signal recorded as address information.

Further, in the present invention, the pilot signal for tracking control is a signal having a pattern corresponding to the address information from the address counter section.

[The value of address information output from the active core address counter is
The address value of the digital signal recorded on the track on the magnetic tape being scanned by the rotating head is equal to the address value of the digital signal, and the address information of the recorded digital signal is equal to the address information and value of the digital signal on the track on which it is recorded. become equal. Therefore, address information is continuous at the joint in spliced recording.

This also applies to the pattern of the tracking control pilot signal.

[Example code] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a digital recording/reproducing apparatus according to the present invention, in which 1 is a magnetic tape, 2a,
2b is a rotating head, 3 is a capstan, 4 is a reproduction circuit,
5 is a switch, 6 is a recording circuit, 7 is a capstan servo circuit, 8 is a demodulation circuit, 9 is an ID detection circuit, 10 is a frame address counter, 11 is an error correction circuit, 12 is a correction circuit, 13 is a modulation circuit, 14 15 is an ID generation circuit, 15 is an ATF signal generation circuit, 16 is an encoding circuit, 17 is a switching circuit, 18 is a control circuit, 19 is a D/A (digital/analog) conversion circuit, 20 is an output terminal, and 21 is an A/A/ D (
analog/digital) conversion circuit, 22 is an input terminal, 2
3 is a switching circuit.

First, the normal recording operation of this embodiment will be explained.

An analog information signal to be recorded is input from the input terminal 22. This information signal is converted into a digital signal by an A/D conversion circuit 21. of course.

A digital signal may be directly input. In this case,
A/D converter 21 is not used.

After an error correction code is added to the digital signal by the encoding circuit 16, the digital signal is supplied to the modulation circuit 13, and then the ID generation circuit 1
ID signals such as frame addresses generated in 4 and AT
The ATF signal generated by the F signal generation circuit 15 is added and modulated to form a digital signal according to a predetermined format.

The digital signal output from the modulation circuit 13 is amplified to a predetermined level by the recording circuit 6, and then supplied to the rotary heads 2a and 2b via the switch 5 and recorded on the magnetic tape 1 running by the capstan 3. Ru.

Here, the rotary head 2a is a +azimuth head, and the rotary head 2b is a -azimuth head, and recording on the magnetic tape 1 is performed alternately by these.

The frame address counter 10 counts and amplifies the frame reference signal from the control circuit 18, and outputs a frame address. This frame address is ID generation circuit 1
4 and the ATF signal generation circuit 15. During normal recording, the ID generation circuit 14 generates an ID signal using the ID information supplied from the control circuit 18 via the switching circuit 23 and the frame address from the frame address counter 10. Further, the ATF signal generation circuit 1It15 generates an ATF signal having a pattern corresponding to the frame address from the frame address counter 10.

The switching circuit 17 is controlled by the control circuit 8, and when recording,
A digital signal output from the A/D conversion circuit 21 is selected. As a result, this digital signal passes through the switching circuit 17, is converted into an analog information signal by the D/A conversion circuit [-9], and is supplied from the output terminal 20 to a monitor (not shown).

Note that the switch 5 is turned on during recording and turned off during playback.

Next, the playback operation will be explained.

The signals reproduced from the magnetic tape 1 by the rotary heads 2a and 2b are amplified at the reproduction port 84 and converted into digital signals, and then demodulated by the demodulation circuit 8, and an ID signal is extracted from the digital signals. The digital signal outputted from the demodulation circuit 8 is subjected to error correction in an error correction circuit 11 using an error correction code, and furthermore, uncorrectable portions are corrected in a correction circuit 12. The digital signal output from the correction circuit 12 passes through the switching circuit 17,
It is converted into an analog information signal by the D/A conversion circuit 19, and is supplied to the monitor from the output terminal 2o.

On the other hand, the ID signal extracted by the demodulation circuit 8 is supplied to the ID detection circuit 9 where error detection is performed.
When the signal is detected, its ID information is supplied to the control circuit 18. The control circuit 18 is, for example, a microcomputer, and controls operation modes such as recording and reproduction, and controls generation of an ID signal in the ID generation circuit 14, based on the ID information supplied from the ID detection circuit 9. .

In addition, in the reproducing circuit 4, the ATF is converted from the reproduced digital signal.
A signal is extracted, and this ATF signal is supplied to the capstan servo circuit 7 to control the capstan 3. The capstan servo circuit 7 runs the magnetic tape 1 at a constant speed during recording under the control of the control circuit 18, and controls the running speed of the magnetic tape 1 based on the ATF signal during playback.

Next, with reference to FIG. 2, a description will be given of splicing recording for recording a new digital signal on the magnetic tape 1 on which recording has already been performed. However, in this splicing recording, a new digital signal is recorded overlappingly from a designated position in the recording area of the already recorded digital signal.

Assume now that the magnetic tape 1 is in a stopped mode as shown in FIG. 2(A). This magnetic tape 1 has
A digital signal has already been recorded. At this point, if there is an instruction to start recording from an external source.

When the magnetic tape 1 starts running, an information signal is input from the input terminal 22. However, as shown in FIG. 2(A), first, along with the recording start instruction.

The playback mode is set. Also, at this time, switching circuit 1
7 selects the digital signal output from the A/D conversion circuit 21 in response to the recording start instruction.

Thereby, as shown in FIG. 2(D), it becomes possible to monitor the input information signal simultaneously with the recording start instruction.

As described above, the magnetic tape 1 starts running and the digital signal is reproduced, but since the running state of the magnetic tape 1 does not become steady, the frame address is detected by the ID detection circuit 9 as shown in FIG. 2(B). cannot be detected properly. after that,
When the magnetic tape 1 is in a normal running state, the ID detection circuit 9 detects a normal frame address. Assuming that the first detected frame address is "n" as shown in FIG. 2(B), this frame address "n" is loaded into the frame address counter 10.

Further, ID information other than the frame address detected by the ID detection circuit 9 is supplied to the III) generation circuit 14 via the switching circuit 23. As a result, the ID generation circuit 4 generates an ID signal from the frame address from the frame address counter 10 and this ID information, and outputs the ID signal from the frame address "n". Further, the ATF signal generation circuit 15 generates an ATF signal with a pattern corresponding to the frame address from the frame address counter 10.

As a result, the ID generation circuit 14 and the ATF signal generation circuit 1
5 means that a frame address and ATF signal consecutive to the frame address and ATF signal reproduced from the magnetic tape 1 are generated.

Furthermore, the ID information output from the ID detection circuit 9 is also supplied to the control circuit 18. When the control circuit 18 receives this ID information, it switches to the recording mode as shown in FIG. 2(A). However, one frame later, the switch 5 is turned on and recording of a new digital signal is started.

Therefore, as shown in FIG. 2(C), a new digital signal is recorded on the magnetic tape 1 from the portion to which the frame address of rn+2J is added. In this way, the reason why recording starts one frame after switching to the recording mode is because the ID generation circuit 14 and the ATF signal generation circuit 15
This is because there is a possibility that it is not working properly.

In this way, even if the recording start timing of a new digital signal is delayed by one frame, the new digital signal will be recorded over the already recorded digital signal, so the frame address of "n+1" will be changed. The digital signals already recorded on the magnetic tape 1 remain as digital signals, and therefore, at the joint, both the frame address and the ATF signal are continuous.

Note that when a recording start command is issued and no frame address is detected by the ID detection circuit 9 for a predetermined period of time, the reproduction mode is switched to the recording mode and recording of a new digital signal is started. As a result, the unrecorded magnetic tape 1
It is also possible to record. In this case, the ID generation circuit 14 generates an ID signal using the ID information supplied from the control circuit 18 via the switching circuit 23 and the frame address from the frame address counter 10. This also applies to normal recording without splice recording.

When recording is completed, the magnetic tape 1 is rewound by a predetermined amount and then stopped. When recording a new digital signal, the ID detection circuit 9 detects when the magnetic tape 1 has traveled by the rewound amount. The frame address provided may be used as described above. Thereby, a new digital signal can be successively recorded on the unrecorded area of the magnetic tape 1.

Next, the operations of the ID detection circuit 9 and frame address counter 10 will be explained with reference to FIG.

The frame address counter 10 normally operates as shown in FIG. 3(B).
The count is incremented at the rising edge of the frame reference signal representing the timing of the frame shown in , and a frame address is generated.

Here, as explained earlier, in the playback mode after the recording start instruction (as shown in Figure 3 (A) and Figure 3 (C), the digital signal of each frame is being played back). Then, when the ID detection circuit 9 correctly detects the frame address to be reproduced, it outputs a frame address detection signal (FIG. 3(D)) representing this.As the detection condition, for example, the frame address is detected twice or more and when at least two consecutively reproduced frame addresses match, it is assumed that the frame address has been detected correctly.In addition, in FIG.

This detection is performed track by track, but 2
The processing may be performed in units of tracks (in units of 1 frame).

Based on this frame address detection signal, the frame address counter 10 is loaded with the frame address detected by the ID detection circuit 9, as shown in FIGS. Generates a frame address.

FIG. 4 is a flowchart showing loading conditions for the frame address counter 10.

When the frame address is not detected correctly by the ID detection circuit 9 (step 100), -azimuth head 2b
Each time the frame address counter 10 scans the magnetic tape 1 (step 101), the frame address counter 10 counts up by 1 (step 102).

When the ID detection circuit 9 correctly detects a frame address (step 100), if this detection occurs when the magnetic tape 1 is scanned by the ten address head 2a (step 103), the detected frame address at that time is set as the frame address. Step 10 to load into counter 10
4)--If the magnetic tape 1 is being scanned by the azimuth head 2b (step 103), the value obtained by adding 1 to the detected frame address at that time is loaded into the frame address counter 10 (step 105).

Here, the track scanned for reproduction by the +azimuth head 2a and the track scanned for reproduction by the -azimuth head 2b form the same frame and the same frame address is recorded, and the ID detection circuit 9 detects the frame There is a delay of one trunk scanning time between detecting the address and loading this frame address into the frame address counter 10, and as is clear from FIG. Since the counter 9 counts up, as in steps 103 to 105, the frame address counter 1 is counted up according to the frame address detection timing.
Different loading values to 0.

FIG. 5 is a block diagram showing another embodiment of the digital signal recording/reproducing apparatus according to the present invention, and parts corresponding to those in FIG. 1 are given the same reference numerals.

This embodiment uses four single-rotation heads, two of which are used for recording and the remaining two for reproduction.

That is, in FIG. 5, the rotating head 2 consists of four heads R,, P, , II, and P-, which are arranged in this order at equal intervals on the rotating drum, and the heads R,, R- are arranged at equal intervals on the rotating drum. Heads P+ and P- are for recording, and heads P+ and P- are for reproduction. + represents a +azimuth head, and - represents a -azimuth head, respectively. Further, the scanning trajectories of head R+IP on the magnetic tape 1 overlap, and the scanning trajectories of heads R- and P- also overlap.

The reproduction heads P, , P- are recording heads R+.

Even when recording by R-, by performing a reproduction operation and monitoring the reproduction signals resulting from these operations, the recording operation can be confirmed, and the reliability of recording can be improved.

Next, the operation at the start of recording in this embodiment will be explained with reference to FIG.

In the embodiment shown in FIG. 1, the recording/reproducing head 2a,
2b is used, as shown in FIG. 3, recording and reproduction occur at the same timing if the frame reference signal is used as the time reference. On the other hand, in the embodiment shown in FIG. 5, as is clear from FIG. 6, there is a 90" (1/4 frame) difference between recording and reproduction. The detected frame address is also shifted in timing by 1/4 frame and loaded into the frame address counter 10.The value loaded into the frame address counter 10 is the detected frame address plus 1. be.

FIG. 7 shows the operation when the frame address counter 1o is reset every 16 frames.

In this case, the frame address counter 1° is O~1
The count of 5 is repeated, and the frame address of the digital signal recorded on the magnetic tape 1 also repeats the values of 0 to 15.

In the embodiment shown in FIG. 5, the frame address correctly detected by the ID detection circuit 9 is incremented by 1 and loaded into the frame address counter 10, so when the detected frame address has a value of 15, As shown in FIG. 7, the value O is loaded into the frame address counter 1o, but the frame address counter 1° is configured to be reset, and when a frame address with a value of 15 is detected. , can be reset to a value of 0. That is, the frame address counter 10 continues counting up until a frame address with a value of 15 is detected. The digital signal is recorded using the frame address counter 10.
will not start until reset.

The above also applies to the embodiment shown in FIG.

By setting the frame address in this way, the frame address can be made into 4-bit data,
The circuit configuration can be simplified, such as by making the frame address counter 10 a simple 4-bit counter.

In each of the above embodiments, the frame address is directly loaded from the ID detection circuit 9 to the frame address counter 10, but the ID detection circuit 9 is configured to detect the frame address, and the control circuit 18 loads the frame address directly to the frame address counter 10. It is also possible to receive the address, perform processing such as adding 1, and load the result into the frame address counter 10.

[Effects of the Invention] As explained above, according to the present invention, during splice recording, the frame address and AT
The F signal can be made continuous at all times, and during reproduction, it is possible to prevent reproduction disturbance from occurring at this joint.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a digital signal recording and reproducing apparatus according to the present invention, FIG. 2 is a timing chart showing the operation of this embodiment in spliced recording, and FIG. 3 is a frame address counter in FIG. 1. FIG. 4 is a flowchart showing loading conditions of the frame address counter; FIG. 5 is a block diagram showing another embodiment of the digital signal recording/reproducing apparatus according to the present invention. 6 is a timing chart showing the loading operation of the detected frame address to the frame address counter in FIG. 5, and FIG. 7 is a timing chart showing an example of the timing operation of the frame address counter in FIG. 1...magnetic tape, 2, 2a, 2b...
・Rotating head, 5...Switch, 8...Mountain demodulation circuit, 9...rD detection circuit, 10...Frame address counter, 1...Error Correction circuit, 12... Correction circuit, 13... Modulation circuit, 14... ID generation circuit, 15...
...ATF signal generation circuit, 16...encoding circuit. 18... Control circuit, 19... D/A conversion circuit, 20... High strength terminal, 21... A/D conversion circuit, 22... Output terminal. Peng 2nd figure 4th figure

Claims (1)

[Claims] 1. An address counter that sequentially counts up for each frame of a digital signal to generate address information;
In a digital signal recording and reproducing device that adds the address information to the digital signal for recording and reproducing, the address information is detected from the reproduced digital signal, and a value corresponding to the detected address information is assigned. A digital signal recording and reproducing device characterized in that it is provided with means for loading an address counter. 2. In claim 1, a reproduction mode is once set with a recording start command, and the address information is detected from the reproduced digital signal by the means, and the recording mode is set, and the recording mode is set by the means. A digital signal recording and reproducing apparatus, characterized in that a value corresponding to the address information detected in the reproduction mode is loaded into the address counter. 3. In claim 2, a switching circuit is provided that selects and outputs either the digital signal to be reproduced or the digital signal to be recorded, and in the reproduction mode after the recording start command, the switching circuit selects and outputs the digital signal to be reproduced or the digital signal to be recorded. 1. A digital signal recording and reproducing device that selects and outputs a digital signal. 4. In claim 1, 2 or 3, the address counter repeats counting within a predetermined value range, and the address information repeats a value within the predetermined value range, and the means A digital signal recording and reproducing device characterized in that when address information of a predetermined specific value within the predetermined value range is detected from the signal, a value corresponding to the address information is loaded into the address counter. . 5. Claim 1, 2, 3 or 4, further comprising means for generating a tracking control pilot signal having a pattern according to the address information outputted from the address counter, the tracking control pilot signal being recorded. A digital signal recording/reproducing apparatus characterized in that the digital signal is added to the digital signal.