JPH0457969U - - Google Patents
Info
- Publication number
- JPH0457969U JPH0457969U JP9931390U JP9931390U JPH0457969U JP H0457969 U JPH0457969 U JP H0457969U JP 9931390 U JP9931390 U JP 9931390U JP 9931390 U JP9931390 U JP 9931390U JP H0457969 U JPH0457969 U JP H0457969U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- switch
- synchronizing signal
- clamp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000926 separation method Methods 0.000 claims description 4
- 230000001360 synchronised effect Effects 0.000 claims description 4
- 230000005684 electric field Effects 0.000 claims description 3
- 230000001629 suppression Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003044 adaptive effect Effects 0.000 description 1
Landscapes
- Picture Signal Circuits (AREA)
- Synchronizing For Television (AREA)
Description
第１図は本考案の一実施例を示す電界適応型の
同期分離回路のブロツク図、第２図は同第１図の
クランプ／積分回路部の回路図である。
１ａ，１ｂは電界レベルに対応したクランプ／
積分回路部、４は同期分離回路、７はノイズ抑圧
回路、８はコンパレータである。
FIG. 1 is a block diagram of an electric field adaptive type synchronous separation circuit showing one embodiment of the present invention, and FIG. 2 is a circuit diagram of the clamp/integrator circuit portion of FIG. 1. 1a and 1b are clamps/clamps corresponding to the electric field level.
In the integrating circuit section, 4 is a synchronous separation circuit, 7 is a noise suppression circuit, and 8 is a comparator.
Claims (1)
ランプ／積分回路部と第２のクランプ／積分回路
部とに接続し、同第１と第２のクランプ／積分回
路部の垂直同期用出力映像信号をそれぞれ第１の
スイツチ回路に、また、水平同期用出力映像信号
をそれぞれ第２のスイツチ回路に接続し、前記第
１のスイツチ回路出力と同第２のスイツチ回路出
力とをそれぞれ同期分離回路を介して垂直同期信
号および水平同期信号に分離出力し、更に、同水
平同期信号を第３および第４のスイツチ回路にて
直接出力またはノイズ抑圧回路出力の複数モード
選択出力とし、設定電界強度に基づく制御信号に
て前記第１、第２、第３および第４のスイツチ回
路を切り換えてなる同期分離回路。 In a television receiver or the like, a video signal is connected to a first clamp/integrator circuit section and a second clamp/integrator circuit section, and the output video signal for vertical synchronization of the first and second clamp/integrator circuit sections is are respectively connected to a first switch circuit, and the output video signals for horizontal synchronization are respectively connected to a second switch circuit, and the first switch circuit output and the second switch circuit output are connected to a synchronous separation circuit, respectively. The horizontal synchronizing signal is separated into a vertical synchronizing signal and a horizontal synchronizing signal through the third and fourth switch circuits, and the horizontal synchronizing signal is output directly through the third and fourth switch circuits, or as a multi-mode selective output of the noise suppression circuit output, based on the set electric field strength. A synchronous separation circuit in which the first, second, third and fourth switch circuits are switched by a control signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9931390U JPH0457969U (en) | 1990-09-21 | 1990-09-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9931390U JPH0457969U (en) | 1990-09-21 | 1990-09-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0457969U true JPH0457969U (en) | 1992-05-19 |
Family
ID=31841148
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9931390U Pending JPH0457969U (en) | 1990-09-21 | 1990-09-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0457969U (en) |
-
1990
- 1990-09-21 JP JP9931390U patent/JPH0457969U/ja active Pending
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