JPH0457520A - Information converter - Google Patents

Abstract

PURPOSE:To ensure a large Tmin without reduction of a TW by selecting groups A, B so that a charge storage value DSV of a converted code word string is converged in a definite value, thereby the value into a code word. CONSTITUTION:The converter consists of an 8-bit latch 1, a pre-coder 2, a computing element 3, a driver circuit 5, coders 21-23, 6-bit P/S converters 24-26 and AND gates 41, 42. A charge storage value (CDS) of each code word is any of 0, + or -1-+ or -3 and a conversion map consists of two groups A, B in which code words whose CDS is not equal to '0' have the same absolute value and opposite polarity are used in pairs. Thus, the groups A, B are selected so that the charge storage value (DSV) of a converted code string is made within a definite value to convert the information and the number of code words of the conversion map is selected so that number of consecutive same levels in each code word is <=4 and the number of consecutive same level in a code string is <=5. Thus, the result that a detection wind width TW is 1.33T and a minimum magnetization inversion internal Tmin is 1.33T is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information conversion device that converts binary 8-bit digital information into a ternary 6-baud code word.

[Conventional technology]

In general, in systems where information is recorded via a rotating transformer, it is difficult to transmit low frequency components, so it is desirable to use a DC-free modulation method with as small a low frequency power spectrum component as possible. T-r, and the minimum magnetization reversal interval T1. It is desirable that the device be large and capable of high-density recording. In order to reduce the high-frequency components as much as possible, it is desirable that T vs = n be large.

Conventionally, as a modulation method for high-density recording such as PCM audio of VTR and digital audio tape recorder, the 8-14 modulation method shown in IEICE technical research report MR86-5 and Japanese Patent Application Laid-Open No. 60-48646 have been used. There were 8-10 modulation schemes shown.

Table 1 shows a comparison of parameters for each modulation method.

Table 1 [Parameters comparison table for each encoding method] The former 8-14 modulation method uses original data words in which a binary level (High level r1., Low level "0") data string is divided into 8 bits. , into a 14-bit binary level codeword, and the code is configured such that the converted codeword string has at least 2 consecutive bits of the same level. As a result, the cycle T for detecting the code string is given by TX (number of bits of the original data word)/(number of bits of the code word), where T is the cycle of the original data word.BT/14
Although it is small as ζ0.57T, the minimum magnetization reversal interval T, 8
ゎ becomes bigger next door.

In addition, the latter 8-10 modulation method converts the original data word, which is a binary level data string divided into 8 bits, into 10-bit 2
It converts to a value-level code word, and T is 8 T/1.
0 = 0.8T, T, , l is (8T/10) X
1 = 0.8T, and T is larger than the 8-14 modulation method, but T1. , becomes smaller.

Note that both of the above two modulation methods have C in each code.
D S (Code word-Digital-3
(abbreviation of um), High level is r+1'', Low
The amount of charge accumulated in the code word (if a charge of "-1" is accumulated at the level) is regulated, and in the case of the 8-14 modulation method, it is limited to "0.±2.4.±6". In the case of the 8-10 modulation method, only the code word "0 or ±2" is used.

Furthermore, the relationship between the original data word and the code word is that the code word with CD5=0 has a one-to-one correspondence with the original data word, and for other code words, code words with different CDS polarity are used as bare code words.
Two code words are associated with one data word.

In addition, the selection of the code word is based on the charge accumulation amount D S of the code word string.
V (Digital-Sua+-Variation
), and when converting the original data word to a code word, if DSV>O, a code word whose CDS is O or negative is output corresponding to the original data word, and when DSV<0 In this case, a code word whose CDS is 0 or positive is output, and D
In the case of SV=O, if the code word corresponds to the original data word, it is configured to output a code of either 0 or Free modulation is realized.

[Problem to be solved by the invention]

Since the conventional information modulation device is configured as described above, if you try to increase T18, T becomes smaller,
On the contrary, T. If we try to increase,T,i,,,, becomes smaller. In addition, in order to realize DC-free modulation, it is necessary to prepare two code words corresponding to one original data word, and if we want to realize a more efficient modulation method,
Since it is necessary to increase the ratio of the number of code words to the number of original data words, there are problems such as the need to increase the scale of the hardware.

This invention was made to solve the above-mentioned problems, and T min without reducing Th.
Information conversion that can secure a large amount of data, generate a phase error generation signal to generate a clock synchronized with the playback data required during playback without increasing the hardware scale, and achieve DC-free modulation. The purpose is to obtain equipment.

[Means to solve the problem]

The information conversion device according to the present invention classifies binary level input digital information into 8-bit units and converts the divided original data words into ternary level 6-baud code words according to a conversion map. , the above conversion map has a charge storage amount CDS of each code word of 0. ±1. ±2. ±3, and each code word has at least one code string in which +1 and -1 are adjacent, and is divided into 82 groups, and A when CDS = 0. , Each code word in group B is the same, and each code word in group A and B when CDS≠0 consists of a pair with the same absolute value and opposite polarity, and the same level within each code word The number of consecutive code word strings is 3 or less, and the number of consecutive code word strings of the same level is 4 or less. Quantity DS
A and B of the above conversion map so that V falls within a finite value.
It is configured to select a group and convert it into a code word.

[Effect]

In this invention, the conversion map is converted into CDS of each code word.
is O9±1. ±2. Either ±3, CDS≠
For the code word 0, it consists of 82 groups A, which are pairs of code words with the same absolute value and opposite polarity.
Information is converted by selecting groups A and B so that the DSV of the converted codeword string is within a finite value.
Furthermore, for the codewords of the conversion map, the number of consecutive same levels in each codeword is set to 4 or less, and the number of consecutive same levels in a codeword string is set to 5 or less, so DC-free conversion can be performed. , detection window width T.

is 1.33 T, and the minimum magnetization reversal interval T a i n is 1
．． 33T can be realized.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

First, before explaining the operation of the embodiment of the present invention, the conversion principle will be explained.

Now, if the original data word length is 8 bits, the number of combinations is 2" = 256. If this is replaced with a 6-baud 3-level code word, 25 out of 36 = 729 combinations.
An appropriate code corresponding to the six sets may be selected.

When reproducing digital signals, it is necessary to generate a clock synchronized with the reproduced data, and generally P
An LL circuit is used. This PLL circuit detects phase information between a reproduced signal and a data detection clock every time the data state changes, and generates a clock synchronized with the reproduced data.

This three-value recorded digital signal is reproduced, integrally detected and converted into the original digital signal, and the reproduction digital signal generation for detecting the phase information of the data detection clock is shown in FIG.

In Fig. 4, X is a ternary recording signal waveform, Y is a reproduced signal waveform after waveform equalization and integration of the reproduced signal, and Z is a reproduced digital signal for detecting phase information with the data detection clock. .

First, as you can see by comparing the X and Y diagrams, during playback, the zero cross point corresponding to the data conversion point of ternary recording is obtained when the signal changes from "+1" to "1" or from "-1" to "+1"level; during other conversions, the relationship between the recording conversion point and the zero cross point of the reproduced signal is not guaranteed. Therefore, the reproduction digital signal generation for detecting the Z phase information is “+1” to “-”
The reproduced digital signal level is repeatedly inverted at only the zero cross points where the level changes from "1" and "-1" to "+1", and other zero cross points are masked. Therefore, the code word string is as much as possible from °“+1” to “-1” or from “par-1” to °°+1
It is desirable that there are many patterns whose level is converted to ``.

Furthermore, in devices to which the present invention is applied, it is common to record digital information on a magnetic medium via a rotating transformer. Since it is difficult to transmit the low-frequency power spectrum components, it is desirable that the recorded signal contains at least a small amount of low-frequency power spectrum components, and therefore, it is desirable that the code string has many state changes.

Therefore, in this embodiment, in a code word string, there are a maximum of five identical states, and within each code word, there is always a code string in which +1 and -1 are adjacent, and there are a maximum of four identical states. Yes, and up to 3 at the beginning where codewords are connected
, and a maximum of two consecutive run-length limited codewords are selected at the end. As a result, the number of codes that can be selected is as shown in Table 2.

Table 2 [Table of number of code words after run length restriction] CDS in the table is the charge accumulation value of the code word, and is
This is the added value from the first baud to the last baud when the ``+1'' level is +1 and the ``0'' level is 01, and the ``-1'' level is -1.

On the other hand, in order to realize DC-free modulation that does not include a DC component in the code word string after information conversion, it is necessary to maintain the DSV at a finite value, as in the conventional modulation method.

Therefore, in the present invention, a code word with CDS=0 is associated with an original data word on an I to l basis, and a code word with CDS≠0 is associated with a code word with a different polarity as bare.

As a result, the combination obtained from the number of code words in Table 2 is 100 (CDS=O) + 89 (CDS・+1) +58
(CDS・+2)+22 (CDS・+3) =26
Since there are 9 sets and 2''<269, ternary level DC-free modulation can be realized while satisfying the run length restriction as described above.

In the modulation method of this embodiment, a codeword with as many state changes as possible within the codeword is selected from among the run-length limited codewords shown in Table 2, and a codeword with as many state changes as possible within the codeword is selected.
The conversion map shown in d) associates the original data word with the code word.

In addition, the selection of A group and B group in the conversion map of Table 3 is such that when DSV=O and DSV<0, a code word corresponding to the original data word is selected from the code word group of A group, and when DSV>O , a code word corresponding to the original data word is selected from the code groups of group B.

Hereinafter, a circuit for realizing an information conversion method according to an embodiment of the present invention will be described.

FIG. 1 is a block circuit diagram of an information conversion device according to an embodiment of the present invention, showing the configuration of only one circuit. Figure 2 is a diagram showing the output data of each part of this embodiment.
) to (chains indicate output signals a to g of each part in Fig. 1. Fig. 3 is a conversion map for converting 8-bit data in this embodiment into a code word of ternary level 6 baud. be.

In the figure, 1 is an 8-bit latch that latches an 8-bit original data word, and outputs 8-bit parallel data a in synchronization with the rising edge of the symbol clock. 2 is a precoder for converting a binary level original data word into a code word of level 3 (I), and encoders 21, 22 and 23 to which the output a of 8-bit latch 1 is input in parallel; 6-bit P/S converters 24, 25 . It consists of 26.

3 is an arithmetic unit that calculates the DSv of the code word string by adding CD5 (shown in FIG. 2 (C)) output from the precoder 2, outputs "l" when DSV≦O, and calculates the DSV >O, outputs "0". 4 is a gate circuit; It is composed of second AND gate circuits 41 and 42, and generates a gate signal for converting a binary level signal input from the precoder 2 on three lines into a ternary level signal.

5 is a driver circuit, which outputs current to the output terminal when it is "+1" and turns the current to 0FF when it is "0" according to the three-value level according to the gate signal input from the gate circuit 4.
When L is "-1", the configuration is such that a current of 1 is drawn from the output terminal.

Next, the input data conversion operation in this embodiment will be explained.

The 8-bit parallel original data word a output from the 8-bit latch 1 is input in parallel to the encoders 21, 22, and 23, and the encoders 21, 22, and 23 perform the following processing in response to the ternary level code word. 6-bit parallel signals d, e, f under the conditions
Output.

The encoder 21 outputs a signal of high level "1" in binary level only for baud which is "+1" in the ternary bell signal, and outputs "0" in other cases. The encoder 22 outputs a low level "0" signal at a binary level only for a port which is "0" in the ternary bell signal, and outputs "1" in other cases. The encoder 23 outputs a 3-level signal that is High at 2W level only for baud that is "-1" in the bell signal.
Outputs level "1", otherwise outputs r□.

For example, as shown in Figure 2, the original data word is r68 (
HEX) J, "1" is output from the arithmetic unit 3, and the selected code word is [1, -1, 1, 0, 1] of the A group.
, IJ, the 8-bit original data word is changed to "001011" by the encoder 21 and rll by the encoder 22.
lo11+, the encoder 23 precodes it to "110000". These 6-bit parallel outputs d.

e and f are input to 6-bit P/S converters 24, 25, and 26, and converted into serial outputs. These three lines of serial output are input to the gate circuit 4, and the output of the gate circuit 4 is input to the driver 5 to set the switching transistors Ql and Q2 to ON or OFF.

In this setting operation, one of the two inputs of the gate 41 corresponding to "-1" of the first baud of the input code word, which is a ternary level, is at the "0" level, so Ql is turned OFF.
Since the two inputs of gate 42 are both "1", Q
2 is turned ON. As a result, transistor Q4 is turned off.
, Q5 is biased and turned ON since Q2 and Q3 are ON. Therefore, the output g becomes the level "-1" as a current is drawn from the output terminal to Q5.

Next, since the two inputs of the gate 41 corresponding to the third baud "1" of the input code word are both "1", Ql is ON, and one of the inputs of the gate 42 is "O", so , becomes OFF. As a result, Q4 is ON and Q5 is OF
It becomes F. Therefore, the output g has a level of "+1" as a current is discharged from Q4 to the output terminal.

Next, since all the gate inputs of the gate circuit 4 corresponding to the 4th baud "0" of the input code word become "0", Ql
, Q2 are both turned off, and as a result, Q4. Since Q5 is also turned off, the output g is at the "0" level.

In the manner described above, the 8-bit original data word a is converted into a 6-baud 3-level code word g.

Next, the operation for realizing DC free will be explained.

As can be seen from the conversion maps shown in FIGS. 3(a) to 3(d), when CDS=0, the codewords of group A and group B are the same, and CDS≠0 In this case, code words with the same absolute value and different polarities are used in pairs, and a positive code word is applied to the A group and a negative code word is applied to the B group.

Furthermore, each code word has at least one code string in which +1 and -1 are adjacent.

When selecting groups A and B, the arithmetic unit 3 calculates the DSV by integrating the CDS of the code word output from the encoder 21 using a 3-bit information word, and as a result, if DSV≦0,
The arithmetic unit 3 outputs "l", and when converting the next original data word, the encoder 21, 22, 23 outputs a 6-bit signal corresponding to the code word of group A, and the result is DS
In the case of V>O, the arithmetic unit 3 outputs "0", and when converting the next original data word, the encoders 21, 22, and 23 output a 6-bit signal corresponding to the code word of group B. It works like this.

For example, the selection operation will be explained in detail below with reference to FIG.

Now, consider a case where "68" is input as the original data word, the CDS up to the immediately preceding code word is 3 (011), and the output of the arithmetic unit output 3 to which this 3 is added is "1".

Note that the CDS of the code word used in this example is MA
Since X±3, the DSV for each end of the code word is MAX +
3. MIN becomes -3. Therefore, the fact that the output of the arithmetic unit 3 becomes "1" by adding CD5=3 is nothing but DSV-0.

Therefore, the code word corresponding to "68" in the A group is selected as the original data word 68, and +1 (001) is output to the CDS.

Next, if "09" is input as the source data word,
The integrated value of computing unit 3 is DSV=0+1, and DSV>O
Therefore, the output of the arithmetic unit 3 becomes "0" level, each encoder outputs a signal serving as a code word corresponding to "09" of group B, and O(000) is output to the CDS.

Furthermore, when the original data word FC is input, the integrated value of the calculator 3 is DSV-1+O, and DSV>0, so
The output of the arithmetic unit 3 becomes "0" level, and each encoder outputs a signal serving as a code word corresponding to the FC of the B group, and the C
-3 (111) is output to DS.

Furthermore, when the next data word is input, the integrated value of the arithmetic unit 3 becomes DSV=1-3, and DSV<0, so the arithmetic unit 3 outputs the "1" level, and each encoder outputs the A A signal that is a code word corresponding to the data word of the group is output.

Through the above conversion operation, the DSV becomes finite and DC-free modulation can be realized.

In the above embodiment, the CDS information is output from the encoder during encoding, but instead of this, the CDS information may be obtained by calculation from the converted code word.

〔Effect of the invention〕

As described above, according to the information conversion device according to the present invention,
When converting binary level input information into ternary level 6-baud codewords by dividing them into 8-bit units, this conversion map is divided into at least one adjacent code string of +1 and -1 in each codeword. , and the charge storage amount CDS of each code word is 0.
±1. ±2°+3, and for codewords with CDS≠0, two groups A and B with the same absolute value and opposite polarity are set up as a pair, and furthermore, the same level within each codeword is set. The above A and B groups are set so that the consecutive number is 4 or less, the consecutive number of the same level in the codeword string is 5 or less, and the DSV of the converted codeword is a finite value. By selecting , the inversion of the reproduced digital signal for detecting the phase information required when generating a clock synchronized with the reproduced data during reproduction is guaranteed for all information, and the probability of inversion is increased. It becomes possible to generate a reproduced clock with high precision. Furthermore, the spectrum of the encoded signal has low frequency components suppressed, DC-free modulation can be performed, and the detection window width is T. is 1.33T, which ensures a large detection margin for playback data, and
The minimum magnetization reversal interval T min is as large as 1.337, and there is no variation in output level due to spacing loss (e.g., an information conversion device capable of high-density recording with high reliability is obtained).

[Brief explanation of the drawing]

Fig. 1 is a block circuit diagram of an embodiment of this invention, Fig. 2 is a timing diagram for explaining the operation of this embodiment, and Figs. 4 is a diagram showing a digital signal recorded in three values, its reproduced signal waveform, and a reproduced digital signal for detecting the phase information of the data detection clock. In the figure, 1 is an 8-bit latch. , 2 is the precoder, 3
5 is an arithmetic unit, 5 is a driver circuit, 21.22.23 is an encoder, 24, 25.26 is a 6-bit P/S converter, 41.
42 is an AND gate. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1) The original data word, which is binary level digital information divided into 8 bits, is converted to ternary level 6 according to the conversion map.
This is an information conversion device that converts into a Baud code word, and the above conversion map is such that the charge storage amount CDS of each code word is 0, ±
1, ±2, ±3, and each code word has +
There is at least one code string where 1 and -1 are adjacent, and it is divided into two groups, A and B. When CDS = 0, each code word in groups A and B is the same, and CDS≠0.
In this case, each code word in groups A and B consists of a pair with the same absolute value and opposite polarity, and the number of consecutive same levels in each code word is 4 or less, and the code word string is is configured such that the number of consecutive same levels is 5 or less, and when converting information, the charge storage amount DSV of the converted code word string
An information conversion device characterized in that the information conversion device is configured to select the A and B groups and convert them into code words such that the group A and B fall within a finite value.