JPH0457410A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To realize low power consumption and high speed by using an NTL circuit for a circuit with a light load and using an NTL circuit with an emitter follower output circuit added thereto for a circuit with a comparatively heavy load, and selecting a voltage used for the NTL circuit depending on the pre- stage circuit constitution. CONSTITUTION:An NTL circuit is used for a logic gate circuit having only a light load such as reception of input signals A, B and supply of an output signal C to only an input transistor(TR) Q3 of a logic gate circuit of a next stage. In such a case, an operating voltage -VEE1 is selected to be a small voltage as about -1.2V. The NTL circuit to an output section of which an emitter follower output circuit is added is used for a logic gate circuit having a comparatively heavy load such as reception of input signals A, B and supply of an output signal C to the input TR Q3 and plural logic gate circuits. That is, collector output signals of TRs Q1, Q2 are supplied to the base of an emitter follower output TR Q5. In such a case, an operating voltage -VEE2 is selected to be a large voltage as -2V.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and for example,
The present invention relates to a technology that is effective for use in semiconductor integrated circuits using NTL (non-threshold logic) circuits.

[Prior Art] A conventional high-speed bipolar logic LSI is constructed using ECL (emitter coupling logic). Referring to the threshold voltage like an ECL circuit,
Unlike those that distinguish between high level and low level, NTL does not have a specific logic threshold.
(non-threshold logic) circuit. N.T.
In an L circuit, a signal is amplified through multiple gate circuits, and if the input-output transfer characteristics of multiple gate circuits intersect at approximately the center voltage, input levels higher than this crossing point are sequentially amplified. Eventually, it converges to the high level side. In a logic gate circuit, a plurality of logic gates are arranged in a multi-stage configuration, so the above-mentioned NT
Even if there is a one-point variation in the transfer characteristic of the L circuit, the level is corrected by passing the signal through another logic gate circuit having a similar variation, so the variation in the transfer characteristic does not pose much of a problem in practice.

Regarding such NTL circuits, for example,
Published by Radio Gijutsusha on May 20th, there is a page 72 of ``Encyclopedia of Latest Electronic Devices'' written by Genshiki Baba. In addition, patents related to this include Tokoku No. 42-21132 and Tokoku No. 42-229.
No. 4 and Special Publication No. 45-32005.

[Problem to be solved by the invention]

The ECL circuit described above has a problem in that, although it is high-speed because the transistors switch with low amplitude and unsaturated, it consumes a large amount of power, and when it is highly integrated, it quickly becomes large in power. On the other hand, NTL circuits have low power consumption and high speed, and are suitable for large scale integration. however,
Its load driving ability is relatively weak.

Therefore, the inventors of the present application developed a circuit with an emitter follower output circuit (EF
/NTL) and emitter follower output circuit.
Focusing on the fact that there is a so-called SPL (super pull-down logic) circuit that replaces the pull-down circuit, we thought of combining these circuits to form a single circuit system. When adopting this configuration, there is a problem in that the signal levels of the NTL circuit and the SPL circuit and the NTL circuit added with an emitter follower output circuit are different, so it may not be possible to directly connect these circuits. The present inventor's studies have revealed that there is.

An object of the present invention is to provide a semiconductor integrated circuit that has both low power consumption and high speed.

Another object of the invention is to provide a semiconductor integrated circuit that achieves large-scale high-speed operation.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, a circuit with a light load uses an NTL circuit, a circuit with a relatively heavy load uses an NTL circuit with an added emitter follower output circuit, and a circuit with a heavy load uses an SPL circuit to form one semiconductor integrated circuit. , the above NT
Among the L circuits, those receiving the output signal formed by the emitter follower output circuit or the SPL circuit use the operating voltage of the emitter follower output circuit or the SPL circuit as their operating voltage.

[For production]

According to the above-mentioned means, by taking advantage of the characteristics of the NTL circuit, such as low power consumption and high speed, the voltage used in the NTL circuit is switched according to the circuit configuration of the previous stage, and the signal transmission speed is not compromised. Level consistency can be achieved.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a semiconductor integrated circuit according to the present invention. Semiconductor integrated circuit LS in the same figure
I is formed on a single semiconductor substrate, such as single crystal silicon, by known bipolar integrated circuit manufacturing techniques.

The semiconductor integrated circuit LSI of this embodiment has functional blocks B1 to B29 each having a specific function.
It is composed of a combination of. That is, functional block B
1 to B29 are circuit blocks each having a specific function, and are registered in advance like standard cells or macro cells, from which one is selected according to the function desired by the user. The above semiconductor integrated circuit LSI
An input/output circuit IOB is provided at the periphery of the chip.

FIG. 2 shows an example of a unit logic circuit constituting each of the above functional blocks. For example, NAND is a Nand gate circuit, NOR is a Nor gate circuit, and SE
L is a selector circuit that selects one or two signals from a plurality of input signals; DEC is a decoder circuit that receives, for example, a 4-bit signal and forms 16 output signals;
The AU is, for example, a 4-bit arithmetic unit. The selector circuit SEL, decoder circuit DEC, and arithmetic operation unit AU are also constructed from a combination of unit gate circuits such as the Nant gate circuit and the NOR gate circuit. The functional blocks B1 to B29, etc. are constructed from combinations of unit circuits as representatively shown in FIG. 2. In this way, when one semiconductor integrated circuit LSI is configured by a combination of circuit blocks B1 to B29 etc. with specific functions prepared in advance, the minimum unit of logic gate circuit is determined by its fan-out number, wiring length, etc. The magnitude of the load determined by this is fixedly determined.

Focusing on this, the semiconductor integrated circuit LSI of the second embodiment
The minimum unit gate circuits constituting the circuit blocks B1 to 829, etc., are composed of the following combinations.

FIG. 3 shows a circuit diagram of an embodiment of the logic gate circuit when the load is light.

As a logic gate circuit with a light load, such as receiving input signals A and B and supplying the output signal C only to the input transistor Q3 of the next stage logic gate circuit,
Uses TL circuit. In other words, the NTL circuit on the front stage side is
It is composed of transistors Q1 and Q2 connected in parallel, a resistor R1 provided at a common collector of these transistors Q1 and Q2, a resistor R2 provided at a common emitter, and a capacitor C1. Input signals A and B are supplied to the bases of transistors Q1 and Q2, respectively. This minimum unit logic gate circuit operates as a NOR gate circuit because when the input signal A or B is at high level, these transistors Q1 or Q2 are turned on and form a low level output signal C from the commonly connected collectors. do.

The subsequent NTL circuit also consists of a two-man NOR gate circuit similar to the above, and the base of its input transistor Q3 is
The output signal C of the previous stage circuit is supplied as an input signal, and the output signal from another similar NTL circuit (not shown) is supplied to the base of the input transistor Q4. The subsequent NTL circuit includes transistor Q3. Output signal E is sent from the collector of Q4.

In such an NTL circuit, the operating voltage -VEEI is approximately -1
, 2V, and the output signals C and D are as follows.
As shown in FIG. 6, the high level H is set to O2, which is like a ground potential, and the low level L is set to -0.5V. The resistance ratio of the resistors R1 and R2 is set so as to form the above-mentioned level. In the case of a logic gate circuit with such a light load, by using an NTL circuit, the operating voltage and signal amplitude are small, so that ultra-high speed operation is performed with low power consumption.

FIG. 4 shows a circuit diagram of an embodiment of a logic gate circuit with a relatively heavy load.

A relatively heavy load is applied by receiving input signals A and B and supplying the output signal C to the input transistor Q3 of the next-stage logic gate circuit as well as to the input transistors of a plurality of other logic gate circuits (not shown). As a logic gate circuit, an emitter follower output circuit is added to the output section of the NTL circuit.

That is, the collector output signals of transistors Q1 and Q2 are transmitted to the base of emitter follower output transistor Q5. A load resistor R5 is provided at the emitter of this transistor Q5. In this application, the NTL circuit with an emitter follower output transistor added is called EF/NT.
It is expressed as an L circuit. When an emitter follower output circuit is added in this way, as shown in FIG. H becomes -0.8V and low level L becomes -1.3V. Therefore, the operating voltage is −
If it remains at 1.2V, the transistor Q5 will not be able to operate, so a large voltage such as 12V is used as the operating voltage -VEE2.

In this example, transistors Ql, Q2 and resistor R1
-VEEI is used as the operating voltage of the front-stage circuit consisting of R2 and capacitor C1. The reason for this is that the input signals A and B
This is because if the voltage is set to a large voltage such as -VEE,2 when is at the NTL level, the transistor Q1 or Q2 cannot be turned off when the signal A or B is at the low level L of about -0.5V. Therefore, when input signals A and B are formed by an EF/NTL circuit or an SPL circuit as described later, the operating voltage is -VEE2
It is done like this.

When the similar NTL circuit receives the output signal C formed by the EF/NTL circuit as described above, its input level is level-shifted as described above, so the operating voltage also changes accordingly to -VEE2 (-2V ). In other words, even in the same NTL circuit, depending on the circuit configuration of the previous stage, the operating voltage can be changed to -VE as shown in FIG.
EI, and there are also -VEE2 as shown in FIG. As shown in Figure 4, a simple configuration in which the operating voltage is supplied in accordance with the previous stage circuit enables high-speed signal transmission between logic gate circuits of different circuit types without providing a level shift circuit for level matching. be able to.

In other words, since the NTL circuit does not have a unique logic threshold voltage as described above, it can receive input signals that are biased toward the low level side as is, as shown in Figure 6, by simply switching the operating voltage as described above. becomes.

Note that when another NTL circuit with a light load receives the output signal E of this subsequent stage NTL circuit, its operating voltage is not -VEE2 (-2V) as in Fig. 4, but -VEEI (as in Fig. 3). 1.2V).

FIG. 5 shows a circuit diagram of an embodiment of the logic gate circuit when the load is heavy.

A logic circuit that has a heavy load such as receiving input signals A and B and supplying the output signal C to the input transistor Q3 of the next stage logic gate circuit as well as the input transistor of a logic gate circuit consisting of many other logic gate circuits (not shown). A so-called SPL circuit in which an emitter follower output circuit is replaced with a super pull-down output circuit is used as a gate circuit or an output circuit that sends an output signal from an external terminal included in the input/output circuit IOB of FIG. 1. That is, the collector output signals of transistors Q1 and Q2 are transmitted to the base of emitter follower output transistor Q5. An output transistor Q6 is provided at the emitter of this transistor Q5 in place of the load resistor R5. This transistor Q
The emitter side output signals of the transistors Q1 and Q2 are transmitted to the base of the transistor 6 via the capacitor C3. A resistor R is connected between the base and emitter of transistor Q6.
6 is provided, and a bias current is supplied from transistor Q7. A bias voltage is supplied to the base of the transistor Q7, and a base-emitter voltage V B E is supplied to the base of the transistor Q6. By providing the emitter follower output) transistor Q5 and the push-pull output transistor Q6,
The output signal can also be drawn from a high level to a low level at high speed, and a larger load can be driven at high speed. In this application, we refer to an NTL circuit using such a super pull-down output circuit as SPL (super pull-down output circuit).
(pull-down logic) circuit. In the case of such an SPL circuit, as shown in FIG. 6, the high level and low level of the above-mentioned NTL circuit are connected to the emitter of the output transistor Q5.

The level is shifted by the base-to-base voltage V□, and the high level H
When the voltage becomes 10.8V, the low level L becomes -1.3■.
Therefore, if the operating voltage remains at -1.2v, transistor Q5. Since Q6 cannot operate, a large voltage such as -2V is used as the operating voltage -VEE2. Note that the transistor Q8 provided on the output side is a level limiter transistor, and is used to prevent or reduce the occurrence of undershoot in the output signal C by supplying the limiter voltage VBL to its base. It can be omitted if undershoot is not a problem. When undershoot of the output signal C becomes a problem, it may be configured to prevent or reduce it using another circuit.

In this embodiment, transistor Q1. Q2 and resistor R1
-VEE2 is used as the operating voltage of the front-stage circuit consisting of R2 and capacitor C1. This is the input signal A, B
This corresponds to the case where, for example, is an output signal formed by the EF/NTL circuit or the SPL circuit. When the input signal A or B is at the NTL level, if a large voltage such as -VEE2 is applied, the transistor Q1 or Q2 will not be able to turn off when the signal A or B is at the low level L of about -0.5V. -VEE as shown in Figure 9
Use I.

When the above-mentioned SPL circuit is received by the above-mentioned similar NTL circuit, since its input level is level-shifted as above, the operating voltage is also -VEE2(-
2V) is used. That is, the same N
Depending on the circuit configuration of the previous stage, some TL circuits have an operating voltage of -VEEI as shown in Figure 3, and others have -VEE2 as shown in Figures 4 and 5. . As shown in Figure 5, a simple configuration in which the operating voltage is supplied in accordance with the previous stage circuit enables high-speed signal transmission between logic gate circuits of different circuit types without providing a level shift circuit for level matching. be able to. In other words, as mentioned above, since the NTL circuit does not have a unique logic threshold voltage as mentioned above, it simply switches the operating voltage as described above and receives the input signal that is biased toward the low level side as is as shown in Fig. 6. become something that can be done.

Note that when another NTL circuit with a light load receives the output signal E of this subsequent-stage NTL circuit, its operating voltage is not -VEE2 (-2V) as shown in Fig. 5, but -VEEI as shown in Fig. 9. (-1, 2V).

In this case, an NTL circuit with -VEE2 as the power supply voltage is used at the input section of the circuit block, and -VEE2 is used internally.
By using NTL with EI as the power supply voltage,
The power consumption of the circuit block can be reduced.

FIGS. 10(A), 10(B), and 10(C) show an embodiment in which logic circuits are used differently depending on the wiring length between circuit blocks that are connected to each other. FIG. 10(A) shows a case where the circuit blocks B1 and B3 shown in FIG. 1 are coupled via a wiring line 1 having a relatively short wiring length.

The load capacity of a wiring increases as the wiring length increases. Since the load capacitance of wiring line 1 is relatively small, the output circuit provided in circuit block Bl to drive it is N
It is considered to be a TL circuit. The input circuit provided in circuit block B3 is also an NTL circuit. Therefore, inter-block coupling as shown in FIG. 10(A) can be realized by a circuit configuration as shown in FIG. FIG. 10(B) shows a case where the circuit blocks B1 and B18 shown in FIG. 1 are coupled via a wiring liner 2 having a relatively long wiring length. Wiring L
Since the load capacitance of 2 is relatively large, the output circuit provided in circuit block Bl to drive this is EF/2.
It is considered to be an NTL circuit. The input circuit provided in circuit block B18 is an NTL circuit. Therefore, Fig. 10 (
Inter-block coupling as shown in B) can be realized by a circuit configuration as shown in FIG. FIG. 10(C) shows a case where circuit blocks B1 and B29 shown in FIG. 1 are coupled via a wiring L3 having a considerably long wiring length. Although the load capacitance of wiring 3 is large, the output circuit provided in circuit block Bl to drive it is SPL.
It is considered a circuit. The input circuit provided in circuit block B29 is an NTL circuit. Therefore, the inter-block coupling as shown in FIG. 10(C) can be realized by the circuit configuration shown in FIG. 5 or FIG. 9.

Figure 6 shows the NTL circuit, FE/NTL circuit, and SPL circuit.
An example of the circuit operating voltage and output signal level is shown in Figure 6.
Examples of operating voltages and output signal levels of the TL circuit, FE/NTL circuit, and SPL circuit are shown. Even between logic gate circuits with different levels, as explained above, the operating voltage -VEEl on the NTL circuit side is set to EF/N.
By switching the operating voltage of the TL circuit or SPL circuit to -VEE2, the above E F /NT L circuit or S
It is possible to directly receive the output signal of the PL circuit and form an NTL level output signal. Therefore, the NTL circuit whose operating voltage is -VEE2 has both a logic function and a level conversion function.

FIG. 7 shows a circuit diagram of another embodiment of the NTL circuit according to the present invention.

In this embodiment, reverse transistors in which the emitters and collectors of the input transistors Q1 to Q4 are reversed are used. That is, as shown in the schematic cross-sectional view of the device structure in FIG. Reference numeral 1 denotes a semiconductor substrate of P type. An N+ collector buried layer 2 is provided on its surface. An N− type epitaxial growth layer 4 as an element formation region is formed on its surface. This epitaxial growth layer 4, collector buried layer 2, and ohmic contact 7 constitute an emitter E. The epitaxial growth layer 4 is electrically isolated from other elements by a P-type isolation region 3.

When a reverse transistor is used as in this embodiment, the probability that the α rays LY generated from the package etc. will be irradiated to the joint between the collector 6 and the base 5 is reduced, and the seventh
The noise level generated in the output signals C and E of the NTL circuit shown in the figure can be reduced. That is, input signals A, B
When C is at a low level, transistors Q1 and Q2 are turned off, and the output signal C is at a high level. At this time, when the collector portions of the transistors Ql and Q2 are irradiated with α rays, carriers are generated correspondingly, and a current sinking circuit is isometrically added to the collector portions. As a result, the output signal C temporarily drops to a low level even though the transistors Ql and Q2 are in the off state. If a reverse transistor configuration is used as the input transistor as in this embodiment, the α-ray irradiation L
The probability that Y will be performed can be significantly reduced compared to the case of using a normal transistor configuration.

The noise generated by the α-ray irradiation is temporary, and the output signal C is restored to a high level by the current supply from the resistor R1. However, if the logic gate circuit receiving signal C constitutes a launch circuit, there is a risk that the latch circuit will be inverted and malfunction. Therefore, a circuit using a reverse transistor as an input transistor as described above may be limited to a circuit whose output signal is captured and held in synchronization with a timing signal or is supplied to a launch circuit. .

The effects obtained from the above examples are as follows. That is, (1) A circuit with a light load uses an NTL circuit, a circuit with a relatively heavy load uses an EF/NTL circuit, a circuit with a heavy load uses an SPL circuit to configure a digital information processing circuit, and the above-mentioned NTL Among the circuits, those that receive the output signal formed by the EF/NTL circuit or SPL circuit can achieve high-speed large-scale operation with low power consumption by using the operating voltage of the output circuit in the EF/NTL circuit or SPL circuit as its operating voltage. The effect is that a large-scale semiconductor integrated circuit can be formed.

(2) By switching the operating voltage as described above, logic gate circuits with different signal levels are directly connected, eliminating the need for a level conversion circuit and achieving high integration and high speed by taking advantage of the features of NTL circuits. This has the effect of realizing the

(3) As a transistor constituting the above NTL circuit,
By using a reverse transistor in which a normal emitter region is used as a collector and a collector region is used as an emitter, it is possible to obtain the effect that noise generated by α-ray irradiation can be reduced.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, a large-scale semiconductor integrated circuit LSI may be constructed not only by combining macro cells or standart cells as described above, but also by a gate array. In this case, as each logic gate, the elements necessary to configure the SPL circuit are built in, and depending on the load condition, an NTL circuit, an EF/EF/
An NTL circuit or an SPL circuit may be configured. Further, power supply lines -VEEI and VEE2 may be prepared, and either one of the power supply lines may be used depending on the input signal level.

For example, in FIG. 3, input signal A is formed by an NTL circuit, and input signal B is formed by an EF/NTL circuit or an SPL circuit.
When formed by a circuit, a fourth level conversion circuit is used.
It is sufficient to insert an NTL circuit such as the latter circuit in the figure to convert the signal to an NTL level and match the levels of the two input signals. Further, in FIG. 5, when the input signal A is formed by an NTL circuit, an emitter follower output transistor may be added to the NTL circuit as a level conversion circuit.

FIG. 11 shows a specific embodiment of the power supply voltage generation circuit 8 built into the semiconductor integrated circuit shown in FIG. 1, and an example of power supply wiring for supplying power supply voltage to the circuit blocks. A semiconductor integrated circuit formed on one chip is externally supplied with a ground potential and a power supply voltage of -3V. Based on these external power supply voltages, the power supply voltage generation circuit 8 generates internal power supply voltages (-1, 2V and -2V).

The power supply voltage generation circuit 8 includes a pre-stage circuit PC for generating voltages of -0, 4V and -1, 2 to ', and first and second level shift circuits LS1 for level-shifting these voltages, respectively. ．． LS2. Above-mentioned front stage circuit PC
is the transistor Qll-Q1 used to form the voltage of -0,4V above based on the power supply voltage of -3V.
4. Resistor R11R14 and diode D1, and the above -
Transistor Q1 used to configure an emitter follower circuit for level shifting a voltage of 0.4V
5 and a resistor R15 are provided. Level shift circuit LS
I and LS2 have the same configuration. For example, the level shift circuit LSI has a pair of transistors Q1 with a common emitter.
6 and Q17, common emitter resistance R18, collector resistance R16, R17゜emitter follower transistor Q18
．． Emitter resistor R20, resistor R19 for supplying current to level shift diode D2, and transistor Q1
Contains 9. With this circuit configuration, the level-shifted first internal power supply voltage (-1, 2V) is applied to the cathode of the level shift diode D2 by a forward voltage drop of the diode (0, 8V) from the input voltage 0.4V. is formed. This first internal power supply voltage (-1, 2V) is supplied to the first sub-interconnect LSI via the first main interconnect MLI. The cathode of the level shift diode D3 provided in the level shift circuit LS2 is connected to a second internal power supply voltage (-2, OV) is formed. This second internal power supply voltage (-2, OV) is supplied to the second sub-line SL2 via the second main line ML2.

Inside the circuit block 9, there are first and second circuits having the same configuration.
N “I” L circuit EF/NTL with emitter follower
I and EF/NTL2 are exemplarily shown. The power supply voltage terminal T1 of these circuits is selectively connected to the sub wiring SLI.
or to the terminal T2 coupled to the sub wiring SL2. As a method for selectively connecting the terminals, a method is used in which a through hole is formed between the wirings in a multilayer structure via an insulating film, and then the image wirings are connected with a conductor.

FIG. 12 shows the layout of power supply wiring for supplying internal power supply voltages (-1, 2V, -2V) to each circuit block within the chip. Corresponding to each logic cell column,
Multiple sub power supply wiring pairs (SLl, 5L2), (SLI
', SL2') are formed. A pair of main power supply wirings (MLI, ML2) is formed in common to these plurality of power supply wiring pairs. The sub power supply wiring and the main power supply wiring are through-hole T.
They are coupled via a conductor formed in H. In addition, the first
Although the ground potential supply wiring is omitted in FIG. 2, it can be formed on each logic cell similarly to the layout of the sub-power supply wiring described above.

Other configuration examples of NTL circuits and structures in which semiconductor chips to which the present invention is applied are packaged are described in U.S. Patent Application M, Usami El Al-5erialN.
o, 330.461 is incorporated by reference.

The present invention can be widely used in digital integrated circuits configured using bipolar transistors.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, circuits with light loads use NTL circuits, circuits with relatively heavy loads use EF/NTL circuits, and circuits with heavy loads use SPL circuits to configure digital information processing circuits. EFF/NTL
The circuit or SPL circuit that receives the output signal formed by the EF/NTL circuit or the
By using the operating voltage of the output circuit in the L circuit, a large-scale semiconductor integrated circuit device with low power consumption and high speed can be formed.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of an embodiment of a semiconductor integrated circuit according to the present invention, FIG. 2 is a logic circuit diagram showing an example of a unit circuit constituting each of the above functional blocks, and FIG. FIG. 4 is a circuit diagram showing an example of a logic gate circuit when the load is relatively heavy. FIG. 5 is a circuit diagram showing an example of the logic gate circuit when the load is relatively heavy. FIG. 6 is a circuit diagram showing one embodiment of the gate circuit. FIG. 6 is a conceptual diagram for explaining the signal levels and operating voltages of the NTL circuit, EF/NTL circuit, and SPL circuit. FIG. 7 is the NTL circuit according to the present invention. A circuit diagram showing another embodiment of the circuit, FIG. 8 is a schematic cross-sectional view of the element structure showing one embodiment of the input transistor, and FIG. 9 shows another embodiment of the logic gate circuit when the load is heavy. 10(A), 10(B) and 1o(C) are diagrams showing other embodiments of the present invention, and FIG. 11 is a circuit diagram showing a circuit diagram built in the semiconductor integrated circuit shown in FIG. 12 is a diagram showing an example of the power supply wiring for supplying the power supply voltage to the circuit blocks, and a diagram showing an example of the power supply wiring for supplying the internal power supply voltage to each circuit block in the chip. FIG. LSI...large-scale semiconductor integrated circuit device, IOB...input/output circuit, B1-B29...functional block, NAND
...Nant gate circuit, NOR...Nor gate circuit,
SEL/selector circuit, DEC...decoder circuit, A
U Arithmetic operation unit, 1. Substrate, 2. Collector buried layer, 3. Isolation region, 4. Epitaxial growth layer (emitter), 5. Base region, 6. Collector, 7. Ohmink contact, 8. Power supply voltage generation circuit, 9. circuit block. Figure section ℃ Taste

Claims (1)

[Claims] 1. First NTL driven by first negative power supply voltage
an emitter follower output circuit driven by a second negative power supply voltage lower than the first negative power supply voltage and for supplying the output signal of the first NTL circuit to the first wiring; The second NT is driven by the second negative power supply voltage, with the signal supplied via the wiring as an input signal.
A semiconductor integrated circuit characterized by having an L circuit. 2. Third and fourth NTL circuits driven by the first negative power supply voltage, and a second NTL circuit for coupling the output terminal of the third NTL circuit and the input terminal of the fourth NTL circuit. 2. The semiconductor integrated circuit according to claim 1, further comprising a wiring line of claim 1, further comprising a load capacitance of said first wiring line that is larger than a load capacity of said second wiring line. 3. An SP including first and second bipolar transistors connected in series that operate complementary to each other by signals whose phases are inverted with each other and are driven by the second negative power supply voltage.
L circuit; and a third wiring for coupling an output terminal of the SPL circuit and an input terminal of a fifth NTL circuit driven by the second negative power supply voltage, and further includes the third wiring. 3. The semiconductor integrated circuit according to claim 2, wherein the load capacity of the first wiring is larger than that of the first wiring. 4. A power supply voltage forming circuit for forming the first and second negative power supply voltages based on a third negative power supply voltage lower than the second negative power supply voltage; 4. The semiconductor integrated circuit according to claim 3, wherein the negative power supply voltage is supplied from outside the semiconductor integrated circuit. 5. Claim 3, further comprising a sixth NTL circuit whose input terminal is supplied with the output signal of the fifth NTL circuit and is driven by the first negative power supply voltage. The semiconductor integrated circuit described. 6. The semiconductor integrated circuit includes a plurality of circuit blocks, the emitter follower output circuit forming an output circuit of the first circuit block, and the second NTL circuit forming an input circuit of the second circuit block. A semiconductor integrated circuit according to claim 5, characterized in that: 7. The SPL circuit constitutes an output circuit of the third circuit block, the fifth NTL circuit constitutes an input circuit of the fourth circuit block, and the sixth NTL circuit constitutes the fourth circuit block. 7. The semiconductor integrated circuit according to claim 6, comprising an internal circuit. 8. First NT driven by first negative power supply voltage
an emitter follower output circuit driven by a second negative power supply voltage lower than the first negative power supply voltage and for supplying the output signal of the first NTL circuit to the first wiring; a second NT that uses the signal supplied via the first wiring as an input signal and is driven by the second negative power supply voltage;
L circuit, and third and fourth circuits driven by the first negative power supply voltage.
and a second wiring for coupling the output terminal of the third NTL circuit and the input terminal of the fourth NTL circuit, and further the wiring length of the first wiring is as described above. A semiconductor integrated circuit characterized in that the length of the second wiring is longer than that of the second wiring. 9. An SP including first and second bipolar transistors connected in series, which operate complementary to each other by signals whose phases are inverted to each other and are driven by the second negative power supply voltage.
L circuit; and a third wiring for coupling an output terminal of the SPL circuit and an input terminal of a fifth NTL circuit driven by the second negative power supply voltage, and further includes the third wiring. 9. The semiconductor integrated circuit according to claim 8, wherein the wiring length is longer than the wiring length of the first wiring. 10, a power supply voltage forming circuit for forming the first and second negative power supply voltages based on a third negative power supply voltage lower than the second negative power supply voltage; 10. The semiconductor integrated circuit according to claim 9, wherein the negative power supply voltage is supplied from outside the semiconductor integrated circuit. 11. Claim 9, further comprising a sixth NTL circuit whose input terminal is supplied with the output signal of the fifth NTL circuit and driven by the first negative power supply voltage. The semiconductor integrated circuit described. 12. The semiconductor integrated circuit includes a plurality of circuit blocks, the emitter follower output circuit forming an output circuit of the first circuit block, and the second NTL circuit forming an input circuit of the second circuit block. A semiconductor integrated circuit according to claim 11, characterized in that: 13. The SPL circuit constitutes an output circuit of the third circuit block, the fifth NTL circuit constitutes an input circuit of the fourth circuit block, and the sixth NTL circuit constitutes the input circuit of the fourth circuit block. 13. The semiconductor integrated circuit according to claim 12, comprising an internal circuit.