JPH0456516A - Error check circuit and a/d converter - Google Patents

Abstract

PURPOSE:To attain error detection of a matrix type encoder with simple constitution at high speed by employing MOSFETs and a resistor to detect the number of signal lines whose level is logical H in a current detection way at first, and processing the result in a voltage processing way. CONSTITUTION:Assuming the resistance of a resistor 15 as R, the current of a drain flowing thereto when an H level signal enters a gate of an N-channel MOSFET 14 through a signal line as IH and the current of a drain flowing thereto when an L level signal enters as IL, in a level detection section 19 deciding an output level through the summation of input signals by means of eight N-channel MOSFETs 14 and the resistor 15. When an error signal is inputted to the level detection section 19 in a way that two input signal lines or over are at an H level, since the level detected by the level detection section 19 reaches R(2IH+6IL) or over, the output of a comparator 16 goes to L and the output of a comparator 17 goes to H in a logic circuit section 20, then the output of a NAND circuit 18 goes to H to discriminate the presence of an error. Thus, an input error to a matrix encoder 13 is detected in a high speed processing time.

Description

[Detailed Description of the Invention] Industrial Field of Application Four Friends of the Present Invention Error detection circuit and A/D for semiconductor electronic circuits
Related to D converter: Conventional technology (1) As an example of a conventional matrix encoder,
FIG. 10 shows an example of a 3-bit binary code matrix encoder. In the figure, 101, 10
2, 103 is the bit IL for coding 104 is a constant current source This encoder is one of the seven input signals
Only the book inputs H (high voltage, written like this from now on) and codes the bit line accordingly. For example, if input 2 is H and all others are L (low electricity, written like this from now on), only bit line 102 is input. becomes H, and the output is [010](
[Outputs 3, 2, 1] (in the order of output 3, 2, 1)) However, there are cases where an error input is made to the matrix encoder due to an error in the previous stage circuit connected to the input of this matrix encoder. . For example, if input 3 is now H and [011] is being output, then with the next input signal, input 4 will become H and input 3 will become L. Input 3 falls slowly and input 3, 4
If both become H and an input error occurs, the output will be [111], which is a large error of 3 in decimal compared to the actual correct output of [100]. . As a countermeasure against such errors, for example, in matrix encoders used in A/D converters, a method is often used to reduce errors by using Gray code instead of binary code for coding, as shown in Figure 11. An example of a 3-bit Gray code matrix encoder is shown. Since each component is the same as in Fig. 10, the same number will be given and detailed explanation will be omitted. However, in Fig. 11, if the above error occurs,
In other words, the board is originally where only input 4 is H and everything else is. If both inputs 3 and 4 are H, the output will be [110]. This is when only input 4 is H. It is not an error because it matches the output [110] of (℃) On the contrary, when only input 3 should be H, input 3.
When both 4 become H, the output becomes [110,
The power of an error compared to the original correct output [010] When converted to a decimal number, there is only an error of 1 (℃) Gray code, compared to binary code, Gray code is very effective in reducing errors when mixing data, and is often used as a countermeasure against errors.Also, Gray code is effective in mixing data above and below the input signal.When the input signal is lost As a countermeasure for such a case, there is a method of coding the input signal with two H signals (patent application number 62-105138).4 Figure 12 shows an example of this method. The component is the 10th
Since it is the same as that in FIG. 11, the same numbers are given and detailed explanation is omitted. In FIG. 12, the input signals are encoded with the front and rear two input signals being H. For example, the first
In the example in Figure 1, when input 4 becomes H, the output is [
110], when input 5 becomes H, the output is [111]
In the example of Figure 12, inputs 3 and 4 become H and the output is [110], and inputs 4 and 5 become H and the output is [111]. The number of times when the signal becomes 2 H and coding is performed Even if a loss of input signals occurs, the probability of losing both signals at the same time is very small or even.The remaining input signal is coded and the output is completely 0 4. Example (
L Now, even if an error occurs and input 4 becomes L when inputs 4 and 5 should be H and [111] is output, the number coded by input 5 will be the output [101] So, if you convert the correct value to a decimal number, there will only be an error of 1, t,X.

As mentioned above, errors in conventional matrix encoders can be countered by devising coding methods. (2) As an example of a conventional parallel A/D converter, Fig. The block diagram of a D converter is shown. In the same figure,
71 is the same section where the reference voltage is generated. 72 is the comparator row 173.
is the logic circuit No. 1, 74 is a matrix encoder,
75 is a gray binary conversion block. 76 is an output buffer. 4 In the parallel A/D converter configured as above,
First, the reference voltage and the input voltage are compared by the comparator array 72, and then the potential level of the input voltage with respect to the reference voltage is detected by the logic circuit array 73, and the matrix type encoder 74 encodes it into a -H Gray code. The code is converted into a binary code by the binary conversion circuit 75 and output from the output buffer 776.In order to reduce coding errors in the encoder, it is common to use a Gray code.The code is directly coded into a binary code by the encoder and output. Problems to be Solved by the Invention (1) However, in the case of a matrix encoder that only takes measures against errors by using the coding techniques described in the prior art (1), the output data is normal. When using the Gray code, which had the problem of being recognized as a correct value even if the value had an error, it was quite effective in mixing the signals before and after the correct input signal. In the example of Figure 11, where input 2 should be H as the correct input, input 1 or input 3 before and after it would be If input 2 becomes H, the ζ output will be [011] in any case, and will not be an error output (if an input error occurs such that input cuff becomes H together with input 2, the output will be [011]). 111] and for the correct output,
In decimal terms, the output will be 3 larger. When a large error occurs like this, there is no way to determine whether an error is included from the output data, and there is no way to determine whether the output data is correct and is output to the subsequent circuit. In this circuit, no countermeasures were taken against error data.9 Atsushi Konota
In order to take effective measures against error data output from a matrix encoder, a circuit for detecting errors in the matrix encoder is required. The problem with A/D converters is that no effective countermeasures have been taken to prevent conversion errors.The occasional conversion error causes a significant deterioration of the conversion characteristics of the A/D converter. It is called a conversion error. It is an error that occurs when the input to the encoder is incorrect due to an error in the encoder input section, which is a comparator or the next logic circuit. In the example of the 3-bit binary code matrix type encoder shown in FIG. 10 explained in Prior Art (1), if input 2 is H and all others are L, the bit line 10
However, due to an error in the comparator or the next logic circuit, if not only input 2 but also input 6 becomes H, bit lines 102 and 103 become H. The output is [110
]. The conversion characteristics at this time are shown in FIG. In the figure, the dotted line is the correct conversion characteristic, and the solid line is the actual conversion characteristic. The input power of the encoder shown in the figure is correct when input 6 should be H. Even though it shows the case where all the inputs are L due to an error, the characteristics of the A/D converter are very poor due to conversion errors like this that occasionally occur. It becomes a thing.

In view of the above, an object of the present invention is to provide an error detection circuit for a matrix encoder that can take effective measures against errors.
It is an object of the present invention to provide an A/D converter that can make the conversion characteristics of the D converter as close to ideal characteristics as possible even when a conversion error occurs.4 Means for Solving the Problems The present invention (1) solves the above-mentioned problem (1).The present invention (1) is composed of a gate element array whose gate is connected to each input signal line of a matrix type encoder, and a load driven by the gate element array. a potential detection unit that outputs a potential or current corresponding to the number of input signal lines whose potential is logically 1; and a potential detection unit that determines the number of input signal lines whose potential is logically 1 based on the output of the potential detection unit. The present invention (2) is an error detection circuit characterized by having a circuit that solves the above-mentioned problem (1). An approach to solving the above-mentioned problem (2) is to provide an error detection circuit configured with a circuit and determining an error by adding up the number of input signal lines whose input potential is logically 1.The present invention (3) is characterized by having an error detection circuit connected to the output of the comparator array or the output of the next logic circuit, and a circuit that corrects the output data by receiving the error signal from the error detection circuit. Tosube is an A/D converter with a fully parallel or partially parallel circuit configuration.
Effect of the present invention With the configuration (1), the present invention uses one gate element for each load and input signal line to detect a potential corresponding to the number of input signal lines that is logically 1, and easily calculate the potential. The present invention also provides (2)
With this configuration, errors are detected by forming an adder using a logic circuit and counting the number of input signal lines that are logically 1 in the matrix encoder.

According to the configuration (3), the present invention includes an error detection circuit and a data correction means controlled by the output of the error detection circuit, so that when a conversion error occurs, the error data can be outputted. Embodiment (Embodiment 1) Fig. 1 shows a parallel A/D converter in the first embodiment of the present invention.
This figure shows an input error detection circuit for a 3-bit matrix encoder used in a converter.
Comparator data 1 and 12 of the D converter are comparator row 1
Logic circuit Tl1 that determines the position of the input potential from the output of
113 is a matrix encoder, and %14 is an N-channel MO8FET that receives the input signal of the encoder.
It is. Eight N-channel MO3FETs 14 and a resistor 15 constitute a potential detection unit 19 that determines the output potential by adding each input signal with current, and the output is detected by comparators 16 and 17 and a NAND logic circuit 18 to detect errors. The operation of the error detection circuit of this embodiment configured as described above will be explained below. Let IN be the value of the drain current that flows when an H signal is input from the signal line to the gate of N-channel MO8FET14, and IL be the value of the drain current that flows when an L signal is input.In this case, IN>IL. be. now,
Suppose that only one of the input signal lines of the encoder becomes H and coding is performed, and the others are an error. In a normal case, only one of the input signal lines of the encoder becomes H and all others Because of this, a current of (IH+7IL) flows through the resistor 15, and a current of R(I14+7IL) flows through the terminals connected to the comparators 16 and 17.
) Even if the potential of VTH potential force (comparator 17
If the potential of VTL is applied to each of the lower terminals, then R(IN+7 IL) <VTH<R(2IH+6 I
L) If 8RIL<VTL<R(IN+7IL), then a In normal case, the potential detected by the potential detection section 19 is R(IN+7IL).Comparators 16 and 17i table Both upper terminals becomes high potential, both outputs become H, and the output of the NAND logic circuit 18 becomes L. If an error signal is input in which two or more of the input signal lines are H, then the potential detection section The potential detected at 19 must be equal to or higher than R (2In+6 IL). Since the output of comparator 16 is L and the output of comparator 17 is H, the output of NAND circuit 18 is H and it can be determined that there is an error. Next 1 If an input error occurs in which all the input signal lines are connected, the potential detected by the potential detection section will be 8RIL. The output of circuit 18 becomes H, and in this case as well, it can be determined that there is an error.However, if two of the input signals become H and the encoder performs coding, then C friend R (2IN + 6 IL) <VTH<R(3IH+
5 IL) R(IN+ 7 IL) <VTL<R
(2I++ 6 IL), and other cases can also be handled by changing the VTH and VTL settings.In the case of the example shown in Figure 1, the processing speed is Circuit 2 gates and MOSF
It only takes time for one gate to pass through the ET, and the number of elements can be configured with three logic circuit gates, eight MOSFETs, and one resistor. As a result, only one MOSFET is added for each input signal line, and the processing speed is L. Since the number of gates passing through remains the same, there is almost no slowdown of 1.% As shown above, ζ is H. By processing the detection of the number of signal lines using a voltage that is once added with a current using a MOSFET 14 and a resistor 15, it is possible to detect errors at high speed with a simple configuration.In this example, as a gate element Using MOSFET 1. % A resistor can be used as a load (for example, the gate element can be implemented with a bipolar circuit, etc., and the load can be configured with another circuit (Example 2). Figure 2 GEL Second example of the present invention 21 shows an input error detection circuit for a 3-bit matrix encoder used in a parallel A/D converter.
22 is a full adder for configuring the error detection circuit 21. 23 is also a half adder.Other configurations are the same as in FIG. 1. 6 Identical components are given the same numbers and detailed explanations are omitted. FIG. 5 shows an example of a full adder, and FIG. 6 shows an example of a half adder. In both figures, 5
1 is an AND logic circuit, 52 is an exclusive logic circuit, and 53 is an OR logic circuit.Regarding the adder! Since this is a known technology, detailed explanation will be omitted, but the operation of the error detection circuit configured as above will be explained.The 3-bit encoder has eight input signal lines, only one of which is If you try to perform coding based on the following, when only one of the eight input lines to the error detection circuit 21 is H, it is normal, and otherwise it is detected as an error.
In this case, 1 bit 8 is used as the error detection logic circuit 21.
It constitutes an input adder, and only this output terminal l is H.
It is normal only when all other output terminals are L, and all others are recognized as errors. For example, if two input wires to the encoder 13 are H, output 2 of the error detection circuit 21 is H and others are recognized as errors. If all of the input lines become L, it can be detected as an error, but if up to three input lines become H, it can be detected at output 1 and output 2, and there is no need to calculate outputs 3 and 4. Even if the circuit can be omitted, in a normal circuit, only one H input signal is used for coding.The possibility of an error that results in 4 or more H is extremely low, so only output 1 and output 2 should be calculated. However, according to the present embodiment, it is possible to detect errors by detecting the number of H signal lines and adding them using an adder using a logic circuit. 1 and Example 2
In particular, the error detection circuit of the present invention is an error detection circuit for a matrix encoder used in an A/D converter. can be used (Embodiment 3) Figure 3 (Friend) is a configuration diagram of a parallel A/D converter in an embodiment of the present invention. Since the other configurations are the same as those in FIG. 7, the same components are given the same numbers and detailed explanations are omitted. 4 The A/D of this embodiment configured as above The operation of the converter will be explained below. First, if a normal conversion is performed, the error detection circuit 3
If error detection is not performed in step 7, the output data correction circuit 38 does not perform any correction on the converted data sent from the gray binary conversion circuit 75 and directly sends it to the output buffer 76 for output. Next, when a conversion error occurs, the error detection circuit 37 detects the error and sends an error signal to the output data correction circuit 38. When the error signal is received, the output data correction circuit 38 converts the signal to ζ. After making appropriate corrections to the conversion data sent from the converter, it can be sent to the output buffer 76 and output.If this is done, conversion errors that occur occasionally will cause the conversion characteristics to become large, as shown in the characteristic diagram of the conventional example in Figure 9. As described above, it is possible to obtain characteristics close to ideal characteristics without deteriorating the characteristics.According to this embodiment, it is possible to detect when an error occurs in the A/D converter, and apply appropriate information to the error data. By adding appropriate corrections, large conversion errors can be prevented,
Although conversion characteristics close to ideal characteristics can be obtained (Example 4) Fig. 4 41 Parallel type A/D in an example of the present invention
This is a configuration diagram of the converter. In the figure, 37 is an error detection section, 48 is a data storage section, and 49 is an output control circuit.The other configurations are the same as in FIG. 7, so the same components are 4. The A/D converter of this embodiment configured as described above has the same number and its detailed explanation is omitted.
The operation will be explained below. First, if normal conversion is performed and no error is detected by the error detection circuit 37, the data storage circuit 4
8 stores the converted data for which no error was detected, and the output control circuit 49 outputs the converted data as is.If an error occurs in the next conversion, the error detection circuit 37 detects an error and outputs an error signal. If an error signal is sent to the data storage circuit 48 and the output control circuit 49, the data storage circuit 48 (main) does not store the converted data and continues to hold the previous data, but the output control circuit 49 (main When an error signal is received, the current conversion data is not output, but stored in the data storage circuit 48.The previous conversion data is output to the output buffer 76.In other words, the operation of the A/D converter As a C friend, when a normal conversion is performed, the converted data is output as is, and when a conversion error occurs, the error detection circuit operates so as to output the previous converted data without outputting the converted data. Regarding the configuration of 37, the error detection circuit power shown in Figure 1 or the power that can be configured as shown in Figure 2 (it can also be realized with an appropriate circuit). If possible, it can be configured with a small number of memory circuits, and the increase in the number of elements can be suppressed slightly.Also, the normal output buffer7
6 often includes a data latch function (this can also be achieved by prohibiting data capture here, and by adopting this configuration, the configuration can be easily configured without increasing the number of elements.Output control circuit Regarding 49, all we need is a switch circuit for the number of L bits and a control circuit that switches the switches in response to an error signal, so it does not impose a large burden on the number of elements, so the system configuration this time is configured with a simple circuit. The conversion characteristics of the A/D converter of this example are shown in Figure 8.The dotted line is the conversion characteristic of an ideal A/D converter, and the solid line is the conversion characteristic of this example. As shown in the example characteristic diagram, it is assumed that a similar error occurs in the range of input voltages a-b and c-d (in this case, even if an error occurs, the correct converted value is I LSB
L does not deviate, and the curve is very smooth compared to the characteristics of the conventional example shown in Figure 9.The characteristics are close to the ideal curve.With this invention, the input to the A/D converter can be made smooth like this. This method is very effective when the signal changes, and is effective when used as an image signal, for example.

As described above, according to this embodiment, large conversion errors can be prevented by detecting when an error occurs in the A/D converter and outputting the previous conversion data instead of the error data. , although smooth conversion characteristics can be obtained (Example 5).
This is a configuration diagram of the converter. In the figure, 37 is an error detection apposition, 131 is an operation apposition 132, 133, 134
135 is a data latch circuit; 135 is an output control circuit; and 4. Other configurations are similar to those shown in FIG. The operation of the A/D converter of this embodiment configured as described above will be explained below. First, the converted data output from the gray binary conversion circuit 75 enters the data latch circuit 132, and the data is input to the data latch circuit 132 by the clock.
3, 134 and pass through the output control circuit 135,
Here, if the error detection circuit 37 detects an error, when the error data reaches the data latch circuit 133, the arithmetic circuit 131 takes in the data in the data latch circuits 132 and 134. a This unit 134 holds the conversion data immediately before the error data in 133, and 1
Even if the next conversion data is held in 32, the arithmetic circuit 131 calculates the average value of the two captured data.Then, when the error data is moved to the data latch circuit 134 by the clock, it is output. In the control circuit 135, the switch is changed to send the average value of the data before and after the error data calculated by the arithmetic circuit 131 to the output buffer without sending the error data in 134 to the output buffer. Arithmetic circuit 131 C & Power that may perform arithmetic operations only when an error signal is detected (Always perform arithmetic operations regardless of the presence or absence of an error 1.% Select which data is output by the output control circuit 135 depending on the error signal) The conversion output characteristics of this embodiment are shown in Figure 14.The horizontal axis is time;
The vertical axis is the conversion output, and if an error occurs between a and b and between c and d, if the data changes monotonically before and after that, like between a and b, the 3 tables can be corrected for 4 cmd. Assuming that the correct conversion output is 6, if you take the average before and after, it will be 5, which is a value that is quite close to the correct data. For data that changes drastically, this correction will give the correct data. In that case, ζ may be quite different. For example, increase the number of data before and after the correction, judge the tendency of the data, and calculate by weighting rather than just an average value. It is also possible to change the correction method (the arithmetic circuit 131 becomes quite complex and the number of stages of the data latch circuit needs to be increased). In some cases, just taking the average value can be expected to be quite effective.

As described above, according to this embodiment, ii) By detecting when an error occurs in the A/D converter and performing correction using the data before and after the error data, smooth conversion close to ideal characteristics can be achieved. As is clear from the above description, according to the present invention, (1) input errors in a matrix encoder can be detected with a small number of elements and a high processing time. (2) By configuring the adder with logic circuits, it is possible to detect errors in matrix encoders; By detecting conversion errors in the converter and adding appropriate correction to the error data, it is possible to prevent deterioration of the conversion characteristics of the A/D converter due to accidental conversion errors, and its practical effects are as follows: Thick (℃

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of an error detection circuit in a first embodiment of the invention. FIG. 2 is a schematic diagram of an error detection circuit in a second embodiment of the invention. Figure 4 shows the configuration of a parallel type A/D converter in an embodiment of the present invention. Figure 5 shows the circuit of the full adder circuit. schematic diagram
Fig. 7 is a configuration diagram of a conventional parallel type A/D converter. Fig. 8 is a conversion characteristic diagram of a parallel type A/D converter in an embodiment of the present invention. Fig. 9 is a diagram of a conventional parallel type A/D converter. Figure 10 is a circuit diagram of a conventional 3-bit binary code matrix encoder. Figure 11 is a schematic diagram of a conventional 3-bit Gray code matrix encoder.
FIG. 12 shows a circuit diagram of a Gray code matrix encoder based on conventional 3-bit composite input coding. FIG. 13 shows a configuration diagram of a parallel A/D converter according to an embodiment of the present invention. 14... N-channel MO8FET, 15... Resistor 16, 17...
・Convalley Hisashi 18...NAND logic expansion 19・
...Potential detection circuit 20...Logic circuit block 21...Logic circuit for error detection 22...Full adder circuit 23...
Half adder circuit 37...Error detection circuit 38...
Output data correction same section 48...Data storage same section 49.
135... Output control same section 131... Calculation same section 13
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Claims (5)

[Claims] (1) The number of input signal lines that are composed of a gate element array with a gate connected to each input signal line of the matrix encoder and a load driven by the gate element array, and whose input potential is logically 1. an error detection circuit comprising: a potential detection section that outputs a potential or a current according to the potential detection section; and a circuit that determines the number of input signal lines whose potential is logically 1 from the output of the potential detection section. . (2) An adder that receives each input signal line of the matrix encoder as an input is configured with a logic circuit, and the number of input signal lines whose input potential is logically 1 is determined by addition, thereby determining an error. error detection circuit. (3) It is characterized by having an error detection circuit connected to the output of the comparator array or the output part of the next logic circuit, and a circuit that corrects the output data by receiving the error signal from the error detection circuit. An A/D converter with a fully parallel or partially parallel circuit configuration. (4) an error detection circuit connected to the output of the comparator array or the output of the next logic circuit; and if there is no error signal from the error detection circuit, store the data;
a data storage circuit that does not store data and retains the previous data when there is an error signal, and outputs the data as it is when there is no error signal from the error detection circuit;
Claim 3, further comprising an output control circuit that outputs the data stored in the data storage circuit without outputting the error-detected data when there is an error signal. A/D converter. (5) If there is an error detection circuit connected to the output of the comparator array or the output part of the next logic circuit and an error signal from the error detection circuit, capture the data before and after the error-detected data. , an arithmetic circuit that performs calculations for correction, a data holding circuit that temporarily holds data before and after the error data necessary for the calculation, and an error signal from the error detection circuit, if any. A/C according to claim 3, further comprising an output control circuit that outputs data corrected by the arithmetic circuit without outputting error-detected data.
D converter.