JPH04564A - Logical simulation system - Google Patents

Abstract

PURPOSE:To shorten a processing time and to improve the using efficiency of a memory by replacing all logical elements by interface gates each of which has an input and an output corresponding to an input terminal and an output terminal and executing simulation. CONSTITUTION:An interface gate forming means 11 forms a gate having an input and an output corresponding to the input and output terminals of a logical element to be simulated and forms circuit data 101. A logical operation defining means 12 defines the logical operation of an objective logical element by program language and forms logical operation description 102. When a change is generated in the input status value of the gate, a logical gate evaluating means 13 refers and evaluates the description 102 and determines the operation of the logical element. When a change is generated in the status value of the output terminal of the logical element, a status change propagating means 14 transmits the change to the gate and then propagates and registers the status change to the fan-out destination of the gate. Thus, the processing time can be shortened and the using efficiency of the memory can be improved.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a logic circuit simulation method.

[Technological environment]

Advances in conventional semiconductor technology have increased the scale of LSIs,
Its application fields are also rapidly expanding.

Furthermore, the manufacturing style of LSIs has shifted from high-volume production of a small number of products to high-mix low-volume production, and product life cycles are also becoming shorter. Along with this, design support systems that can realize necessary functions quickly and correctly are becoming more essential than ever before, so logic simulators that verify logic and timing before actually manufacturing LSIs are becoming more and more essential. developed and widely used.

Early logic simulators ANDed all the elements in the circuit.
, OR, flip-flop, etc. - gate level simulators that perform simulations by decomposing them into gates were common, but as LSIs have become larger and more complex, the functions of the elements in the circuit have been described in a special language. Higher level simulators such as a functional level simulator that executes simulation for each element or an MIX level simulator that is a mixture of a gate level simulator and a functional level simulator have been developed, and some of them have been put into practical use.

[Prior Art] A conventional upper level simulator has a logic operation definition means for defining a logic operation for each logic element existing in a circuit to be simulated, and an input state value storage means for storing input state values of the logic elements. and output state value storage means for storing an output state value of the logic element; logic gate evaluation means for determining the operation of the logic element by the logic operation definition means when a change occurs in the input state value; When a change occurs in the state value of the output terminal of a logic element, the change occurs,
and state change propagating means for propagating the state change to a fan-out destination of the output terminal.

[Invention or problem to be solved]

The conventional upper-level simulator described above manages input state values and output state values for each logic element, so in order to simulate a logic element with terminals on any side, a pointer is stored in the child structure. 2, and some of the data is of variable length, or a large area is reserved for storing the state values of input and output terminals. The disadvantages are that data access requires pointer processing, which takes a lot of time, and memory usage efficiency deteriorates.

[Measures to solve problems]

The logic simulation method of the present invention includes a logic operation definition means for defining a logic operation for each logic element existing in a logic circuit to be simulated, and an interface case with one input and one output for each input terminal and output terminal of the logic element. −
an interface gate 1- generating means for generating an interface gate 1-, and a logic gate that determines the operation of the logic element to which the interface gate belongs from the logic operation defining means when a change occurs in the input state value of the interface gate. evaluation means and the state value ζ of the output terminal of the logic element;
and state change propagation means for transmitting the state change to the front d pin interface gate connected to the output terminal when this change occurs, and further propagating the state change to the fan-out destination of the interface gate. It is realized by twisting.

〔Example〕

Next, embodiments of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a flowchart showing one embodiment of the logic simulation method according to the present invention. In the same figure, the logic shimmy +-1,- John method is inter-]:- gate/generation means 11 and 7 brass physical operation definition method? ',Q
12 and 2 logic gate evaluation means 13, and state change propagation means 14.

The interface gate generation means 11 connects logic elements (ND to 5,
OR,, FF'1lj)(') Generates an interface gate with 1 input and 1 output for each input terminal and output terminal,
Create circuit data 10l.

The payroll definition means 12 defines the logical operation of a logic element existing in a logic circuit to be simulated using a programming language, and creates a logical operation description 1.2.

When a change occurs in the input state value of the interface gate, the logic gate evaluation means 13 refers to and evaluates the logic operation description 102 of the interface gate t, the increasing logic, and the child, and evaluates the operation of the logic element i. Determine. State change propagation means 14i, 1 When a change occurs in the state value of the output terminal of the logic element, the state change is transmitted to the interface gate 1- connected to the output terminal, and further to the fan gate of the interface gate. Propagate state change to the destination 5
register.

The interface gate generation means 1] and logic operation definition means 12 correspond to logic simulation preprocessing, and the logic gate evaluation means 3 and state change propagation means 1.1 correspond to a logic simulation execution unit.

FIG. 2 is an explanatory diagram showing an example of the interface gate generating means 11 shown in FIG. 1. The logic element 2 shown in FIG. 2(a) has a plurality of interface gates (input side) 22, as shown in FIG. The interface gate (output side) 23 is modeled. In the same figure (b), the dotted line part does not exist in the circuit data, but indicates that there is a logic operation definition file to be referred to when the input state is registered in the interface gate (input side) 22. There is.

Similarly, the circuit shown in FIG. 3(C) is modeled as the circuit shown in FIG. 3(d).

FIG. 3 is an explanatory diagram showing an example of the logical operation defining means 12. In the figure, numeral 31 indicates a logic element, and numeral 32 indicates a logic operation description. In the same figure (a, ), three logic elements have four input terminals (A, B, C).

D), there are two output terminals (Ql, Q2), and as an operation, the value obtained by calculating the logical product of B, C, and D and the logical sum of A is sent to Ql, the logical product of A, , B, and C, and the logical sum of D. The value obtained by calculating the logical sum is Q
2, logical behavior description 32 is obtained (see Figure 3(b)). Here, +' is the logical sum, "×"
is a logical product.

In this way, when the logic element is a combinational circuit, the operation can be expressed using pool algebra. Also, if the logic element has an internal state like a sequential circuit, that is, if it cannot be determined from only the state value of the output terminal or the state value of the input terminal, define variables related to the internal state in the behavioral description. This makes it possible to describe even complex operations.

FIG. 4 is a flowchart showing the processing operation of the logic gate evaluation means j3. (13 is applied to all the logic elements existing in the logic circuit to be simulated, and the interface among the logic elements existing in the logic circuit to be simulated is shown in Figure 6). Pay attention to changes in the input state values to the game 1 (input side) (step 42), and evaluate the operation of the logic element with reference to the logic operation description 102 created by the logic operation definition means 12 (step 42). 43) Then, the logic element whose output terminal has changed is registered in the force state change logic element list (step 44.4.5).

This is performed for all logic elements (step knob 41). The above state change logic element list is a list of logic elements that propagate state values, and the state change propagation means 14
Referenced in

FIG. 5(a) is a flowchart showing the processing operation of the state change propagation means 4. In FIG. Then, the state value is propagated to the connection destination by referring to the fan-out list that stores the connection destination from the output terminal of the logic element (step 52). This process is repeated until all logic elements on the state change logic element list are processed (step 5).6 The above fan-out list generally has a configuration as shown in FIG. 5(b). That is, the connection destination logic element and input pin name are described in pairs corresponding to the output terminal name.

〔Effect of the invention〕

The logic simulation method of the present invention replaces all logic elements with interface gates with one input and one output for each input terminal and output terminal and executes the simulation, so that the minimum unit data structure to be managed is the input of the logic element. It is determined uniquely regardless of the number of terminals and output terminals, and pointer processing is not required. As a result, processing time is shortened, and since only the minimum required memory area is secured, memory usage efficiency is improved.

[Brief explanation of drawings]

FIG. 1 is a flowchart showing one embodiment of the present invention, and FIG.
3 is an explanatory diagram showing an example of logic operation definition 4: p v>; FIG. 4 is a flowchart illustrating logic game I-evaluation means; FIG. 5 is an explanatory diagram showing the processing operation of LJ' state change propagation means; 511...interface gate generation means;]2...logic operation definition means;
3...Logic gate evaluation means, 14...State change propagation means, 2]-Logic element, 2...Interface gate (input side) 3...Interface gate (output side)

Claims (1)

[Claims] Logic operation definition means for defining logical operation for each logic element existing in a logic circuit to be simulated; and interface gate generation for generating a 1-input, 1-output interface gate for each input terminal and output terminal of the logic element. means for determining the operation of the logic element to which the interface gate belongs based on the logic operation definition means when the input state value of the interface gate changes; and an output terminal of the logic element. and state change propagation means for transmitting the state change to the interface gate connected to the output terminal when a change in state value occurs, and further propagating the state change to a fan-out destination of the interface gate. A logical simulation method characterized by