JPH045594A - Input signal noise removing device - Google Patents

Input signal noise removing device

Info

Publication number
JPH045594A
JPH045594A JP2107096A JP10709690A JPH045594A JP H045594 A JPH045594 A JP H045594A JP 2107096 A JP2107096 A JP 2107096A JP 10709690 A JP10709690 A JP 10709690A JP H045594 A JPH045594 A JP H045594A
Authority
JP
Japan
Prior art keywords
signal
comparator
time
noise
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2107096A
Other languages
Japanese (ja)
Other versions
JP2843640B2 (en
Inventor
Tomohiko Suzuki
智彦 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Furuno Electric Co Ltd
Original Assignee
Furuno Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Furuno Electric Co Ltd filed Critical Furuno Electric Co Ltd
Priority to JP2107096A priority Critical patent/JP2843640B2/en
Publication of JPH045594A publication Critical patent/JPH045594A/en
Application granted granted Critical
Publication of JP2843640B2 publication Critical patent/JP2843640B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Radar Systems Or Details Thereof (AREA)
  • Measurement Of Velocity Or Position Using Acoustic Or Ultrasonic Waves (AREA)

Abstract

PURPOSE:To easily separate and extract an extremely fine target signal from noises by selectively removing a noise which has shorter width than the target signal to be extracted and preventing the target signal from dropping in level. CONSTITUTION:A resistance R and a capacitor C constitute a CR time constant circuit, and a transistor TRQ turns on when the output of a comparator 6 is 'L' to discharge the capacitor C or turns off when the output of the comparator 6 is 'H' to charge the capacitor C with the CR time constant. Therefore, while the output of the comparator 6 is 'H', the input signal (b) of a comparator 10 rises with the CR time constant and when the reference voltage of the comparator 10 is exceeded, the output signal of the comparator 10 goes up to 'H'. Thus, a gate circuit cuts a received signal for the time determined by the relation between the CR time constant and the reference voltage of the comparator to selectively remove short-width noises. Then the level of the target signal is made not to fall and then the fine target signal can easily by separated and extracted from noises.

Description

【発明の詳細な説明】 (al産業上の利用分野 この発明は、レーダーやソナー等に適用され、信号に含
まれている雑音成分を効果的に除去する入力信号雑音除
去装置に関する。
DETAILED DESCRIPTION OF THE INVENTION (Al Industrial Field of Application) The present invention relates to an input signal noise removal device that is applied to radar, sonar, etc. and effectively removes noise components contained in a signal.

(b)従来の技術 レーダーやソナー等において、表示装置に受信映像を表
示する場合、高感度状態では受信信号に外来雑音または
受信系で生じる雑音が混入して、細かなドツト状のノイ
ズが表示されることがあるこのような雑音は見苦しいば
かりでなく、例えば自動レーダープロッティング装置(
ARPA)等において目標物標を自動追尾する際に、雑
音が誤って追尾されて本来の目標物標が追尾されなくな
るといった不都合が生しる。
(b) Conventional technology When displaying received images on a display device in radar, sonar, etc., when the sensitivity is high, external noise or noise generated in the receiving system mixes with the received signal, and fine dot-shaped noise is displayed. Such noise is not only unsightly, but can also be caused by, for example, automatic radar plotting equipment (
When a target object is automatically tracked in ARPA), etc., there is a problem that noise is erroneously tracked and the original target object is not tracked.

このような問題を解決するため、−船釣には感度が若干
低下するように調整し、不要な雑音を軽減するようにし
でいる。
In order to solve this problem, - For boat fishing, the sensitivity is adjusted to be slightly lower to reduce unnecessary noise.

(e)発明が解決しようとする課題 ところが、感度を低下させることによって雑音を低減す
れば、目標信号のレベルも低下するため、ごく微弱な目
標信号が抽出できな(なるといったことも生じる。
(e) Problems to be Solved by the Invention However, if noise is reduced by lowering the sensitivity, the level of the target signal also decreases, which may result in the inability to extract a very weak target signal.

この発明の目的は、目標信号のレベルを低下さセること
なく、雑音を効果的に除去するようにして、上記従来の
問題点を解消した入力信号雑音除去装置を提供すること
にある。
SUMMARY OF THE INVENTION An object of the present invention is to provide an input signal noise removal device that eliminates the above-mentioned conventional problems by effectively removing noise without reducing the level of a target signal.

(d1課題を解決するための手段 この発明の入力信号雑音除去装置は、抽出すべき目標信
号と、この目標信号より幅の短い雑音信号を含む入力信
号を一定のしきい値と比較して、このしきい値を超える
点を検出する信号開始点検出手段と、上記信号開始点か
ら目標信号の幅より短い一定時間分の入力信号を除去す
る短時間信号除去手段とからなる。
(Means for Solving Problem d1) The input signal noise removal device of the present invention compares a target signal to be extracted and an input signal including a noise signal having a width shorter than the target signal with a certain threshold value. It consists of a signal start point detection means for detecting a point exceeding this threshold value, and a short time signal removal means for removing an input signal for a certain period of time shorter than the width of the target signal from the signal start point.

(e)作用 この発明の入力信号雑音除去装置では、信号開始点検出
手段は、入力信号を一定のしきい値と比較して、このし
きい値を超える点を入力信号開始点として検出する。そ
して、短時間信号除去手段は、入力信号開始点から一定
時間分だけ入力信号を除去する。この一定時間は目標信
号の幅より短いため、この一定時間の信号除去処理によ
っては目標信号の一部が除去されるだけて、その大部分
は残存する。一方、雑音は目標信号より時間幅が短いた
め、上記一定時間の信号除去処理によってその殆どが除
去されることになる。したがって、雑音が殆ど除去され
た目標信号のみ含む信号が得られる。
(e) Operation In the input signal noise removing device of the present invention, the signal starting point detection means compares the input signal with a certain threshold value and detects a point exceeding this threshold value as the input signal starting point. The short-time signal removing means removes the input signal for a certain period of time from the input signal starting point. Since this certain period of time is shorter than the width of the target signal, only a part of the target signal is removed by the signal removal process for this certain period of time, and most of it remains. On the other hand, since noise has a shorter time width than the target signal, most of the noise is removed by the signal removal process for a certain period of time. Therefore, a signal containing only the target signal from which most of the noise has been removed can be obtained.

(f)実施例 この発明の実施例であるレーダー装置の主要部のブロッ
ク図を第1図に、その各部の波形図を第2図にそれぞれ
示す。
(f) Embodiment FIG. 1 shows a block diagram of the main parts of a radar device according to an embodiment of the present invention, and FIG. 2 shows a waveform diagram of each part.

第1図において、制御回路1は送信回路2に対して送信
トリガ信号を与える。送信回路2はこのトリガ信号によ
って送信信号をアンテナ3へ与える。受信回路4はアン
テナ3による受信信号を増幅する。時間設定回路5は制
御回路1から与えられるレンジ信号に応じた時間だけ、
後述するタイマ回路7が一定時間を計時するように時間
設定制御を行う。コンパレータ6は受信回路4により受
信された信号を一定の基準電圧Vrと比較して二(it
化する。タイマ回路7はコンパレータ6の出力信号が立
ち上がった時から一定時間(時間設定回路5により設定
された時間)の計時を行う。ゲート回路8はタイマ回路
7による計時時間だけ受信信号のレベルを強制的に0に
し、その他の期間は受信信号をそのまま出力する。表示
回路9はこのようにして雑音除去された受信信号を画面
表示する。
In FIG. 1, a control circuit 1 provides a transmission trigger signal to a transmission circuit 2. In FIG. The transmitting circuit 2 provides a transmitting signal to the antenna 3 in response to this trigger signal. The receiving circuit 4 amplifies the signal received by the antenna 3. The time setting circuit 5 operates only for a time corresponding to the range signal given from the control circuit 1.
Time setting control is performed so that a timer circuit 7, which will be described later, measures a certain period of time. A comparator 6 compares the signal received by the receiving circuit 4 with a constant reference voltage Vr and compares it with a constant reference voltage Vr.
become The timer circuit 7 measures a certain period of time (time set by the time setting circuit 5) from when the output signal of the comparator 6 rises. The gate circuit 8 forcibly sets the level of the received signal to 0 for the time measured by the timer circuit 7, and outputs the received signal as is during the other period. The display circuit 9 displays the received signal from which noise has been removed in this way on a screen.

第2図に示す(a)〜(d)は第1図中に示した(a)
〜(d)の各部の波形例である。同図(a)においてA
およびBは抽出すべき目標信号、Nは雑音信号である。
(a) to (d) shown in Figure 2 are (a) shown in Figure 1.
It is an example of a waveform of each part of - (d). In the same figure (a), A
and B are the target signals to be extracted, and N is the noise signal.

一般に雑音信号は目標信号に比較して振幅レベルが低く
、且つ持続時間が短い。このような受信信号を雑音のレ
ベルより低い一定のしきい値Vrでコンパレートするこ
とによって、同図(b)に示すように二値化信号が得ら
れる。また、(c)に示すように二値化信号の立ち上が
りから一定時間だけ受信信号をカントすることによって
同図(d)に示すように雑音の除去された受信信号が得
られる。
Generally, a noise signal has a lower amplitude level and a shorter duration than a target signal. By comparing such received signals with a constant threshold value Vr lower than the noise level, a binarized signal is obtained as shown in FIG. 4(b). Further, by canting the received signal for a certain period of time from the rise of the binarized signal as shown in (c), a received signal from which noise has been removed can be obtained as shown in (d) of the figure.

次に受信信号が一定のしきい値を超える点から一定時間
を4時するためのタイマ回路の具体的回路例を第3図に
、その各部の波形図を第4図にそれぞれ示す。
Next, FIG. 3 shows a specific circuit example of a timer circuit for counting down a certain period of time from the point at which the received signal exceeds a certain threshold value, and FIG. 4 shows a waveform diagram of each part of the timer circuit.

第3図において抵抗RとコンデンサCはCR時定数回路
を構成し、コンパレータ6の出力力げL”レベルの時、
トランジスタQがオンしてコンデンサCの電荷が放電し
、コンパレータ6の出力が“H″の時、トランジスタQ
はオフしてCR時定数でコンデンサCが充電される。し
たがって、第4図(a)、  (b)に示すように、コ
ンパレータ6の出力が“H”レベルである期間、コンパ
レータ10の入力信号(b)は上記CR時定数で立ち上
がり、コンパレータ10の基準電圧を超えた時、第4図
(C)に示すようにコンパレータ10の出力信号が“H
”レベルとなる。このようにしてCR時定数とコンパレ
ータの基準電圧との関係で定まる第4図中に示すTの時
間だけ、ゲート回路が受信信号をカントすることになる
In FIG. 3, the resistor R and the capacitor C constitute a CR time constant circuit, and when the output of the comparator 6 is at L'' level,
When transistor Q is turned on and the charge in capacitor C is discharged, and the output of comparator 6 is "H", transistor Q
is turned off and capacitor C is charged with the CR time constant. Therefore, as shown in FIGS. 4(a) and 4(b), during the period when the output of the comparator 6 is at "H" level, the input signal (b) of the comparator 10 rises with the above CR time constant, and the reference signal of the comparator 10 When the voltage exceeds the voltage, the output signal of the comparator 10 becomes “H” as shown in FIG. 4(C).
In this way, the gate circuit cants the received signal for the time T shown in FIG. 4, which is determined by the relationship between the CR time constant and the reference voltage of the comparator.

タイマ回路としてはその他に、発振回路とカウンタによ
って一定時間をカウントする回路や単安定マルチバイブ
レーク等を用いることもできる。
As the timer circuit, it is also possible to use a circuit that counts a certain period of time using an oscillation circuit and a counter, a monostable multi-by-break circuit, or the like.

なお、ゲート回路による受信信号の一定時間のカットに
よって、第2図中(d)に示したように、受信信号の一
部もカットされるが、これは例えば第5図に示すような
回路によって元の目標信号の時間幅に戻すことができる
。第5図においてメモリ11はゲート回路8の出力信号
を例えばlスィーブ分記憶し、遅延回路12はメモリ1
1から読み出したデータを上記タイマ回路による一定時
間分だけ遅延させる。OR回路13はメモリ11から読
み出した信号と一定時間遅延した信号とを合成する。な
お、メモリ11、遅延回路12およびOR回路13はデ
ィジタル回路でもよく、アナログ回路であってもよい。
Note that by cutting the received signal for a certain period of time by the gate circuit, a part of the received signal is also cut, as shown in (d) in Figure 2. It is possible to return to the original target signal time width. In FIG. 5, the memory 11 stores the output signal of the gate circuit 8, for example, for l sweeps, and the delay circuit 12 stores the output signal of the gate circuit 8.
The data read from 1 is delayed by a certain amount of time by the timer circuit. The OR circuit 13 combines the signal read from the memory 11 and the signal delayed for a certain period of time. Note that the memory 11, delay circuit 12, and OR circuit 13 may be digital circuits or analog circuits.

以上に述べた実施例は全て1スイープ内における信号の
雑音除去についてであったが、本願発明は方位方向につ
いても同様に通用することができる。以下その例につい
て述べる。
Although all of the embodiments described above have been concerned with signal noise removal within one sweep, the present invention can be similarly applied to the azimuth direction. An example will be described below.

方位方向について雑音除去を行う主要部の回路図を第6
図に、またその各部の波形図および説明図を第7図およ
び第8図に示す。第6図においてコンパレーク6は入力
された受信信号を一定のしきい値で二値化する。ゲート
回路14は第1図または第3図に示したものと同様に二
値化信号の立ち上がりから一定時間だけ信号を力・ノド
するための回路である。ただし前記ゲート回路8とは異
なり論理信号をゲート制御する。メモリ15〜18はそ
れぞれ1スイ一ブ分の二値化された受信信号を記憶する
もので、番号が大きい程前の(古い)受信信号が一時記
憶される。23〜35て示す論理回路はゲート回路14
の出力信号およびメモリ15〜18の各出力信号から、
方位方向における受信信号の内、方位方向に連続する受
信信号をその開始点から一定幅(一定スイーブ数)だけ
除去するための回路である。またカウンタ19〜22は
距離に応じて上記一定幅(一定スイープ数)を変更する
ために、トリガ信号が与えられてから一定時間をカウン
トするものである。
The circuit diagram of the main part that removes noise in the azimuth direction is shown in Part 6.
In addition, waveform diagrams and explanatory diagrams of each part are shown in FIGS. 7 and 8. In FIG. 6, a comparator 6 binarizes the input received signal using a certain threshold. The gate circuit 14 is a circuit similar to the one shown in FIG. 1 or FIG. 3, which controls the signal for a certain period of time from the rise of the binary signal. However, unlike the gate circuit 8, logic signals are gate-controlled. The memories 15 to 18 each store one switch's worth of binary received signals, and the larger the number, the earlier (older) the received signal is temporarily stored. Logic circuits 23 to 35 are gate circuits 14
From the output signal of and each output signal of memories 15 to 18,
This is a circuit for removing continuous reception signals in the azimuth direction by a certain width (a certain number of sweeps) from the starting point of the reception signals in the azimuth direction. Further, the counters 19 to 22 count a certain period of time after a trigger signal is applied in order to change the above-mentioned fixed width (fixed number of sweeps) according to the distance.

メモリ15〜18にはそれぞれ1スイ一プ分の受(8信
号が記憶され、1スイ一プ分の信号が受信される毎に記
憶内容が番号の大きなメモリへ転送されるように構成さ
れている。このため、例えば第8図に示すa点の受信信
号がゲート回路14から出力される時、メモリ15から
b点の信号、メモリ16からは0点の信号がそれぞれ同
時に出力される。
Each of the memories 15 to 18 stores 8 signals corresponding to one sweep, and is configured such that each time a signal corresponding to one sweep is received, the stored contents are transferred to a memory with a higher number. For this reason, for example, when the received signal at point a shown in FIG.

今、例えばカウンタ19,20の出力がともに″H″レ
ベル、その他のカウンタ21〜22の出力がすべて“L
”レベルであるとすると、メモリ15.16の出力は“
H”レベルの時に限りORゲート25.28の出力が“
H″レベルなる。
Now, for example, the outputs of counters 19 and 20 are both at the "H" level, and the outputs of the other counters 21 and 22 are all at "L" level.
” level, the output of memory 15.16 is “
Only when the level is “H”, the output of the OR gate 25.28 is “H” level.
It becomes H'' level.

その他のORゲート31〜34はカウンタ21〜22の
出力が“L”レベルであってインバータ30〜33の出
力が“H”レベルとなることから常に“H”レベルであ
る。したがってこの状態でゲート回路14の出力が“H
”レベルとなった時ANDゲート35の出力力びHルベ
ルとなってゲート回路36は入力信号をそのまま出力す
る。
The other OR gates 31-34 are always at the "H" level because the outputs of the counters 21-22 are at the "L" level and the outputs of the inverters 30-33 are at the "H" level. Therefore, in this state, the output of the gate circuit 14 is “H”.
When the signal reaches the "H level," the output signal of the AND gate 35 becomes the H level, and the gate circuit 36 outputs the input signal as it is.

カウンタ19〜22が上記した条件であれば、3スイ一
プ分方位方向に受信信号が連続しなければANDゲート
35の出力は“L”レベルのままとなって、結果として
2スイ一プ分連続した受信信号は雑音として除去される
(第8図中E1参照)。逆に、3スイ一ブ分以上方位方
向に受信信号が連続したなら、その連続する受信信号の
開始から2スイ一プ分だけ除去された残りの受信信号が
抽出されることになる(第8図中E2参照)。
If the counters 19 to 22 are under the above conditions, if the received signals are not continuous in the azimuth direction for 3 sweeps, the output of the AND gate 35 will remain at "L" level, and as a result, for 2 sweeps. Continuous received signals are removed as noise (see E1 in FIG. 8). Conversely, if the received signals are continuous in the azimuth direction for three sweeps or more, the remaining received signals are extracted by removing two sweeps from the start of the consecutive received signals (8th (See E2 in the figure).

上記カウンタ19〜22は第7図に示すようにトリガ信
号が与えられてからそれぞれ予め定められた一定時間だ
け“H”レベルを保ち、その後“L”レベルとなるよう
にし、しかも番号の大きなカウンタ程“H”レベルの持
続時間を短(するように構成する。このことによって、
遠距離からの受信信号程、除去される時間が短くなり(
除去されるスイープ数が少なくなり)、近距離からの受
信信号程、除去される時間が長く (除去されるスイー
プ数が多く)なる。このようにして距離に関わらず同程
度の雑音除去効果が得られる。
As shown in FIG. 7, the counters 19 to 22 are kept at the "H" level for a predetermined period of time after the trigger signal is applied, and then set to the "L" level, and the counters with a large number are The duration of the "H" level is shortened. By this,
The farther away the signal is received, the shorter the time it takes to be removed (
The fewer sweeps are removed), and the closer the received signal is, the longer it takes to remove the signal (more sweeps are removed). In this way, the same level of noise removal effect can be obtained regardless of the distance.

(g1発明の効果 この発明によれば、抽出すべき目標信号に比較して幅の
短い雑音が選択的に除去され、しかも目標信号のレベル
は低下しないため、微弱な目標信号を雑音から分離して
容易に抽出することができる。したがって、これを例え
ばレーダーやソナー等に適用すれば、遠距離における探
知能力が向上することになる。
(g1 Effect of the invention According to this invention, noise that is shorter in width than the target signal to be extracted is selectively removed, and the level of the target signal does not decrease. Therefore, a weak target signal can be separated from the noise. Therefore, if this is applied to radar, sonar, etc., the detection ability over long distances will be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の実施例であるレーダー装置の主要部
のブロック図、第2図はその各部の波形図である。第3
図はタイマ回路の回路図、第4図はその各部の波形図で
ある。第5図は他の実施例に係るレーダー装置の主要部
のブロック図である。第6図は方位方向について雑音除
去を行うレーダー装置の主要部の回路図、第7図はその
各部の波形図、第8図はその動作を説明するための図で
ある。
FIG. 1 is a block diagram of the main parts of a radar device according to an embodiment of the present invention, and FIG. 2 is a waveform diagram of each part thereof. Third
The figure is a circuit diagram of the timer circuit, and FIG. 4 is a waveform diagram of each part thereof. FIG. 5 is a block diagram of the main parts of a radar device according to another embodiment. FIG. 6 is a circuit diagram of the main parts of a radar device that removes noise in the azimuth direction, FIG. 7 is a waveform diagram of each part thereof, and FIG. 8 is a diagram for explaining its operation.

Claims (1)

【特許請求の範囲】[Claims] (1)抽出すべき目標信号と、この目標信号より幅の短
い雑音信号を含む入力信号を一定のしきい値と比較して
、このしきい値を超える点を検出する信号開始点検出手
段と、上記信号開始点から目標信号の幅より短い一定時
間分の入力信号を除去する短時間信号除去手段とからな
る入力信号雑音除去装置。
(1) Signal starting point detection means for comparing a target signal to be extracted and an input signal including a noise signal with a width shorter than the target signal with a certain threshold value and detecting a point exceeding this threshold value; and short-time signal removing means for removing the input signal for a certain period of time shorter than the width of the target signal from the signal starting point.
JP2107096A 1990-04-23 1990-04-23 Input signal noise eliminator Expired - Fee Related JP2843640B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2107096A JP2843640B2 (en) 1990-04-23 1990-04-23 Input signal noise eliminator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2107096A JP2843640B2 (en) 1990-04-23 1990-04-23 Input signal noise eliminator

Publications (2)

Publication Number Publication Date
JPH045594A true JPH045594A (en) 1992-01-09
JP2843640B2 JP2843640B2 (en) 1999-01-06

Family

ID=14450357

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2107096A Expired - Fee Related JP2843640B2 (en) 1990-04-23 1990-04-23 Input signal noise eliminator

Country Status (1)

Country Link
JP (1) JP2843640B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014132248A (en) * 2013-01-07 2014-07-17 Nec Corp Sonar image processing apparatus, sonar image processing method, sonar image processing program, and recording medium
JP5634404B2 (en) * 2009-09-14 2014-12-03 三菱電機株式会社 Ultrasonic detector

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5634404B2 (en) * 2009-09-14 2014-12-03 三菱電機株式会社 Ultrasonic detector
JP2014132248A (en) * 2013-01-07 2014-07-17 Nec Corp Sonar image processing apparatus, sonar image processing method, sonar image processing program, and recording medium

Also Published As

Publication number Publication date
JP2843640B2 (en) 1999-01-06

Similar Documents

Publication Publication Date Title
GB778288A (en) Improvements in or relating to the electronic counting of objects
GB1399660A (en) Detector having a constant false alarm rate and a method for providing same
EP0132232A3 (en) An mtd digital processor for surveillance radar with a bank of doppler filters and system of thresholds both selectable and dependent on the interference
US3098210A (en) Echo ranging with reference to boundar conditions
JPH045594A (en) Input signal noise removing device
US4114152A (en) Pulse radar apparatus with integration device
JPH0158467B2 (en)
US4369508A (en) Sonar having signal amplitude differentiation and noise suppression
JPS5572880A (en) Processor for sonar video signal
GB1423565A (en) Device for determining in a signal the presence of a given frequency
JP2567493B2 (en) Input signal noise eliminator
US4206410A (en) Automatic frequency control system for single sideband signal receiver
JPS6411917B2 (en)
GB1571540A (en) Pulse radar apparatus
SU1387026A1 (en) Device for counting items
JP2575312B2 (en) Reflection image display
US3803542A (en) Moving target indicator for sonar and frequency measuring means therefor
GB1529624A (en) Detection of atmospheric activity
GB1380679A (en) Processing circuit
JPH01212379A (en) Ftc circuit
JPH0458587B2 (en)
JPH0411184Y2 (en)
JPS6360347B2 (en)
JPH02195286A (en) Ultrasonic detector
JPS6412725A (en) Synthesizer receiver

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees